JPH0363869A - Information processor - Google Patents

Abstract

PURPOSE:To efficiently perform computation by automatically deciding the number of arithmetic processors used in the content of respective computation by measuring processing time per one processing when different computation are performed with respective control processor. CONSTITUTION:Execution units(EXC) 4-7 dedicated for computation are connected to each local bus, and one bus disconnection switch SW 8 is connected. Multiprocessors 1-3 receive instructions and data from a main memory unit 28, and perform processings by using the EXCs. The EXC performs the computation while data for computation from the processor 1 is accumulated in an LM(local memory) buffer 29, and when the computation is completed, sends accumulated data to a local memory(LLM) which performs monitoring in local bus unit. At such the case, when the transfer speed of the data is high, the data is stocked in the LM 29 one by one, and stocked status is judged with a buffer monitor/control means 27, and an instruction is issued to a bus disconnection SW control means 12 and a selector switching control means 16. In such a way, the computation can be efficiently performed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to data processing in a multiprocessor,
In particular, the present invention relates to a device in which each multiprocessor has its own bus, several arithmetic processors are connected to the bus, and parallel processing is performed.

[Conventional technology]

Conventionally, in this type of multiprocessor data processing, a plurality of processors are connected to one data bus. However, although not very common, there is a system like the present invention which has a unique local bus for connecting an arithmetic processor further below a plurality of processors.

In this case, the number of operating processors connected to the local bus determines the number of processors used for each processor.

E. Problems to be Solved by the Invention] In the conventional multiprocessor system described above, since all processors are the same, when processing the same instruction, all have the same processing speed. However, if each executes a different command, the processing time will naturally differ. In other words, a certain processor has already finished processing and is in a state of waiting for an instruction, while a certain processor is still processing.In this situation, the next instruction cannot be executed until all processors have finished. In this case, other processors must be stopped until the processing of the slowest processor is completed.Even if instructions are processed before processing other processors, there will be a large time difference when the final program is completed. As a solution to this problem, it is possible to create processors with high processing speeds and processors with low processing speeds by attaching arithmetic processors under each processor and changing the number depending on the processor.

Therefore, instructions that are likely to take a long time to process can be processed at a faster processing speed. It becomes very inefficient if only a few processors are needed, since there is no flexibility in executing instructions.

[Means to solve the problem]

The information processing device of the present invention has a large number of arithmetic processors in one system, and each of the processors has its own local bus. A common brochure that governs 6/<s to which ys?
The individual control processors are connected by a common bus and receive instructions for the entire system from a common memory.
In an information processing system to be executed, a bus connection means that can connect individual unique busses in all combinations, a bus disconnection means for cutting the length of the bus together with the connection interval of the arithmetic processors, and the above-mentioned arithmetic A buffer is provided in front of the processor, and depending on whether the buffer becomes full or empty, an overflow alarm signal and a buffer empty alarm signal are output, and these signals are monitored in each local memory (L). L
M) Buffer monitoring means, a buffer provided between the control processor and a dedicated bus attached thereto, and means for differentially measuring the amount of data stored in the buffer, the measuring means and each of the LLM buffers; controlling the bus disconnection means and the bus connection means based on information from the monitoring means, determining the number of arithmetic processors connected to each control processor, and notifying each control processor of the arithmetic processors to be controlled by each control processor; have the means.

〔Example〕

Next, the present invention will be explained with reference to the drawings. 5th 1st
The figure is a system configuration diagram of a multiprocessor.

In FIG. 1, multiprocessors 1.2.3 each perform different operations. Each multiprocessor has its own local bus 100, 101, 102. However, as will be described later, control can also be transferred to another processor using this bus. Each local bus has EXECU 7, which is dedicated to calculations.
:>:C) Several 4, 5, 6.7... are connected.

One bus disconnection SW8 corresponding to each of EXC and EXC
is connected. This SW determines the EXC connection on the local bus. Further, only one SW can be made non-conductive in one local bus, and all the remaining SWs are made non-conductive. For example, in FIG. 1, the usable EXCs of multiprocessor 1 are all 4 to 7, but if SW is made non-conductive at 8, only 4 is usable by multiprocessor. By controlling these SWs, the number of usable EXCs in the □-calpath in one processor is determined. Bus disconnection SW control means 12 to 14 are provided to control these SWs for each local bus. In addition, a bus monitoring/bus control means 27 is provided to collectively control the SWs of each bus. Monitor this buffer/
The bus control means is an upper level device of the bus disconnection SW control means, and is necessary for controlling the SW in cases where the bus 12 and -14 cannot be processed independently. 15 is in front of the path selector S and is used to connect buses. This SW allows all combinations. For example, in Figure 1, buses 100 and 101 +
102 and bus 100+1011+102 and so on. 1 to 1. n vs n.

all possible. As a result, the maximum number of EXCs that can be used in one processor is a*b, assuming that a number of multiprocessor stems and b number of EXCs are connected to each bus. This path selector S is controlled by bus selector switching control means 1a. Bus disconnection SW mentioned above
, it is possible to adjust the number of usable EXCs in each processor by using the path selector SW. For example, in FIG. 1, if the multiprocessor 1 requires 6 EXCs, there are 4 EXCs on the local bus 100.
There are only 1 EXC and the remaining 2 EXC must be brought from other buses. Suppose multiprocessor 2 is 2
Assuming that even if EXC is let go, the remaining two are enough to carry out the processing up to now, EXC will take over two of the buses on bus 101. In this case, if it is close to EXC15, 16.
17 is taken, and at 18 the bus disconnection 5W18 is made non-conductive. With this operation, bus 101 is set at 5W18,
Each performs independent operations. Therefore, the EXCs 19 and 20 on the right side of the 5W18 continue to perform the processing of the processor 1. At this time, bus 1/ri SW is bus 10
0 and 101 are connected. Next is data control in each EXC, which is controlled by the LL connected to the top of the EXC.
This is done by controlling the M buffers 21-23. In the LLM buffer, data is stacked in a first-in, first-out manner, and a signal is generated when data accumulates in the buffer to a certain extent or when the data in the buffer becomes empty. These signals 24-26
buffer monitoring means. One buffer monitoring means is arranged for each local bus, and the entire control is performed by 27 buffer monitoring/bus control means.

As an example, let us consider the case of actually performing calculations. Each multiprocessor receives instructions and data from the main memory unit 28 and processes them using EXC.

In this case, the multiprocessors 1, 2.3 perform completely independent operations. EXC used by one processor
In general, this is the EXC attached to the local bus of that processor. Therefore, when n EXCs are attached to one local bus, one processor uses n EXCs as standard. However, the situation changes when each processor has a different processing speed for a single piece of data. For example, in FIG. 1, if the calculations assigned to one processor are extremely difficult, zones will occur in the calculation processing in EXC.

In other words, when the calculation data is distributed and transferred to each EXC in order from 1 and the calculation processing is performed by each EXC, the data accumulates in the LLM buffer because the distribution and transfer is faster than the calculation processing.

As this situation worsens, overflow warning signals are issued from the LLM buffers of all EXCs in the local buffers, and all EXCs become busy. In this state, data cannot be output on the 100 bus. The calculation data from 1 processor is 29 LM (
local memory) accumulates in the buffer. The EXC continues to perform calculations while the data is stored in this buffer, and when the calculation is completed, the overflow warning signal from the EXC is canceled and the data stored in the LM is sent to the LLM. Here, if the data transfer speed is approximately equal to the sum of the processing power of all EXCs on one local bus,
The number of data stocks is almost in a steady state. However, if the data transfer speed is quite high, the data will be stored in 29 LMs one after another. These 29 LMs
27 buffer monitoring of data stock status in /
Based on the judgment made by the control means, a command is output to the 12 bus disconnection SW control means and the 16 path selector switching control means. FIG. 2 shows an internal schematic diagram of the buffer monitoring/bus control means. The signal coming from the buffer (LLM) monitoring means enters 50 LLM statuses. Here, the status of each LLM is written. This data can be read or written by the central controller 51.

Next, the signals received from each LLM are checked by the LM differential detection circuit to determine the rate of increase in data stored in the LM.

Using each of the 53 increase rate comparison circuits, it is possible to detect which local bus is the busiest, or in other words, how much data is stacked on which LM. Further, in step 53, the required number of EXCs for each processor is calculated based on the increase rate of data stacked in the LM. Then, based on the status data of 50 and the information from 52, the EXC diversion determination circuit 54 determines whether the EXC
After adjusting the required number of C, the final E in each processor is
Determine the number of XCs used. In the central control unit of 51, this E
The E to be controlled to each processor by the XC diversion determination circuit.
It notifies XC and also sends a switching signal to the bus selector switching control means 16, bus disconnection SW, and control means through buffers 55 and 56.

In Figure 1, EXC required in l processor
If the number of EXCs is greater than the number of EXCs on the local bus, EXCs belonging to other processors are borrowed. If the number is low, leave it as is, and lend it out if there is a request to lend EXC.

Regarding the EXC rental method, first, in step 27, the number of EXCs to be rented is determined, and in step 27, the EXCs belonging to the bus to be rented are made busy by the number of rented ones. This bu
EXC for sy is performed preferentially from the one closest to SW 15. Next, when the EXC becomes a buy, data no longer enters, so it processes only the data stacked in the LLM buffer, and when the buffer becomes empty, it generates a buffer empty alarm signal. E requested for loan
When a buffer empty alarm signal is generated from all XCs, the bus to the EXC to be rented is disconnected from the bus disconnection SW, and
A request is issued by the path selector S in front of the path selector S. The buffer monitoring/bus control means 27 notifies the processor that control of the EXC has been transferred to the bus, allowing the processor to use the newly borrowed EXC.

Next, the buffer (LLM) monitoring means is shown in FIG. The contents are only the buffer monitoring portion of the buffer monitoring/bus control means.

Figures 5(a) and 5(b) are a bus disconnection SW circuit diagram and a path selector S front circuit diagram, respectively.

〔Effect of the invention〕

As explained above, in a multiprocessor system, the present invention provides a bus connection means that can connect individual unique local buses in all combinations, and a method for cutting the bus length in accordance with the connection interval of arithmetic processors. A buffer is provided in front of the bus disconnection means and the arithmetic processor, and depending on whether the buffer becomes full or empty, an overflow alarm signal and a buffer empty alarm signal are output, and these signals are stored in each unique local memory. local memory (LLM) buffer monitoring means for monitoring;
A buffer is provided between the control processor and the dedicated bus attached thereto; means for differentially measuring the amount of data stored in the buffer; and information from the measuring means and each LLM buffer monitoring means. By having means for controlling the bus disconnection means and the bus connection means to determine the number of arithmetic processors connected to each control processor, and to notify each of the control processors of the arithmetic processors to be controlled by each control processor, respectively. When performing different operations in the control processors of the computer, the number of operation processors to be used is automatically determined depending on the content of each operation by measuring the processing time per process. Therefore, it is possible to perform very efficient calculations. Furthermore, even if the processing time in the processors changes due to a change in the content of the calculation during one calculation processing step, the number of processors is adjusted accordingly. For these reasons, this system is designed to automatically optimize computational efficiency. Economic efficiency is also very good.

John Unit (EXC), 8-11...S
W, 12-14...Bus disconnection SW control means, 1
5...Pass selector SW, 24-26...
... Buffer monitoring means, 27 ... Buffer monitoring/bus control means, 28 ... Main memory.

Claims (1)

[Claims] A common processor that has a large number of arithmetic processors in one system, each of the processors owns its own local bus, connects the large number of arithmetic processors via the bus, and controls the bus to which the arithmetic processors belong. In an information processing system in which each control processor is connected by a common bus and receives and executes instructions for the entire system from a common memory, a bus connection means and a bus connection means capable of connecting individual unique local buses in all combinations are provided. , a bus disconnection means for cutting the length of the bus together with the connection interval of the arithmetic processors, and a buffer provided in front of the arithmetic processor, and an overflow alarm signal and an overflow alarm signal depending on whether the buffer becomes full or empty. , a local memory (LLM) buffer monitoring means for outputting a buffer empty alarm signal and monitoring these signals for each unique local bus; a buffer provided between the control processor and the dedicated bus attached thereto; means for differentially measuring the amount of data stored in a buffer; the measuring means and each of the LLMs;
The number of arithmetic processors connected to each control processor is determined by controlling the bus disconnection means and the bus connection means based on information from the buffer monitoring means, and the arithmetic processors to be controlled by each control processor are connected to each control processor. An information processing device characterized by having a means for notifying.