JPS6218170A - Multi-gradation type printer - Google Patents

Abstract

PURPOSE:To obtain a pseudo halftone output picture having N times of picture elements by applying a clock signal having a period N times that of a clock signal fed to the 2nd address generating circuit to the 1st address generating circuit. CONSTITUTION:An input data stored in a buffer memory 1 is read by the 1st address generating circuit 2 and a threshold value data stored in a threshold matrix storage memory 5 is read from the 2ns address generating circuit 6 respectively and they are inputted to a comparator 7, where they are compared. When input data >= threshold value data, the output of the comparator 7 goes to an H level and is inputted to a recording head 8 and becomes a black level signal to form dots on a recording medium. In applying a clock signal having N times of period to that of a signal fed to the circuit 6 to the circuit 2 by clock frequency division circuit 4, the threshold value data from the memory 5 is read and the input data is read from the buffer memory 1 at a time interval of N times. Thus, the output obtained from the comparator 7 is a pseudo halftone picture signal having picture elements N times those of the input data.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a multi-tone printer capable of forming an image having pseudo halftones on a recording medium using binary dots.

Conventional technology Conventional printers that use dots express halftones by (1) changing the size of the recorded dots, (2) using a threshold matrix of finite size, and expressing halftones from one pixel of the input image. How to determine one pixel in binary display, (3
) A method has been adopted in which the density of one pixel of an input image is expressed using a large number of binary display pixels.

Problems to be Solved by the Invention Among the above-mentioned conventional techniques, method (1) has difficulty in controlling the size of recording dots, making it difficult to express many gradations, and method (2). In this method, one pixel of the human image corresponds to one pixel of the output image, so if the number of pixels of the input image is small compared to the resolution of the printer, the physical size of the output image will be small, and the size will be the same as the input image. If you try to obtain an image larger than that, it is necessary to enlarge the input image in advance to increase the number of pixels, which has the disadvantage of increasing the amount of data transferred to the printer.
In method 3), one pixel of the input image corresponds to a dot pattern of MxN dots to express gradation, so the number of pixels of the output image by this method is Mx the number of pixels of the input image.
This has the disadvantage that the physical size of the output image is determined only by the size of the dot pattern (M x N dots) employed.

The present invention aims to eliminate the above-mentioned drawbacks of the conventional printer, and provides a multi-tone printer capable of forming a pseudo-halftone image at an arbitrary magnification with a simple configuration.

Means for Solving the Problems In order to solve the above problems, the present invention provides a buffer memory for temporarily storing data input to the printer;
a first address generation circuit for generating an address for the buffer memory; a threshold matrix storage memory for storing a threshold matrix to be compared when input data is binarized; and an address for the threshold matrix storage memory. a second address generation circuit for generating a second address, a comparator for binarizing the data obtained from the buffer memory using the data obtained from the threshold matrix storage memory, and a signal obtained from the comparator for recording. It consists of a recording head for forming dots on the medium, a timing generation circuit for supplying two clock signals with different periods to the two address generation circuits, and the like, and supplies the clock signals to the second address generation circuit. By supplying a clock signal having a period N (N: 1, 2.3...) times the period of the clock signal to the first address generation circuit, main scanning of the image input to the printer is performed. A pseudo halftone output image having N times as many pixels as the component is obtained.

Operation The present invention uses the above-described configuration, and the clock signal supplied to the second address generation circuit for generating the address of the threshold matrix storage memory is multiplied by N (N: 1, 2).
,3. By supplying a clock signal with a period of (...) to the first address generation circuit for generating the address of the buffer memory, , data is read from the buffer memory at N times the time interval, so
The output signal obtained from the comparator for comparing the sizes of these two types of data becomes a pseudo halftone image signal having N times as many pixels as the input image, and the image signal thus obtained is sent to the recording head. By inputting the image and forming dots on the recording medium, a pseudo halftone output image in which pixels in the main scanning (X-axis) direction are enlarged N times compared to the input image can be obtained.

In addition, in the sub-scanning (Y-axis) direction, the above process is repeated M times (M: 1) without changing the contents of the buffer memory.
．． 2, 3. (...) By repeating this process, an image having M times the number of scanning lines as the number of scanning lines of the input image is obtained.

Example Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a multi-gradation type printer of the present invention. In FIG. 1, 1 is a buffer memory for temporarily storing input data, 2 is a first address generation circuit for generating an address for the buffer memory 1, and 3 is a clock for generating a clock signal of a constant period. a signal generation circuit; 4 is a clock frequency divider circuit for generating two clock signals having different periods from the clock signal obtained from the clock signal generation circuit 3; 5 is a clock frequency division circuit that is compared when input data is binarized; A threshold matrix storage memory for storing a threshold matrix, 6 a second address generation circuit for generating an address for the threshold matrix storage memory 5, and 7 a second address generation circuit for generating the address of the threshold matrix storage memory 5; a comparator for binarizing data obtained from 5;
Reference numeral 8 denotes a recording head for forming dots on the recording medium based on the signal obtained from the comparator 7.

The input data stored in the buffer memory 1 is read out by the first address generation circuit 2 and added to the input power P of the comparator 7, while the threshold value data stored in the threshold value matrix storage memory 6 is read out by the first address generation circuit 2. The data is read out by the address generation circuit 6 and applied to the other input q of the comparator 7, and the sizes of both data are compared. When the input data is larger than or equal to the threshold data, the output from the comparator is logic level "H", and when this signal is input to the recording head 8, it becomes a black signal. Form dots on the recording medium. At this time, the clock frequency dividing circuit 4 divides the clock signal having a period N times (N=1.2°3...) the clock signal supplied to the second address generation circuit 6 into the first clock signal. When supplied to the address generation circuit 2, the input data is read from the buffer memory 1 at a time interval that is N times the time interval at which threshold data is read from the threshold matrix storage memory 5, so the output signal obtained from the comparator 7 is becomes a pseudo halftone image signal having N times as many pixels as the input data.

FIG. 2 is a block diagram showing another embodiment of the invention.

In Figure 2, 1 is a number (rough memory, 3 is a clock signal generation circuit, 4 is a clock frequency divider circuit, and 5 is a threshold value mask).
The IJ storage memory, 7 is a comparator, and 8 is a recording head, and the above is the same as in FIG. Further, in FIG. 2, 11 is a three-state buffer that controls the connection between the data database of the microprocessor that controls this printer and the buffer memory 1, and 14 is a three-state buffer that is supplied from the clock frequency dividing circuit 4. clock signal S2
The first counter circuit 12 generates the read address of the buffer memory 1, and the address bus 12 generates the address obtained from the address bus B of the microprocessor controlling this printer, and the first counter circuit 14. Data selector circuit for selecting either one, 1
5 is a clock signal S1 supplied from the clock frequency divider circuit 4, and a threshold value WI is set to the IJ storage memory 5.
A second counter circuit 13 for generating a read address is a delay line for slightly delaying the clock signal supplied to the second counter circuit 15 to generate a clock signal S7 for the recording head 8. be.

Three-state buffer 11 and data selector circuit 12
By appropriately controlling the buffer memory 1, the microprocessor can access the buffer memory 1, and input data can be written to the buffer memory 1. When the writing of the predetermined number of data is completed, the three-state buffer 1 is
1 and the data selector circuit 12,
The backup memory 1 is separated from the microprocessor, and the input data S4 is read out according to the address obtained from the first counter circuit 14 and applied to the P input of the comparator 7. On the other hand, the threshold value data S3 stored in the threshold value matrix storage memory 5 is transferred to the second counter circuit 15.
The magnitude of the data read out by and applied to the Q input of the comparator 7 and applied to both inputs is compared. If the data S4 applied to the P input is greater than or equal to the data S3 applied to the Q input, the output S6 of the comparator 7 becomes "H" at the logic level; otherwise, it becomes "L".
'', which is input to the recording head 8 by the clock signal S7 obtained from the delay line 13.

At this time, by appropriately controlling the clock frequency dividing circuit 4, the data read interval of the buffer memory 1 is set to N times the threshold value matrix storage memory 5 (N=1.2.3...
), it is possible to obtain a pseudo halftone image having N times as many pixels as the input data.

FIG. 3 is a timing diagram illustrating the signal states of each part in the embodiment shown in FIG. 2. In Figure 3, S
l is a clock signal supplied to the second counter circuit 15;
S2 is a clock signal supplied to the first counter circuit 14, S3 is threshold data read from the threshold matrix storage memory 6, S4 is input data read from the buffer 7 memory 1, S6 is an output signal obtained from the comparator 7, S
7 supplies a clock signal for inputting the output signal S6 to the recording head 8.

Effects of the Invention As described above, according to the present invention, a pseudo halftone image can be formed at an arbitrary enlargement ratio with an extremely simple circuit configuration, and is extremely useful in practice.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a multi-tone printer according to an embodiment of the present invention, FIG. 2 is a block diagram showing another embodiment of the present invention, and FIG. 3 is a block diagram showing various parts of the printer shown in FIG. 2. FIG. 1... Buffer memory, 4... Clock frequency divider circuit, 6... Threshold matrix storage memory,
7... Comparator, 8... Recording head. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3

Claims (1)

[Claims] A buffer memory that temporarily stores input data, a first address generation circuit that generates an address for the buffer memory, a threshold matrix storage memory that stores a threshold matrix for binarizing the input data, and the threshold matrix. a second address generation circuit that generates an address of the storage memory; and a second address generation circuit that generates an address of the storage memory;
A comparator for converting into a value, a recording head for forming dots on a recording medium based on the signal obtained from the comparator, and two address generation circuits having different periods.
By supplying the first address generation circuit with a clock signal having a cycle that is an arbitrary natural number multiple of the clock signal supplied to the second address generation circuit. , a multi-gradation printer capable of obtaining a pseudo-halftone image having an arbitrary natural number times as many pixels as the main scanning component of image data input to the printer.