JPH0769681B2 - Halftone dot processor - Google Patents

Description

Description: TECHNICAL FIELD The present invention is intended to automatically perform shading processing by electronically shading a photographic image having light and shade in printing of newspapers, magazines and the like. And a halftone dot processing device.

2. Description of the Related Art In printing newspapers and magazines, natural images with gradation are expressed as halftone dot images that are converted into binary halftone dots of different sizes. Normally, this halftone dot processing is performed by exposing a natural image by overlaying a halftone dot screen, and for example, binarization is performed by binarizing the natural image with points that exceed the halftone dot density as black and those that do not exceed the halftone dot white. ing. This halftone dot processing can be performed by optical exposure as described above, but recently, electronically digitized multi-valued image data is electronically halftone dot processed by using a halftone dot pattern. I'm getting an image. To generate this halftone dot pattern, an analog method is used to spatially generate on the xy plane using a periodic function such as a sine wave or a triangular wave having an offset level, and the same periodic function is digitally calculated. There is a way to occur.

Moreover, even in the same digital calculation generating means,
A means for calculating the total size of a halftone dot pattern and a means for generating a small block area forming one halftone dot and developing it in accordance with the halftone dot angle have been considered.

First, the analog method has the advantage that a simple periodic function can be generated and used and the hardware configuration is simple, but it is difficult to generate a slightly modified periodic function, and accuracy, It is inferior in stability. In FIG. 2, a triangular wave periodic function is generated, and the amplitude is changed for each line (l _{1 to} l ₁₀ ), and the change corresponds to the same triangular wave periodic function. In Fig. 2 (A)
Shows that the amplitude of the triangular waveform changes as the lines are moved. When a certain image level is given, the binarization process is performed for each line, and the binarized signal can be obtained for each line as shown in (B). . When this binary signal is recorded by a binary recording device such as a laser beam printer, a halftone dot image as shown in (C) is output.

Further, as a simple example in the case where the halftone dot processing is performed by the halftone dot pattern which is calculated or output in advance for all sizes by the digital system, a halftone dot pattern as shown in FIG. is there. In this example, it is indicated by a cosine wave, and Zx = 0.5 · COSwX is given on the X axis, and Y
A halftone dot pattern generated by synthesizing on the XY plane by giving Zy = 0.5 · COSwY about the axis is shown.

As a result, a halftone dot pattern spatially expressed by the equation (1) is generated on the XY plane.

Z = Zx + Zy = 0.5 · (COSwX + COSwY) (1) In FIG. 3, the small black and white dots indicate the centers of the black and white dots, respectively.

Problems to be Solved by the Invention In this way, it takes time to generate a large-sized halftone dot pattern by calculation, and it is difficult to perform halftone dot processing of a grayscale image while generating it in real time. In particular, in a color image, in order to reduce the moire pattern that occurs due to periodic overlapping between color halftone dot patterns, it is necessary to perform color halftoning processing in which each halftone dot has an angle, It becomes more difficult to perform the calculation of the halftone dot pattern at high speed.

Therefore, one dot is prepared in advance corresponding to each poison and the number of screen dots, and a large size dot pattern is generated while arranging the dots according to the dot angle. Methods are being considered. According to this method, a halftone dot pattern can be generated by expanding halftone dots prepared in advance, but as shown in FIG. 4, it is necessary to develop the halftone dot pattern in consideration of the dot gradient according to the halftone dot angle. However, there is a drawback that the control circuit becomes complicated.

In FIG. 4, halftone dots are composed of A and B types of matrix, and halftone dot angles are represented by dot gradient b / a. Therefore, when expanding the small matrix A, it is necessary to expand while maintaining the halftone dot angle θ = tan ⁻¹ (b / a) while considering the periodicity of a and b. This complicates the halftone dot pattern generation circuit. Usually, the shape of the inside of the small matrix A as shown in FIG. 4 is often not neatly formed according to the halftone dot angle. For this reason, the generated halftone dot pattern is not clearly continuous on the grid, so that the recording result becomes conspicuous.

In view of the above-mentioned drawbacks of the prior art, the present invention does not calculate a large-sized halftone dot pattern in real time in a digital halftone dot processing apparatus which is excellent in accuracy and stability without depending on the analog method. In addition, a halftone dot processing apparatus for generating a large-sized halftone dot pattern by a simple hardware configuration without paying attention to the halftone dot angle even when a small halftone dot pattern is developed and performing a halftone dot processing is provided. It is a thing.

Means for Solving Problems According to the present invention, when converting to a binary image for controlling on / off of dots of a recording device in accordance with input grayscale image data, a network designated in advance is used. Storage means for storing a halftone dot pattern generated by the number of lines and halftone dot angle, a storage memory for storing a repeating halftone dot pattern of a rectangular area of a designated size, and a writing / reading address for the storage memory A first address generating circuit, a line buffer circuit for temporarily storing the input grayscale image, a second address generating circuit for generating write and read addresses for the line buffer circuit, and an image from the line buffer circuit The above object is achieved by providing data and a comparison circuit for reading and comparing halftone dot pattern data from the halftone dot pattern storage memory. It is a thing.

With the above-described structure, the present invention generates a halftone dot pattern having a minimum required size in accordance with a predesignated halftone dot number l, a halftone dot angle θ, and a recording density k of a recording device. By extracting a halftone dot pattern of a square area having a size corresponding to a uniquely determined repetition period from the halftone dot pattern, the storage capacity is reduced without generating all the large size halftone dot patterns. Then, the extracted halftone dot pattern of the square area is set in the storage memory as a repeated halftone dot pattern so that it can be developed only by repeatedly reading when a large size halftone dot pattern is generated.

Example Hereinafter, an example of the present invention will be described with reference to FIG.

FIG. 1 (A) shows a laser beam printer in which a grayscale image composed of multi-valued image data input via the microcomputer 101 is subjected to halftone dot processing to be converted into binary halftone dot data. 2 is a block diagram of a halftone dot processing apparatus in one embodiment of the present invention for recording a grayscale image with a binary image.

First, from the halftone dot number 1 halftone dot angle θ and the halftone dot pattern corresponding to the recording density k of the recording device stored in the storage device 100, a square area of a size corresponding to the square of the halftone dot pitch d is selected. The halftone dot pattern is set in the halftone dot pattern storage memory 103 via the data line 102 from the microcomputer 101.

The next input gray-scale image data for one line is the data line
Write to one line buffer 104 via 102. Writing to the two line buffers 104 and 105 is switched every time a grayscale image for one line is input. From the X address generation circuit 106 and the Y address generation circuit 107, one halftone dot pattern is read from the halftone dot pattern storage memory 103 according to the generated X and Y read address 108.
At the same time, one grayscale image data is read from the line buffer memories 104 and 105 according to the read address 110 of the line buffers 104 and 105 generated by the address generation circuit 109. Reading and writing of the two line buffers 104 and 105 are performed alternately. That is, when the grayscale image data is written in one line buffer, it is read from the other line buffer. The grayscale image data of the line buffer currently read out of the two buffers 104 and 105 is selected by the selector 111 and input to the comparison circuit 112. On the other hand, the halftone dot pattern data 113 read out from the halftone dot pattern storage memory 103 is also input to the comparison circuit 112 to compare the levels, and the multi-value grayscale image data is converted into binary halftone dot image data. To be converted. The binarized halftone data 114 is 1
One bit per dot is output in the corresponding bit serial format. The halftone dot data 114 is the shift register 115.
Input to the laser beam printer 117 and packed into 8-bit parallel data 116 and supplied to the laser beam printer 117 to record a binary halftone dot image.

In the above configuration, how the size of the repetitive halftone dot pattern to be written to the halftone dot pattern storage memory 103 is determined will be described with reference to FIG. 1 (B).

First, from the specified halftone dot number and halftone dot angle and the recording density of the printing apparatus, the halftone dot angle θ [degree] and the halftone dot angle θ [degree] approximated by the dot gradient b / a expressed by an integer number of dots in the vertical direction b and the horizontal direction a The number of lines 1 [lines / inch] is expressed by the equations (2) to (3).

(However, d is called a halftone dot pitch and is represented by the following formula (4).

Therefore, as shown in FIG. 1 (B), the center P of one dot is
The length Td [dots] from when the image is horizontally scanned to the point where it first reaches the center Q of the halftone dot is uniquely determined as follows.

First, from the halftone dot P to the halftone dot angle θ (that is, When the same halftone dot is repeated in the direction of, the halftone dots are repeated by the number of integers a, and the center of the a-th halftone dot is O and OP
Let Ta be the dot length. Next, when repeating the same halftone dot from the point O on a straight line that passes through the point O and is perpendicular to the straight line OP, the halftone dots are repeated by the number of integers b, and the center of the bth halftone dot is set to Q. And the length of OQ is Td [dot].

Therefore, the dot angle is , And the straight line PQ is a horizontal axis parallel to the X axis. Also PQ
The length Td [dot] between them is expressed by the equation (5).

Td = d ² determined from the integers a and b is also an integer, and when the halftone dot is repeated at the dot gradient b / a from the center of the halftone dot at the point P, even at the point Q distant by d ² [dots] in the horizontal direction again. Match the center of the halftone dot. This means that in the horizontal direction d ² [dots]
It shows that the halftone dot pattern of the size is periodically repeated. A similar point in the vertical (Y) direction from point P is point S
Then, the length between PS becomes exactly the same Td = d ² . Therefore, dot patterns of d ² [dot] size are periodically repeated in the vertical (Y) direction. A square dot pattern memory with a side of d ² [dots]
By repeating this in 103 in the X and Y directions, a halftone dot pattern of an arbitrary size can be generated.

In the table below, when using a recording device with a recording density of 400 [dots / inch], a dot gradient and a halftone dot pitch and a repeating square area when generating a halftone number within the range of 50 to 140 [lines / inch] The calculated relationship of the size of one side is shown.
The maximum size of one side of the repeated square area of the halftone dot pattern that can be generated from the table is 64 [dots], and if this halftone dot pattern is stored in the halftone dot pattern storage memory 103,
A large-sized halftone dot pattern of 0 to 140 [lines / inch] can be generated. Similarly, when the recording density of the recording device is 454.5 [dots / inch] and 909 [dots / inch], the size of the repeated square area is 82 [dots] and 328 [dots], respectively.

Further, in the table, a halftone dot pattern having a dot gradient of a = 7 [dots] and b = 2 [dots] has a halftone dot angle of θ = 15.95 [degrees], a halftone dot pitch of 7.28 [dots], and a halftone dot pitch. It is shown that the number of lines is 54.94 [lines / inch], and the size of one side of the square area of the repeating halftone dot pattern is 53 [dots]. Recording density 400 [dot /
As described above, the size of the repeating halftone dot pattern is 64 [dots] at maximum when the halftone dot number of 50 to 140 [lines / inch] is expressed in [inch].
The capacity of 3 is only 64 × 64 [bytes], that is, 4096 [bytes] when one dot represents the gradation of 256 gradations in 1 byte. Under the same conditions, when recording density is 454.5 and 909 [dot / inch], 6724 [byte] each
And 107584 [bytes]. Therefore, these storage capacities correspond to the maximum size recorded by a recording device with a recording density of 909 [dots / inch], which is equivalent to A3 size, that is, 16.5 x 1
Since the total halftone dot pattern capacity for a 1.7 [inch] target is about 152 MB, a storage capacity of about 1/1500 is sufficient. Moreover, a large-sized halftone dot pattern can be generated only by constructing a simple address control circuit from the X address generating circuit 106 and the Y address generating circuit 107.

EFFECTS OF THE INVENTION As described above, the present invention stores a periodic repeating pattern of angled halftone dots in a halftone dot pattern storage memory, and periodically reads halftone dot pattern data from the halftone dot pattern storage memory. By providing the address control circuit for outputting, a halftone dot pattern of an arbitrary size can be generated. As a result, the hardware circuit can be simplified and the cost can be reduced, and an arbitrary large-sized halftone dot pattern can be generated at high speed, so that it can be flexibly dealt with.

[Brief description of drawings]

FIG. 1 (A) is a block connection diagram of a halftone dot processing apparatus according to an embodiment of the present invention, FIG. 1 (B) is a conceptual view showing a generation state of a halftone dot pattern by the same apparatus, and FIG. FIG. 3 is a waveform diagram showing the halftone conversion processing by the analog method, FIG. 3 is a conceptual diagram when a halftone dot pattern of all sizes is generated by calculation by the conventional digital method, and FIG. 4 is a conventional one halftone dot. It is a conceptual diagram which shows the halftone dot pattern generated by developing. 100 ... storage device, 103 ... halftone dot pattern storage memory, 10
4,105 ... line buffer memory, 106,107 ... X, Y address generation circuit, 109 ... address generation circuit, 111 ... selector, 112 ... comparison circuit, 118 ... clock generation / timing control circuit.

Claims (3)

[Claims] 1. A halftone dot pattern storage memory for storing a repetitive halftone dot pattern of a rectangular area of a designated size among halftone dot patterns prepared in advance according to a designated number of halftone dots and a halftone dot angle. A first address generation circuit for generating write and read addresses to the storage memory, a line buffer circuit for temporarily storing input multi-valued image data, and a write and read address for the line buffer circuit A second address generating circuit, and a comparator circuit for binarizing the multivalued image data by reading and comparing the multivalued image data from the line buffer circuit and the halftone dot pattern data from the halftone dot pattern storage memory. And a halftone dot processing apparatus comprising a control circuit for generating clock signals and timing signals for the respective circuits. 2. Each halftone dot of the halftone dot pattern stored in the storage means is represented by an array consisting of a plurality of multivalued element data, and the halftone dot angle θ is a horizontal distance a between two adjacent halftone dots. And the pitch tan ^-1 (b / a) indicated by the number of each element of the vertical distance b, the pitch d indicating the length between halftone dots is When the recording density of the recording device is k, a halftone dot pattern having a halftone dot number l of k / d is generated, and the vertical and horizontal array size N of the generated halftone dot pattern is at least d ² (or
The halftone dot processing apparatus according to claim 1, wherein the size is equal to or larger than a ² + b ² ). 3. A halftone dot pattern to be written in a halftone dot pattern storage memory is read out from the stored halftone dot pattern in terms of vertical and horizontal size d ² and written in the halftone dot pattern storage memory. The halftone dot processing apparatus according to claim 1, wherein the multi-valued image data is binarized by halftone dot processing while repeatedly reading out vertically and generating a virtual large size halftone dot pattern.