JPS5880639A - Method for recording screen plate image - Google Patents

Abstract

PURPOSE:To enable the number of the image elements of quantized indistinct dots to be selected independently of the number of the image elements of the other screen angle, by selecting the number of exposure light beams contained in a unit record scanning width in accordance with a screen pitch. CONSTITUTION:Data of dots corresponding to the plural image elements of indistic quantized dots are read out at the same time in synchronism to image elements signals (e) from a memory device 21 having said dots recorded, and plural exposure beams L1-L10 are controlled in accordance with signals obtained by superposing these dot data on said signals (e) to record a screen plate image. At that time, the number of exposure light beams contained in a unit record scanning width is selected in accordance with a screen pitch, and these selected beams are controlled in accordance with an optional signal among signals obtained by superposing said dot data on said signals (e).

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic halftone image recording method in a halftone image duplication and recording apparatus for printing plate making.

Conventionally, in a recording device that reproduces a halftone image directly by electronic control, an image signal having continuous gradation is obtained by scanning a contour screen in order to convert it into an image signal for recording a halftone image. A halftone signal equivalent to the halftone pattern is separately generated, and both signals are superimposed to obtain a signal for recording the halftone pattern.

Various types of means for generating this mesh signal have been developed, and recently, as solid-state memory devices have become more popular and cheaper, methods using solid-state memory devices have become mainstream.

However, when using a solid state memory device, the halftone dots corresponding to the blurred halftone dots of the contact screen must be quantized and stored. Therefore, the basic properties of the mesh structure created by the mesh signal emitted by the solid-state memory device are determined in advance by the conditions for proper quantization when quantizing blurred halftone dots. .

The conditions include, for example, the screen angle, density expression stage, and screen pitch coefficient. When quantizing blurred halftone dots, the screen angle θ must satisfy the condition that nθ− (m, k is an integer).

The number of pixels (determined by 81, and the maximum density expression stage is determined by the number of pixels S-m" -1-
k”.

Since the mesh structure is a repeating pattern of square blurred halftone dots, the screen pitch corresponds to the square root of the area of the unit halftone dot area. number of pixels (square root of Sl v'
i = q is determined as the screen pitch (coefficient α of Pi).

On the other hand, mesh plates for color printing usually have screen angles of 0°, 45°, and 15° for 4-color printing.

A set of 75° is used and the screen pitches (Pi) of this set are required to be equal.

However, when quantizing blurred halftone dots, the appropriate conditions for quantizing as described above are given for each screen angle,
It becomes difficult to make each screen pitch (P) equal.

so, 841.818 and each screen pitch coefficient α0°α4. , α2. If you ask for wo, it will look like this:

S. −m2, α. -y':
= m.

541-2 mis α41 ”'&='V
'T mis -8+s-m''+s ten+a α
” -6-rIn addition, when the screen angle is 75°,
Consider a screen angle of -15°.

In this way, each screen pitch coefficient αO9α41 . α・6 is 16 integer value ms, m4s
, mis.

No matter how you choose k1w, it is impossible to match them. Therefore, in reality, the number So of each pixel.

Each integer value m0 is selected such that 841 , 811 approximate - the screen pitch coefficient α. ,α,5. α4.
It is approximated.・The above-mentioned screen pitch coefficient α refers to the effective length t of the length of one side of a pixel determined when recording a quantized pixel on a photosensitive material when determining the actual screen pitch P. This is the coefficient multiplied by the actual screen pitch P-αt.

Furthermore, when the blurred halftone dots are quantized and stored in an integrated memory device to generate a mesh signal, the repeating nature of the mesh structure is used, and the size of this cycle has a significant effect on the memory capacity. do.

For example, the integer value me for each screen angle.

If mis , mis , k+s represent the number of pixels lined up in one period of each screen angle, the angle O° is me
, angle 45° is 2 mis, angle 15° is m:s +
k's, and the one with a screen angle of 15 degrees is significantly larger and has a larger memory capacity.

Therefore, each integer value mo... is selected such that Sl is small in m: 10, but this m:s 10's is
Since it corresponds to the number of pixels StS, if this value is small,
The density gradation expression level decreases.

However, screen angles of 0°, 15°, and 75' are usually used for each of three colors: yellow, magenta, and cyan, and these color versions have lower densities than the black version with a screen angle of 45°. It is also possible to lower the gradation expression level.

Therefore, it is possible to reduce the memory capacity by setting the density expression stages at a screen angle of 15° and -15° lower than the density gradation representation stage required for a screen angle of 45°. However, as mentioned above, when the density gradation expression stage is changed, the condition that the number S of pixels is approximated cannot be satisfied, and the clean pitch coefficient α is no longer approximated. Satisfying the above conflicting demands,
At each screen angle ^Wt, the number S of pixels of the quantized blur halftone dot is selected individually, regardless of the number of pixels at other screen angles, and ζThe effective screen of each halftone image recorded This invention relates to a halftone image recording method in which the pitch is approximated, and examples thereof will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of a halftone image duplicating and recording apparatus showing an embodiment of the method of the present invention, in which the main recording scanning means for reproducing images is driven by a motor (1). Projecting an exposure light beam (5) onto a rotating cylinder (2) and a photosensitive material (4) facing the circumferential surface (3) of the cylinder (2) and wound around the circumferential surface (3), and In the axial direction of the cylinder (2), there is a recording head (6) that is sent in synchronization with the rotation of the cylinder (2), a threaded rod (γ) for feeding the recording head (6), and the threaded rod (7). ) and a feed motor (8) that drives the motor.

The rotation of the cylinder (2) is measured by a rotary encoder (10) attached to the cylinder shaft (9). The rotary encoder (10) is connected to one of the cylinders (2).
A one-rotation pulse (gl) generating means that generates one pulse at a predetermined position for each rotation, and a number of pulses per rotation for each rotation phase that equally divides the phase of one rotation. It is equipped with a phase pulse (gl) generating means. - The exposure light beams (5) projected by the recording head (6) are aligned in the feeding direction of the recording head (6), and each
It consists of a collection of a plurality of light beams that are individually controlled in binary values (ON or 0FF).

Such an exposure light beam (5) is a light beam (L.
Branches to (L,,).

These light beams (L,) to (L, .) are connected to shutter devices (ta,) to (131) whose optical paths are electronically controlled to open and close.
@) K Input each shutter device (tag) ~ (13
,. ) output light beam when the optical path is open (L;) ~ (L;.)
U, 10 optical fibers (141) to (14
+o) input to one end surface.

The other ends of the optical fibers (14,) to (141,) are guided to the recording head (6), and their end faces are arranged horizontally in the order of arrangement of the corresponding light beams (Ll) to (L, ,). They are arranged in rows and placed on the optical input surface of the zoom lens (b).

The output light beams (L:) to (L.:) emitted from the end faces of each optical fiber (14I) to (14+o)
) is imaged on the surface of the photosensitive material (4) by a zoom lens (1d1).

The output light beams (L',) to (L. They are arranged in order corresponding to the beams (L).

The zoom lens ■) has an output beam of (L,) ~ (L,,)
This is to change the projection magnification of the output light beam (L,) to (Ll,) while it is focused on the imaging plane.
effective light beam width (W
Change l.

Zooming of the zoom lens (15) is performed using servo motor α.
6) Or controlled by a pulse motor.

The servo motor 06) has a screen pitch (P
Based on the desired value of l, how many output beams (t,
The screen pitch setting control circuit 0 controls the projection magnification by assigning ',) to (t,,',).
7) is driven by the control signal (g4)t.

The upper scanning width (b) is calculated by combining the scanning width W, the scanning width (scanning line pitch) of the original image scanning means when obtaining the image signal (el) to be recorded, the magnification of the original image versus the duplicate image, and the magnification factor. This scanning width (5) determines the resolution of 111 images.

Note that the image signal input to the above device (el is a digital image signal output from the original image scanning means in real time, or a digital image signal stored in the memory device, is read out in synchronization with the recording scanning means. It may be any digital image signal.

The servo motor α6) or the pulse motor controls the zoom lens μs so that the scanning width W of the recording scanning means includes exactly an integer (n) output beams (L, )...
) controls the projection magnification.

This servo motor α6) is controlled by screen settings.

Based on the desired screen pitch (Pl value) set in the control circuit (17), the value of the scanning width W specified in advance, and the value of the number of output light beams (n), the CPU (Central Processing Unit) ) Q8) and is controlled by the servo motor control signal (g4) obtained as a result.

Note that this control itself is not the gist of the present invention, so a detailed explanation thereof will be omitted.

The screen pitch setting control circuit 0I7) receives the control signal (
gs) is output to the feed motor (8) so as to send the recording head (6) with a -scanning width, and output beams (L':) to (L, ,)
Effective beam width (period c71 corresponding to W - 岑○) according to the number of (n>) The O P, L, L circuit surface that outputs to the control loop)-path (to) is equipped with a programmable counter whose count value is set by the control signal (g), and the P,
L, L, circuit r19) fd, s Converts the cycle of the phase pulse (g2) output by the rotary encoder into a clock pulse (Cυ) with a cycle (T1) corresponding to the set count value of the counter.

The clock pulse (e,) and the one revolution pulse (g,) of the rotary encoder 10) are sent to a timing circuit. The timing circuit (20) outputs various control pulses (tl) to (t4) shown in FIG. (The pulse (g,) is waveform-shaped and, in synchronization with the clock pulse (C1), is converted into a start pulse (ct) vc for accurate positioning.

Clock pulse (C:) , the above-mentioned Qn < , each output beam (L, ) ~ (L,
, ) effective beam width (the period () corresponding to the distance equivalent to @)
The beam width (season and period (T, ) is
This corresponds to the feeding direction of each pixel of the quantized blur halftone dot and the length of each side in the scanning direction, which is 4.

One start pulse (et) is obtained at the reference position of the recording cylinder (2), and this pulse generation position corresponds to the start end of the exposure scan of the photosensitive material (4).

Next, the mesh signal generating means will be explained.

Each data of the mesh structure of the mesh pattern and the mesh density for converting into the mesh area ratio is equal to the number of light beams (Ll) to (Ls, ) whose opening and closing are controlled, and each data is individually addressed. Multiple controllable memory blocks (2
Data of a plurality of meshes arranged on mutually adjacent light beam scanning lines is recorded in a screen pattern memory device (21) having 1υ to (21+6).

Screen pattern memory (GL) is a solid-state memory device, ROM, (read-only memory), or RAM.
(Random Access Memory) and its individual memory blocks (211) to (21,
. ) is the desired screen angle, e.g. 0°.

Data for 45°, 15', and 75° are recorded for each screen angle with respective address spaces given.

The data read from each memory block (21,) to (211°) is the number of per-word locations corresponding to the humidity of the blurred halftone dot, which is used to determine the halftone dot size (c, halftone area ratio). This is the data. Each of these data is stored in each memory block (211) to (211) in the pattern extraction device.
A comparator (221
) to (22Io).

The image signals (el) commonly input to each comparator (221) to (22+.) id and the corresponding memory block (2h) to ( 21, .), and outputs a binary signal, and each of these binary signals is
It is sent to the next stage multiplex circuit 43).

The multiplex circuit @8) connects each shutter device (131
) to (+3io) and corresponding 10-channel multiplexers (23,) to (23,.), and each multiplexer (231) to (2310) has a corresponding one of all comparators (221) to (2216). Each output signal is input.

The outputs of the multiplexers (230 to (23to) are respectively output from shutter drivers (24,) to (24Io) that drive the opening and closing of the shutter devices (131) to (13+e).
) @ via shutter device (ta,) ~ (131o)
Control opening and closing.

In the above multiplex circuit (28), each data outputted simultaneously from each memory block (21,) to (21, . It is selectively controlled so that L, ) to (L, , ) can also be controlled.

The address of each memory block (21,) to (21,.) is determined by the selector (25,) to (251°) corresponding to each memory block (211) to (21+a) of the two input channels in the address selection circuit. Through this, two types of address signals can be selectively used.

Two types of address signals are generated by the first and second address counters (Yl) and (Y, ) of the address generation circuit-m. Both address counters (Y, ) (Y,
) l'i is initial preset immediately after the start pulse (C2) is generated so as to have a required count difference in advance.

-Hiho address generation circuit (25+, screen pattern memory device 1211 and multiplex circuit)
is each circuit (25) determined in advance according to the desired network structure.
(zll ul(') Ill ill Ibaraki controls the generation of the start pulse (C1) to be short, and each control data of Ibaraki for each circuit is recorded in the screen control memory device W (271).

The screen control memory device (z7) includes each circuit (25
1 (211 Yu) Each control data of Liu's control element is one word each, arranged in a series in Toronome's ++myo,
One word of screen control 41 data recorded as one word of screen control data in the screen control memory device (fil) has a word length of 16 bytes, and one word of -7 has a word length of 8 bits and 1 byte each. The corresponding address space source can be extracted for each byte.

From this screen control #memory device rIt@7), one word of the screen control data that is leaked out one byte at a time is sequentially sent to the shift register (5), and when all one word is read out, it is shifted. In the register (to), control data for each control element in the screen control data is stored at a predetermined register position.

As shown in Fig. 4, the shift register μs) outputs 1 byte of parallel bits between each stage of the shifted register for each byte, and outputs one word of screen control data. Output parallel bits.

The output bit line of the shift register μs) is connected to each predetermined control terminal of the address generation circuit (26), the address selection circuit (23), and the multiplex circuit (23),
It is distributed as control data for the control elements of each circuit (26,1 (251□)).

The address control of the screen control memory device (attached to the screen control memory device) is performed by a first address counter 1 that specifies an address corresponding to one word of screen control data, and the first address counter El'! The area specified by & is divided by 1 byte, and the area is controlled by a second address color/measurement for sequentially specifying addresses.

The second address counter (8o) has a timing circuit (
Goods)) outputs! Measure the III control pulse (t,),
The address is specified using the count value.

Control rAI pulse (t*)H, start pulse (C,)
Immediately after, in synchronization with that pulse (C1), 1611M
? It is created by extracting the control pulse (C1). At this time, the control pulse (1,) obtained during the period when the control pulse (t,) 1 is output is obtained by reading out the screen control memory device (271). enable possible.

This control pulse (t2) is also sent to the shift register μs), and this pulse (t,) is synchronized with the readout of the screen control memory device Ctn.
When bit data is taken into a register (for example), it is sequentially transferred to the lower digits.

As shown in FIG.
+5) (ahs).

Each line counter (31,) to (31?ri 1”J:
, 0° line counter (atO), a programmable m-ary counter is formed by a counter (to) and a comparator (to). The m-adic counter counts the start pulse (C) and counter C321
The count value is the comparator (34 comparison setting value (m,)
The limit value is set to 11.

The comparison setting value (m,) (m, =) (m, -) (m'-) of each line counter (3111) to (:Al?I) is based on the repetition period of the mesh turn described later. This value is determined in advance and is given from a required numerical value setter (34).

The "screen control" data stored in the screen control memory device (27) is the required screen angle of 0°.

Address spaces are allocated at intervals of 45°, 15°, and 75', and the first address of the address space is the offset value (X,) (X,,) (X,,) corresponding to each screen angle.
It is defined as (X,,).

Each offset value (X0XX,,XX,,XX,,)
is set to a required value setting device 051 for each screen angle.

When the screen angle to be recorded is selected, this setting value is passed to the line counter (atO) ~ (
31) Count value of 5) (D.XD,,XD,,)(D,,
) and the corresponding offset value (Xo
) to (X,,) are sent to the adder C3η.

The adder cJ)7) adds an offset value (3) to the outputs of the corresponding line counters (31o) to (31?) selected at the same time, and the added value D+X is stored in the screen control memory device. Screen control data 1 in
Specify the Natres number of the area where the word was recorded. ``With the start pulse (C1), at the start end of main scanning for image recording,
The screen control data sent to the register .mu.s) is held in this main scanning section, the register .lambda.

The valley bits of the screen control data output by the register) are the lowest bits in the transfer direction of the register, the upper 40 bits go to the multiplex circuit, and the upper 55 bits go to the address generation circuit. The upper 10 bits are sent to the address selection circuit (-). Note that the remaining 17 bits are unused.

The 40 bits input to the multiplex circuit example are divided into 4-bit, 1-word control codes in order from the lowest order, and the lower 10 control codes (M,) to (M,,) are, in order from the lowest order, as follows: Multiplexer (23,) to (23,
. ), and the binary code representing 1 to 10 of the control codes (Ml) to (M,.) is input to the comparators (22,) to (22,) of the corresponding numbers.
22,,) is selected.

When the control codes (M,) to (M,,) have values other than 1 to 10, none of the comparators (221) to (2216) are selected, and any value is selected by another input signal means. , so that the output light beam (L,) ~
(L, , ) can be controlled to either the open/close side +ml, normally open, or normally closed, regardless of the screen pattern.

At this time, two words each consisting of the upper 4 bits of the control code () to (M, .) are placed at the start and end of the scan, such as scale -+7) -v-z t'se''x* io, y-
It can be used as a 7-start code (KS) and a mark-end code (KE).

The 10 bits input to the address selection circuit are input to the selectors (ZS,) to (25111) in the order of the lower one.

Each of these 1 bits is a 1-word selection code (SE, ) to (SE, , ), and one of the outputs of the first and second address counters (Y, ) (Y, ). The address generation circuit @) that selects
11 bits make up 1 word, and the 5 words are:
Starting from the lowest, the address counter (Y, ) offset code (yIO), address counter (Y, , address counter (Y, ) initial preset code (
ysI), as well as the screen pan circulation coefficient code (
y, S).

The offset code 'y+0) (yso) indicates that the line data recorded in the screen <turn memory device (211) is stored in different address spaces according to the screen angle, along with the valley memory blocks (211) to (21+o). Since it is recorded, each initial address of the address space corresponding to each screen angle is used as an offset value.

This offset code (yIO) (ys O) is used by the counter (a) that counts the clock pulses (c, ) at each address counter (Y, ) (Y,
syt) (asyt), adder (39y+)
(asyt) is added.

The initial preset code (y+IXyt') is used to shift the address of mesh data on non-adjacent main scanning lines between the mesh data stored in memory blocks (211) to (21, .) to be described later. Therefore, the value corresponds to the shift amount of the address in order to make the data of adjacent meshes.

This initial preset code (yIIXy, I) is caused by the control pulse (t) generated subsequent to the control pulse (t, ) shown in FIG.
Y weight).

The circulation coefficient code (yS) of the screen data is set to a value corresponding to the number of pixels included in one period based on the periodicity determined in advance by the halftone structure, and this value is set at each screen angle. 0', 45°.

It is given every 15° and 75°.

This circulation coefficient code (yS) has both counters (38yt
)(38Y2) through comparators (4o yt )(40Yt), respectively.

The output of the comparator (40Y, ) (40■) clears the respective counters (38Y+) (38yt) f, and clears the first and second address counters (Y, ) (Y,
)'s addressing code (A,) (A,) is rotated.

Note that both counters (38Y+) (as Y2) are
It is also cleared by the start pulse (C2). For this division, the start of counting is commanded by the control pulse ('i',) in Fig. 2, and the address signal (Aυ
The first J cut 11μ of (A,) is the offset value (ylO) (
y, O) and the initial preset value (ytI) (yt
I') addition value (yro+ytI) arrangement vc (yvo
+ytI).

One of the address signals (Aυ(At)) obtained in this manner is selected by the address selection circuit (25), and each of the memory blocks (211) to (211) of the screen pattern memory group [(211) zl+o) k city control.

Next, the mesh data recorded in the valley memory blocks (21,) to (21,.) will be explained.

FIG. 6 shows the quantization state of blurred halftone dots at each screen angle of 0'', 45°, and 15°.

In the figure, square ABCD is a unit halftone dot area corresponding to one blurred halftone dot, and (1) is the effective length of one side of a pixel, rs.
(S, ,) (S, ,) are the number of pixels included in each unit halftone area, and (P,) (P, , XP, ,) are each screen pitch.

Each screen pitch (P,)(P,,)CP□) is proportional to the square root of the number of pixels (S, )(S,,)(ne). Therefore, at each screen angle shown, the number of pixels is '/::h-'f:hS,=169. S
,,=200. S, , = 130 different ulta, when the length of one side of the pixel is 4 f, and the same at each screen angle, each screen pitch (Po) α, ) (P
An example in which i,) is different is shown.

Note that the screen angle of 75° is symmetrical with 15° and can be easily understood from the screen angle of 15°, so the 70th theory will be omitted.

FIG. 7 shows a memory map in which the halftone dot data for the screen angle of 0° shown in FIG. 6(a) is recorded, showing halftone dot graphics.

The halftone data is divided into pixel rows arranged in the column direction (scanning direction) using the minimum unit of the repetition period of the halftone dot pattern, and the plurality of pixel rows are stored in each memory block of the screen pattern memory device (21). (21I) ~ (211J
is recorded in the address space assigned to the screen angle 0°.

For example, if the pixel containing the point (Al) is the first pixel in the address space,
Address '117' in sequence, corresponding to the first address of '117'
In the increasing direction of the number, starting from the above pixel, the pixels 131+Ql*, the first memory block (21
, ).

From the second memory block (21,) onwards, the 10th memory block (21,0) contains the 1st memory block (21,0).
The nine pixel columns arranged in the row direction (feeding direction) with respect to the pixel columns of 1,) are made to have a common address number with each pixel of the first memory block (211), and , 11 m in the row direction of each pixel column in the order of memory block numbers.
, @7 and record this first address? /
Each pixel having a common address J is defined as a first pixel group.

When there are 10 memory blocks, data in the 11th to 13th columns in the unit halftone area (A)-(1) is insufficient with only the first pixel group. Therefore, the unit halftone area (
Similar unit halftone dot areas (A) adjacent in the row direction of A) to p
10 in the row direction assuming ~0 and the 11th column is the first column
The columns are sequentially recorded from the first memory block to the tenth memory block, and the pixels forming the row with the pixel containing point (A) are recorded in correspondence with the first address of the second address.
Let the pixel group be

In this way, each memory block (21,) to (21+J
, two pixel columns each of the first and second pixel groups are recorded with different initial addresses for each pixel group. The initial addresses of the first and second pixel groups are determined by the address counter (
Offset code (Y, ) given to (Y, )
y Ioo ) (yt Oo ). Furthermore, each pixel 11f having consecutive address numbers, the number of pixels in one column, for example 13, corresponds to a cyclic coefficient code (yS,).

FIG. 8 shows, in the form of halftone dots, a memory map in which the halftone dot data for the screen angle of 45° shown in FIG. 6(b) is recorded.

1 of the unit halftone area at screen angles other than 0°
1-, each side of the square ABCD ↑, run: 5 Since it is not parallel to the force direction and the feed direction, imagine a square EFGH that has sides parallel to both directions and circumscribes the square ABCD, and this circumscribed square EFGH is quantized into several pixels, and the inscribed unit halftone area is quantized into a mosaic pattern.

The circumscribed square EFGH at a screen angle of 45° is
Contains halftone data for two blurred halftone dots, unit halftone area AB
CD is divided into four triangular areas by opposite edges AC and BD (
Q,)(Q,XQ,)(Q,) is a circumscribed square EFGH
The area corresponds to the triangular areas at the four corners of the area in such a manner that they are superimposed by being moved in parallel in the screen line direction.

(7), and the pixel rows arranged in the scanning direction are - circumscribed square E
11” G 2o of pixels included in the length of one side of H
As the first pixel group, 10 pixel columns are taken out in the row direction with a repetition period of 1 frame, and each column is assigned to the block number of the memory block (21,) to (21+o) in column code order. The first pixel group is recorded in the address space of each memory block (21I) to (211°) corresponding to each other and assigned to a screen angle of 45°, starting from the first address of the address space.

Similarly, a second pixel group in 10 columns arranged in the row direction from the 10 pixel columns is recorded by giving a second initial address.

The initial addresses of the first and second pixel groups are the offset code (yto*s) of the screen corner layer 45°, the width α,
), and the number of pixels in one column corresponds to the cyclic coefficient code.

In the case of the above screen angles of 0° and 45°, the initial preset code (y; l5) of the address counter (Y, ) (Y2) is (ytI.)
Also, (ylI4B), 0'*Ls) is always set to 1, which specifies the initial address.

Note that in the case of a screen angle of 45° as shown in FIG. 6(b), halftone dots can be obtained even with only the first pixel group.

For example, since the number of memory blocks (21,) to (21,.) is exactly 10 of the number of pixels included in one side of the circumscribed square (l to ()'1, 20), the first Pixel group 1 contains halftone dot data without any shortage, and from the first pixel group, initial preset data)" width 1
．． 4).

(yxIas), halftone data equivalent to that of the second pixel group can be obtained.

In this case, the initial preset code (ytLs) (
V2I41) is the number of pixels from the pixel containing the point (odor) to the pixel containing the point (l).

9 and 10 show memory maps in which halftone dot data at a screen angle of 15° shown in FIG. 6(c) are recorded, in the form of halftone dots. ) and the mesh structure with the minimum repetition period repeated in the row direction (feeding direction), and FIG. 10 is an enlarged view of the main part thereof.

The blurred halftone dots at a screen angle of 15° are shown in FIG.
By quantizing this circumscribed square EF G Hl into an integer number of pixels, the inscribed square ABC
D is quantized.

In this case, each point of the inscribed square ABCD<A)(B)(
C11row, the ratio m:=ll:3 for dividing the sides of the circumscribed square EFGH determines the screen angle θ.The quantized mesh structure having 10-1 is When m'+k'' pixels are arranged, a minimum unit repeating network structure is formed.

In this repeating mesh structure of the minimum unit, multiple pixel columns that are adjacent to each other are sequentially arranged for each pixel column at a screen angle of 15° in the valley memory blocks (211) to (21Io). Record in the allocated address space O At this screen angle of 15°, if all the mesh data of the repeating mesh structure of the minimum unit is recorded, the address space will increase, so one pixel that shares the initial address Only groups are recorded.

Therefore, the apparently insufficient data can be obtained as follows.

No. 1O1''A is an enlarged view of the main part of FIG. The 10 pixel columns at the beginning are recorded in each memory 7"0 (21+) to (2110) in correspondence with each other, each column having 130 pixels.

The initial address of this first memory block (21,),
For example, the pixel containing the point (A) is recorded at address 1, and the pixel containing the point (A) and the pixels that are continuous in the column direction are recorded at the last address, for example, address 130. The l1i11 sequence is continuous when the address signal is circulated.

From the second memory block ('zx,) to the first address of the tenth memory block (21+o), the pixels containing the point (8) and the pixels lined up in the row direction are sequentially recorded. 11 counting in the row direction from the pixel included in column point (A)'
Ill of the board cut in the row! ! 1 can be obtained from the pixel of the concave 1-line row (8) in the 10th row counting from the 1st row in the marching direction and the pixel row of the same 1st row.

All symmetrical pixels in the mesh structure have equal values, so
The pixel row containing the point Avi in the first column is equivalent to the pixel row containing the point (A) in the 10th column in the marching direction.

Therefore, if you want each pixel in the 11th column to the 20th column in the row of the first address address, enter the address number of the row of pixels including the point (8) in the 10th pixel column in the marching direction, and enter the initial preset code (y + LJ ( ytLg),
It depends on the address counter (Yυ(Y,).

In addition, offset at screen angle 15'': I-
t° (ytou) (ytou) is the screen angle 1
The first address of the address space assigned to 5° is the first address of the pixel group, and the initial preset code (y
tLs

In each memory block (21l) to (221o) in which mesh and mesh data are recorded as described above, the offset code given to the address counter (Yυ(Y,) is as follows.
The address space is changed, and the initial preset code specifies the first pixel to be read out in the 1L circle.

The offset code is used to change the address space 1 for each screen use, and is also used to separately designate the first pixel group and the second pixel group for the same screen angle V.

For example, when the screen angle is 0° and the output beam is 210, the first scanning section No. 11+1 is the first pixel group, and the second scanning section No. 2+o is the second pixel group. The arrangement order of pixels in the row direction is obtained in the normal phase of memory blocks (21,) to (211+1). At this time, the row direction arrangement of pixels and the output light beam (L
, ) to (L, .) correspond to each other in sequential numerical order.

However, in the third scanning section No. 3+o, the 10th
Unless both the pixel group and the second pixel group are specified, the desired pixel row cannot be obtained.

For example, columns 8 to 10 of the first pixel group and column 1 of the second pixel group
Assume that we want to obtain columns 1 to 13 and columns 1 to 4.

In this case, an offset code (y, o,) that specifies the initial address of the first pixel group, an f address counter (
An offset code (y*o) 1 address counter (Y,
), and the 8th to 10th memory blocks (z
ta) to (21111) contain address counters (Y,
) so that you get the output of that memory block (Zta)
Selector (25 Hatake) related to ~(21111) ~(25,
. ) to determine selection codes (S,) to (S,.), and
The first to seventh memory blocks (21,) to (21?) are configured to receive the output of the address counter (Y, ).
Selection codes (Sl)-(
Furthermore, in this case, the valley memory block (21,) ~
The pixel column obtained at (21+11) is the memory block (
Since the pixel rows are not arranged in numerical order from 21, ) to (21+J), this arrangement is changed to create the required light beam (Ll
) to (L,,). To do this, the control codes (Ml) to (M, .) given to each multiplex (231) to (23111) are used to match the corresponding pixel columns and light beams. Connect (L,) to (L,.).

Such control is similarly performed at other screen angles.

In the mesh structure shown in Fig. 6, each screen angle is actually recorded by the number n of light beams included in the feed width W when all 10 light beams are used to record each screen angle. The following table shows how the screen pitch of the mesh structure changes for each screen angle using the following equation.

P=-・W ・・Music 4 hits・Music songs・Listen・Music songs (1) As can be seen from the figure, by changing the light beam n, the screen pitch consistency is approximated, and this approximation You can also change the screen pitch in this state.

For example, if the screen angle is 0°, 9 lines, 45°, 1°, and ±15°, 8 lines, the screen pitches are P, = 1.44・W, 'P41 = 1.41・W
, P, , = 1.43·W.

P? ! = 1.43・W. Other screen pitches can also be determined from the table by the number of beams for each screen whose - is approximate to the screen pitch coefficient.

In this way, when the number (n) of light beams is changed, the number N of pixel columns read out from the screen pattern memory device (21) and the number n of pixel columns actually used
, the periodicity in the feeding direction changes depending on the number of light beams (n).

For example, to explain the case where the screen angle is 0° in FIG. 7, N=10. When n=10, the pixel columns repeated every 13 columns are divided into every 10 columns to form halftone dots, so this repetition period becomes 130, which is the least common multiple.

, 130 pixels and elements are read out 10 by 10 with 10 beams, so it returns to the initial state after 13 repetitions.

This means that after the 13th scanning section NIL1316, the same scanning section as the first scanning section (No. One screen opening side data to be controlled requires 13 words.

This number of repetitions is determined by the comparison setting value (m
, ).

When the number of light beams is n = 9, the least common multiple of 9 and 13, 117, is the number of repeated pixels, and -=13 is,
The number of times the feed is repeated is determined. -13.

For each screen angle, this number of repetitions is generally determined as the least common multiple m of the number R of pixel rows included in the repetition period on the network structure and the number n of pixel rows actually used. , - corresponds to the number of words of the screen control data.

If you change the number n of light beams used in this way, the contents of the screen control data will change, so this screen control data is stored in advance on a floppy disk ( 41) Prepare the data in another storage medium, and load the data into the screen control memory device via the CPU (+s) before use.

As described above, in the halftone image recording method of the present invention,
4. The area included in the scanning width W of the image recording means.
L,)~(L,.),. □1o5, thereby making it possible to finely select the screen pitch of the halftone image without changing the scanning width W.

In addition, since the screen pitch can be changed while keeping the scanning width W constant, the number of pixels of the quantized blur halftone dots to be stored in the solid-state memory device can be set at each screen angle of 0°, 45°, and 15°. , 75°, it is possible to use a value other than the one that approximates the same number, and therefore, it is possible to increase the selection ratio of the number of pixels when quantizing blurred halftone dots.

Furthermore, since it is possible to use quantized blur halftone dots with a different number of pixels for each screen angle, it is possible to change the reproduction gravel layer range of the color plate and the reproduction m degree range of the black plate, etc. It is also possible to reduce the memory capacity of the solid state memory devices used.

[Brief explanation of drawings]

Figure t, 1'' is for explaining the implementation safety of the present redundant method. Figure 1 is a block diagram of an electronic halftone image recording device. Figure 2 is a timing circuit in Figure 1. 3 is a block diagram of the address circuit of the screen control memory device in FIG. 1, FIG. 4 is a block diagram of the shift register circuit in FIG. 1, and FIG. 5 is a time chart of each control pulse obtained in FIG. , a block diagram of the address circuit that generates the address signal of the screen pattern memory device in FIG. 1, and FIG. 6 shows the structure of the quantized blurred dots stored in the screen memory device for each screen angle FIG. 7 is a graphical memory map for storing quantized 'poke halftone dots at a screen angle of 0° into the screen pattern memory device, and FIG. A graphical memory map of 45°. FIG. 9 is a graphical memory map of a screen angle of 15°. FIG. 10 is a graphical memory map showing an enlarged view of the main part of FIG. (2) Rotating cylinder (3) Surface (4) Photosensitive material (5) Exposure light beam, (8) Feed motor (9) Synunda axis rotary encoder (11) Laser beam 112) Beam splitter (13,) ~
(131゜) Shutter device (14,) ~ (1410) Optical fiber housing) Zoom lens C6) Servo motor unit) Screen pitch setting circuit Qs) CPU αo) P, L, L1 circuit (Foundation)) Timing circuit, (21) Screen pattern memory family - (211) ~ (2! to) memory block', (221 pattern extractor (22,
) ~ (2210) Comparator ■) Multiple 1plex circuit (231) ~ (23,,) Multiplexer (241
)~(24Io) Shutter driver (25) Address selection circuit (25,)~(2510) Selector -(
2fil address generation circuit 2) Screen control memory device I28) Shift register lf30) Address counter (310) (314,) (311,) (3
1),) line counter (32 counter (3)
3) Comparator (34) (1351 numerical value setter
06) Selector (37) Adder (as Y
l ) (38yt) counter ('3q Yl) (3
9YJ adder (40) Floppy desk (g,) 1
Rotating pulse (g,) Phase pulse (Ll) ~ (L,.) Light beam (L,') ~ (L,:) Output light beam (e
l) Image signal (5) Scan width (field effective beam width (g,) (g,) (g,) control signal (nl number of beams (C,) clock pulse (C2) start pulse (
tl) (tt) (ts) Control pulse (rli comparison setting value (X,) (X, ,) (X, 6) (XP,) Offset value (tvi + ) ~ (M+ o) Control i code (K
S) Mark beginning code (KE) Mark end code (SE,) ~ (SE,,) Selection code ry, o) (y, O) Offset code (yr I)
(y, I) Initial preset code (yS,) Circulation coefficient, code (S,) (S,,XS,,) Number of pixels (
P,)CP,) (P,,XP,,) Screen pitch (t) Length (Q, )(Q,)(Q,X
Q,) area (A) (B) (C) (I) (eye CF) (G)
(Iffi point □Patent applicant's agent Patent attorney Takezawa
Zhuang −+, −),. 2. 911D 4th name mesh layer iii image 0 marking method 3.
Relationship with the case of the person making the amendment Patent issuer (amendment t) PilF) 1υ l11ilIW, page 5, line 6 ■ Correct ``1 Omiga'' to ``rl@ga''. (2) 1114, line 112, ``obtaining Qin related'' is corrected to ``obtaining Qin matter''. (3) 1ita page 4 @'1' line 7 "Integer value 11.
Next to J, add "Otori-, Jm, kssJ." ．． Correct line ``Number a'' to ``Number (phrase).'' (6) Same page 11191 [Correct IE 2nd line ``Dekabi-゛・4'' to ``Output light beam.'' (7) Same page 9 Correct “signal (・)” in line 1117 to “signal (・1)” (8) Correct “signal (・)” in line 10 of 9N to “signal (・su”) 0 ( 9) No. 111 [[Add "1" next to "ka-)," in the 14th line alli@1121, 1 line 1! --"Output beam (L,)~('11-・)Jt-Correct it as "output light beam (IJ,)~(J1.)". ae Same Il! 12th member, 17th line, correct "memory" as "memory lt@1)" ( Ll Same page 15, line 1S, “Signal (・]” is corrected as “Signal (@1) J.” as PIIIG 141, 111, line ’, “Signal ()”
・)" should be corrected as "signal (・su)". α4ptl, page 15, lines 15-16, "8 bits 01 byte" should be corrected as "1 byte (8 bits)". α9 Same, 17th purchase II, line 4 O Add r (f) J to the 0th order of Tsumugi's "value". ae p13m11 members - Correct "16 pieces 7" on the 6th line to "16 pieces 07". aη Same page 19, line 18 "S circuit Go to (2), ``Then, the upper 8 bits are output as a mark code,''
join.舖 11119 [Correction of "17 bits" to "15 bits" for the car. (2) No. 241 [1] Add "ru" to the end of O in the second line, "nioke" and "ru". 10 Same 521j Line 18 Correct "r(22,.)" to "r(2ts.)". - Same page 40, line 4, "screen angle" is corrected as "screen pitch" (to) same page 40, line 10, "sinunda" is corrected as "cylinder" O HIMI411 [line 9, "addition" Add the ``0th order r (4QY) (40Y*) comparator''. (c) Correct "-floppy desk" on line 9 of the ticket on page 41 of the same cylinder to read "r14970 tubi disk." @ Same No. 41 [Line 15 r(t・)JID Next, add r(t*)J. (2) Line 16 of the slip on page 41 of the same cylinder r (m) J r (Il,) (!Il*sXm-*Xmv*) J
Correction f! . @ Same line 411119116th "Comparison setting value" 0th order "(f) Count value" is added. @ (Jll142 Manazuru 4th line, '(]>IlJ is corrected as r (p・)''. (To) In Figure 1il1, the attached index is O. 1.Delete the code ``Mukai'' and correct the code ring to ``鵠''. In Figure s of ee pi3, add the code and C as shown in the attached red letter υ. (To) ``19m1tCoh'' (, Attachment MO1K. "Correct the leftmost center @totlt character "49" to the character a "51". that's all)

Claims (1)

[Claims] Synchronizing with the image signal, mesh data corresponding to a plurality of pixels of the blurred halftone dot is simultaneously extracted from a memory device in which the quantized blurred halftone dot is recorded, and the mesh data and the image signal are combined. A plurality of exposure light beams are selected according to the screen pitch to be controlled based on the signals obtained by superimposing them, and the selected exposure light beams are converted into a signal in which the mesh data and the image signal are superimposed. A method for recording a halftone image, characterized in that control is performed based on an arbitrary signal.