JPS62180674A - Facsimile signal decoding device - Google Patents

Abstract

PURPOSE:To improve processing capability by sending a test signal being made inactive by a decoding circuit only when the decoding of one encoding signal is completed to a microprocessor, and performing the escape of the microprocessor from a waiting state when the test signal goes to be made inactive. CONSTITUTION:When a completion flag is not set, the test signal is made active, and a microprocessor 11 is in the waiting state by a wait signal programmed in advance, A decoding circuit 12 receives an encoding signal from an external interface, and decides the signal by every bit. Since the completion flag is not set while the signal is decoded, the test signal is made active, and the microprocessor 11 is in the waiting state. At the same time when the decoding of one encoding signal is completed, and the completion flag is set, the test signal is made inactive, and the microprocessor 11 reads a decoded data, and the decoding process of one encoding signal is completed, then an instruction to start the next process being issued.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a facsimile signal decoding device using a microprocessor.

[Tracking technology]

Modified codes (MH codes), modified read codes (MR codes), and the like have been recommended by CCITT as encoding methods for facsimile signals, and are commonly used. A device that decodes those encoded signals into facsimile IJ signals.

It is known to use microprocessors.

In this device, as shown in FIG. 2, a decoding circuit 12 determines the number of black or white pixels contained in one input encoded signal by determining each pixel of an externally input encoded signal. The value is determined and the value is transferred to the Iku convex processor 11.
At the same time, the decoding circuit 12 sets a decoding completion flag, and the microphone processor 11 looks in the completion flag and reads the number of pixels, thereby realizing decoding.

[Problem that the invention seeks to solve]

In the conventional decoding device described above, the microprocessor 11
always looks in the I10 port with the decoding circuit 12,
In order to perform processing after recognizing the end flag, decoding facsimile signals with different code lengths requires processing to roof-in the I10 port at each decoding time when the signal with the shortest code length is input. Ru. Therefore, when a signal with a long code length is input, it is necessary to roof-in the 17-sided port many times without recognizing the end flag.

This method has the disadvantage of performing unnecessary processing in terms of processing capacity.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a facsimile signal decoding apparatus that eliminates such drawbacks of the conventional apparatus and improves processing performance.

[Failure to solve the problem]

According to the present invention, in a facsimile signal decoding device that includes a decoding circuit that decodes a facsimile signal sent via an external interface and a microprocessor that controls the decoding circuit, A test signal line for sending a test signal is provided, and the decoding circuit makes the test signal inactive when decoding of one coded signal is completed, and makes the test signal active at other times.

There is obtained a facsimile signal decoding apparatus characterized in that the processor is in a wait state when the test signal is active and exits the wait state when the test signal is inactive.

〔Example〕

Next, one embodiment of the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the invention. 11 is an 8086 microprocessor, and 12 is a decoding circuit having two types of interfaces: the microprocessor and the outside. 21
2 is an address bus, 22 is a data bus, 23 is a control signal line, and 25 is an external interface signal line.

A test terminal of the 8086 microprocessor 11 is connected to a signal line 24 containing a test signal indicating a completion flag of the decoding circuit 12. When the end flag is not set, the test signal is active and the microprocessor 1
1 is in the eight state due to a wait instruction programmed in advance. The decoding circuit 12 receives an encoded signal from an external interface, and the decoding circuit 12 judges the signal bit by bit. Since the end flag is not set while the signal is being decoded, the test signal is inactive and the microprocessor 11 is in a wait state. When the decoding of one coded signal is completed and the end flag is set, the test signal becomes inactive.

The microprocessor 11 reads the decoded data, completes the decoding process for one encoded signal, and instructs the start of the primary process.

〔Effect of the invention〕

As explained above, in the present invention, a test signal line is provided to send a test signal from the decoding circuit to the microprocessor, and the decoding circuit makes the test signal inactive only when the decoding of one encoded signal is completed. The test signal is sent to the microprocessor, and the microprocessor exits the wait state when the test signal becomes inactive.

Even when a single encoded signal with a long code length is input to the decoding circuit, the microprocessor does not need to look into the decoding circuit at all, and as a result, a facsimile signal decoding device with high processing capacity can be realized.

4 Brief Description of the Drawings FIG. 1 is a block diagram of a facsimile signal decoding apparatus according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional facsimile signal decoding apparatus.

1 and 2, 11...8086 micrometers, 12...decoding circuit, 24...test signal line.

Figure 1 Figure 2

Claims (1)

[Claims] 1. In a facsimile signal decoding device that includes a decoding circuit that decodes facsimile signals sent via an external interface and a microprocessor that controls the decoding circuit, the decoding circuit sends a test signal to the microprocessor. The decoding circuit makes the test signal inactive when decoding of one coded signal is completed, and makes the test signal active at other times, and sends the test signal to the processor, and the processor: A facsimile signal decoding device characterized in that it enters a wait state when the test signal is active, and exits the wait state when the test signal is inactive.