JPH0365876A - High speed 2-dimension coding decoding system - Google Patents

Abstract

PURPOSE:To attain high speed decoding by using a high speed EOL detection circuit and plural decoding circuit to decode 2-dimension code of plural lines simultaneously. CONSTITUTION:A high speed EOL detection circuit 6 detecting an end of line code (EOL) at a high speed, plural decoding circuits 7-10 and a control circuit controlling decoding circuits 7-10 are provided to an image data processing unit decoding a coding data obtained through compression of image data by the modified read(MR) system. Then the control circuit 11 awaits the decoding circuits 7-10 till required reference data are obtained and they apply decoding when the data are available to apply decoding for plural lines at once or the control circuit 11 keeps the decoding circuits 7-10 waiting till change point position information of the required reference line is acquired and they decode the data when the information is available. Thus, the 2-dimension code of plural lines is decoded at the same time, then high speed decoding is attained.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a high-speed two-dimensional code decoding method for decoding encoded data obtained by compressing image data using a modified read (MR) method. be.

[Prior art]

Conventionally, when storing image data in a storage device in a device that processes image data, the compression/expansion method for facsimile encoding/decoding is specified in Recommendation T, 4 of the Consultative Committee on International Telegraph and Telephone (CCITT). The modified Huffman (MH) method and the modified read (MR) method are often used.

FIG. 9 is a block diagram showing an example of an image processing apparatus that uses the MR method, which has a higher compression ratio of the above two methods. In the same figure, the CPU Ol executes a program stored in the memory 102 and loads the external storage device 1.
The MR encoded code data previously stored in 04 is transferred to the code data storage memory 105 through the external storage device control unit 103.

Next, the CPUI O1 uses the decoding circuit 106 to one-dimensionally decode the code data of the first line in the code data storage memory 105, and stores it in the decoded data storage memory 107. Based on this decoded data, the encoded data of the second line is two-dimensionally decoded and stored in the decoded data storage memory 107. In this way, coded data is decoded by performing one-dimensional decoding or two-dimensional decoding from the third line onward as well.

[Problem to be solved by the invention]

However, in the decoding method having the above configuration, code data is taken out word by word from code data storage memory 105, decoded, and stored in decoded data storage memory 107, and after completing decoding for one line, Since the code data of the next line is retrieved from the code data storage memory 105 and decoded in a serial process, there is a limit to the reduction in processing time.

The present invention has been made in view of the above-mentioned points, and it is an object of the present invention to provide a high-speed two-dimensional code decoding method that eliminates the above-mentioned problems and can rapidly decode coded data using the MR method.

[Means to solve the problem]

In order to solve the above problems, the present invention provides high-speed EOL detection for quickly detecting one line delimiter (EOL) in an image data processing device that decodes encoded data obtained by compressing image data using an MR method. circuit and
It is equipped with a plurality of decoding circuits, the high-speed EOL detection circuit, and a control circuit that controls the decoding circuit, and detects the position of the EOL code on the coded data in advance by the high-speed EOL detection circuit, and detects the position of the EOL code on the coded data at the beginning of each line. Each decoding circuit is assigned to each line based on the position, and multiple lines of encoded data are simultaneously decoded. At this time, since a reference line is necessary for decoding the two-dimensional code, the decoded data of the reference line is taken in and two-dimensional decoding is performed. At this time, the decoding data of the necessary reference lines may not be collected, so the control circuit makes the decoding circuit wait until the necessary reference data is collected, and then decoding is performed, thereby decoding multiple lines at once. It is characterized by the fact that it performs

In addition, the position of the EOL code on code data is detected in advance by a high-speed EOL detection circuit, and each decoding circuit is assigned to each line based on the code data position at the beginning of each line. Decrypt. At this time, when decoding a two-dimensional code, a reference line is required, so when decoding the line that becomes the reference line, the position information of the point where the decoded data changes from white to black or from black to white is stored in the change point buffer. The decoded line is decoded based on the position information of the change point of the reference line stored in the buffer at this change point. At this time, the necessary position information of the change point of the reference line may not be available, so the control circuit makes the decoding circuit wait until the necessary change point position information of the reference line is collected, and then The feature is that line decoding is performed.

[Effect]

The control circuit can cause the decoding circuit to wait until the necessary reference data is available, and then perform decoding once the data is complete, thereby decoding multiple lines at once, or the control circuit can cause the decoding circuit to wait until the necessary reference data is available, and decode multiple lines at once. Since the process waits until the changing point position information is complete and performs decoding and equalization at the complete point, two-dimensional codes of multiple lines can be decoded at the same time, making high-speed decoding possible.

〔Example〕

FIG. 1 is a block diagram showing the configuration of an image processing apparatus using the MR method according to the present invention.

The CPU executes the program stored in the memory 2 and transfers the code data previously stored in the external storage device 4 to the code data storage memory 5 through the external storage device control section 3. Next, the decoding circuit control circuit 11 controls the high-speed EOL detection circuit 6 to detect the position of the EOL code in the code data, and transmits the position information to the decoding circuit 17 to the decoding circuit 10. This decoding circuit I7 ~ decoding circuit ■1
0 decodes the code data in the code data storage memory 5 based on the EOL position information. Here, the decoding circuit I7
performs one-dimensional decoding, and decoding circuits 8 to 10 perform two-dimensional decoding. However, in order to perform two-dimensional decoding, it is necessary to refer to the image data of the previous line. [8 cannot be decrypted.

To explain the case where code data is repeated in a combination of one line of one-dimensional code and three lines of two-dimensional code as shown in FIG. 2, decoding circuit I8 decodes decoding circuit I7 and stores the decoded data. Every time decoded data is stored in the memory 12, the decoded data is taken in and used as reference data for decoding. The decoding circuit 9 and the decoding circuit IVIO perform decoding in the same manner, thereby performing decoding in units of 4 lines. Also, if only the first line is one-dimensionally encoded and all the remaining lines are two-dimensionally encoded,
First, the decoding circuit I7 performs one-dimensional decoding, stores the decoded data in the decoded data storage memory 12, and the decoding circuit I8 takes in the decoded data and uses it as reference data to perform decoding. Decoding circuit 1119. The decoding circuit 10 also performs decoding in the same manner. However, for the decoding circuit I[8, only the second line is decoded using the decoded data of the decoding circuit I7 as reference data, and for the fifth and subsequent lines, decoding is performed using the decoded data of the decoding circuit 10 as reference data. . As described above, according to this embodiment, since decoding is performed in units of four lines, processing time can be shortened, unlike the conventional decoding that serially decodes one line at a time.

FIG. 3 is a block diagram showing the configuration of a high-speed EOL circuit. As shown in the figure, the high-speed EQL circuit 6 has a configuration including a ROM table A 14, a latch 16, a ROM table B 18, an address counter 20, and an address latch 23. .

The address counter 20 outputs a code data address 21 for accessing the code data storage memory 5. The code data 13 output from the code data storage memory 5 is input to the ROM table A14 and converted into the tables shown in FIGS.
It is input into the OM table B18. Here, latch 16
The output 17 of the ROM table B1B stores the previous conversion result, and only when this output 17 and the output 15 of the ROM table A14 are the data combination shown in FIG. 6, the output 19 of the ROM table B1B is output. be done. This output 19 causes the address 21 of the address counter 20 to be set to the address latch 2.
2 and is stored in the decoding circuits 17 to 17 as EOL addresses.
It is output to the decoding circuit 10.

FIG. 7 is a block diagram showing the configuration of an image processing apparatus using another MR method according to the present invention. The CPU 31 executes the program stored in the memory 32 and transfers the code data previously stored in the external storage device 34 to the code data storage memory 35 through the external storage device control section 33.

Next, the decoding circuit control circuit 45
is controlled to detect the position of the EOL code in the code data, and send the position information to decoding circuits I37 to IV4.
Tell 0. This decoding circuit ■37 to decoding circuit IV4
0 decodes the code data in the code data storage memory 35 based on the EOL position information. Here, the decoding circuit I37 performs one-dimensional decoding and decoding circuits I3B to
The decoding circuit I40 performs two-dimensional decoding. However, in order to perform two-dimensional decoding, it is necessary to refer to the image data of the previous line, so if the decoding circuit I37 does not perform decoding, the decoding circuit I38 cannot decode. . Therefore, a case where code data is repeated in a combination of one line of one-dimensional code and three lines of two-dimensional code as shown in FIG. 8 will be explained. The decoding circuit 37 reads code data from the code data storage memory 35, performs decoding, and stores the decoded data in the decoded data storage memory 46. At the same time, the address of the position where the decoded data changes from white to black or from black to white is read. Information and a code indicating whether the change is from white to black or from black to white are stored in the change point address information storage memory I41. At this time, the decoding circuit I [38 reads the change point address information of the previous line stored in the change point address information storage memory I41, and performs decoding using this information and the data to be decoded in the code data storage memory 35. At the same time, address information of the position where the decoded data changes from white to black or from black to white, and a code indicating whether the change is from white to black or from black to white, are stored in the change point address information storage memory I.
[Stored in 42. Decoding circuit I39 and decoding circuit I
By performing the same decoding for V40, 4
Decoding can be performed line by line. In addition, if only the first line is one-dimensionally encoded and all remaining lines are two-dimensionally encoded, first the decoding circuit I3
7 performs one-dimensional decoding and stores the decoded data in the decoded data storage memory 46 and the change point address information in the change point address information storage memory I41. Decoding circuit I39. The decoding circuit I40 also performs decoding in the same manner.
However, for the decoding circuit I[38, only the second line is changed point address information storage memory I4 of the decoding circuit 137.
1, when decoding from the 5th line onwards, the decoding circuit I
Decoding is performed with reference to the change point address information storage memory 1V44 of V40. As mentioned above, according to this embodiment, 4
Since decoding is performed line by line, processing time can be shortened, unlike the conventional decoding method in which serial decoding is performed line by line.

〔Effect of the invention〕

As explained above, according to the present invention, a high-speed EOL detection circuit and a plurality of decoding circuits simultaneously perform two
Since dimensional codes can be decoded, an excellent effect can be obtained in that high-speed decoding can be used.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an image processing device using the MR method according to the present invention, FIG. 2 is a schematic configuration diagram for explaining the operation of the image processing device shown in FIG. 1, and FIG. 3 is a high-speed A block diagram showing the configuration of the EOL detection circuit, FIGS. 4 and 5 are diagrams showing input/output data of ROM table A, FIG. 6 is a diagram showing input data of ROM table B, and FIG. 7 is a diagram showing input data of ROM table B. FIG. 8 is a block diagram showing the configuration of an image processing apparatus using another MR method, and FIG. 8 is a schematic configuration diagram for explaining the operation of the image processing apparatus of FIG. 3.
The figure is a block diagram showing an example of an image processing device using the conventional MRi method. In the figure, l...CPU, 2...Memory, 3...
- External storage device control unit, 4... external storage device, 5.
... code data storage memory, 6... high-speed EOL detection circuit, 7... decoding circuit I, 8... decoding circuit ■, 9... decoding circuit ■, 10... ...Decoding circuit ■, 11...Decoding circuit control circuit, 12...
Decoded data storage memory, 31...CPU, 32...
...Memory, 33...External storage device control unit, 34.
... external storage device, 35 ... code data storage memory, 36 ... high-speed EOL detection circuit, 37 ... decoding circuit ■, 38 ... decoding circuit ■, 39 ...・・・
Decoding circuit ■, 40...Decoding circuit ■, 41...
・Change point address information storage memory! , 42... Change point address information storage memory 11 43... Change point address information storage memory ■, 44... Change point address information storage memory ■, 45... Decoding circuit control circuit, 46...Decoded data storage memory.

Claims (2)

[Claims] (1) In the decoding method using the modified read (MR) method, the line delimiter code (EO
A high-speed EOL detection circuit that detects L) at high speed, one or more one-dimensional decoding circuits, and a plurality of two-dimensional decoding circuits,
The position is detected by the L detection circuit, and each decoding circuit is assigned to each line based on the code data position at the beginning of each line, and the code data of multiple lines are simultaneously decoded. Regarding decoding, the decoded data of the reference line is taken in, two-dimensional decoding is performed, the decoding circuit is made to wait until the necessary reference data is collected, and multiple lines are decoded at once. A high-speed two-dimensional code decoding method. (2) In the decoding method using the modified read (MR) method, the line delimiter code (EO
A high-speed EOL detection circuit that detects L) at high speed, one or more one-dimensional decoding circuits, and a plurality of two-dimensional decoding circuits, the position of the EOL code on code data is determined in advance by the high-speed EOL detection circuit. is detected, each decoding circuit is assigned to each line based on the code data position at the beginning of each line, multiple lines of code data are simultaneously decoded, and when decoding a two-dimensional code, a line that is a reference line is selected. When decoding, the position information of the point where the decoded data changes from white to black or from black to white is stored in a change point buffer, and the position information of the change point of the reference line stored in this change point buffer is stored. Based on the decoding line,
A high-speed two-dimensional code decoding method characterized in that a decoding circuit is made to wait until necessary reference line change point position information is collected, and decoding is performed when the information is collected.