JPS62180598A - Programmable read only memory device - Google Patents

Abstract

PURPOSE:To use the prescribed terminal of an address terminal as a control terminal and a power source terminal by adopting a page address system at the time of writing the data. CONSTITUTION:At the time of a reading mode, the address designation of a memory element is executed by address input terminals A0-A4 and the data are read to data terminals D0-D3. At the time of writing, the address input terminal A2 functions as a high voltage supplying terminal, A3 and A4 function as the terminal where a control signal, a writing enable signal WE and an output enable signal OE are impressed at the time of the writing. Since the address terminal is the terminal of various functions, for the lacking address, a page address system is used at the time of the wiring, data terminals D0-D2 are used together with the page input terminal and the writing is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a programmable read-only memory device, and in particular to a method for reducing the number of bins by using address terminals for multiple purposes, such as control terminals. The present invention relates to a programmable read-only memory device.

[Conventional technology]

Generally, programmable read-only memory devices are used in write mode and read mode, where the loading mode allows selected storage elements to retain carriers generated under high electric fields, while the read mode allows carriers to be retained in the selected storage elements. The stored binary information is determined based on the difference between the threshold value of the storage element holding the carrier and the threshold value of the storage element holding no carrier. Therefore, in a programmable read-only memory device, in addition to an address terminal to which an address signal is applied and a data terminal to which a data signal is applied, each pole control signal, such as write enable, chip enable, output enable, etc. A control terminal for application, a power supply terminal for a high voltage for data writing, a power supply voltage for operation, and a ground voltage are required.

In conventional programmable read-only memory devices, address terminals, data terminals, and power supply terminals are commonly used in write mode and read mode, and various control terminals are provided for each control signal, and the same control terminals are used in common for write mode and read mode. Some devices allow separate control signals to be applied to the terminals for write mode and read mode.

[The problem to be solved by the invention]

However, in general, in write mode, three control signals are required: a write enable signal, an output enable signal, and a chip enable signal, but in read mode, only the chip enable signal is required, and they are not required in write mode and read mode. The numbers of both signals are different. Therefore, in conventional programmable read-only memory devices, even if a control terminal is provided for each control signal, and even if a control terminal is used for inputting different control signals in write mode and read mode, at least write There is a problem in that the same number of control terminals as the control signals required in the mode is required, and as the address space expands due to improvement in the degree of integration, the number of required pins increases.

[Means for solving problems]

In the write mode, a predetermined terminal among a plurality of address terminals functions as a power supply terminal, other predetermined address terminals function as a control terminal, and a predetermined terminal among the & number of data terminals function as a page input terminal, and control The number of control terminals can be reduced by using the page address method to write data into the storage element and by inputting the necessary control signals in the write mode from the address terminals.
The gist of this is to make it possible to prepare for the expansion of the address space.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

The figure is a pin layout diagram of a chip 20 for explaining a programmable read-only memory device according to an embodiment of the present invention.

This embodiment is a programmable read-only memory device having a storage capacity of 32 words x 4 bits, and in read mode, addresses of storage elements are specified using address input terminals AQ-A4, and data is read to data terminals Do-D3. In read mode, power supply terminal VccAND
It also requires a chip enable terminal (CB) as a control terminal. During normal writing, two high voltage supply terminals and one control terminal are required, and with the conventional method, writing is not possible without increasing the number of terminals, but with the present invention, writing is possible. becomes possible.

That is, in the figure, address input terminal A2 is used as a high voltage supply terminal, A3 and A4 are used as control signals for writing,
It functions as a terminal to which write enable signal WE and output enable signal OE are applied. The address terminal is used as a terminal for the function of Aki.) For the missing address, the page address method is used when writing, and the data terminal D
O~D2t- Also serves as base input terminal, 8 pages x 4
Writing is performed in the format of word x 4 bits. As a result, writing can be performed without increasing the number of terminals.

In the write mode, when a high voltage is supplied to the address terminal A2, the control circuit within the chip 20 functions in the write mode and writes data in a page address manner.

〔effect〕

As explained above, according to the present invention, since the page address method is adopted when writing data, a predetermined address terminal can be used as a control terminal and a power supply terminal, and the number of control terminals is reduced. Alternatively, the address space can be increased without increasing the total number of terminals.

[Brief explanation of drawings]

The figure is a pin layout diagram showing one embodiment of the present invention. AO~A4・・・Address terminal, Do-D3・
...Data terminal, vl)p, Vcc, G
N L) -- Power supply terminal, WE, OE. CE...Control terminal.

Claims (1)

[Claims] a storage space made up of a plurality of storage elements; an addressing means having a plurality of address terminals and for addressing any storage element in the storage space based on an address signal applied to the address terminal; and a data signal. A plurality of data terminals to which a plurality of voltages are applied, a plurality of power supply terminals to which a plurality of voltages are respectively supplied, and a control terminal to which a plurality of control signals necessary for write mode and read mode are applied, and the control terminal is based on the control signals. In a programmable read-only memory device having a control means for writing data represented by a data signal into a storage element designated by an address signal or reading data, in a write mode, a predetermined terminal of a plurality of address terminals is connected to a power supply terminal. Another predetermined address terminal functions as a control terminal, a certain terminal of the plurality of data terminals functions as a page input terminal, and the control means is configured to write data into the storage element using a page address method. A programmable read-only memory device.