JPS62180592A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To decrease the power consumption of a semiconductor by constituting so that an input circuit to which the signal unnecessary at the time of the refreshing mode is inputted can be the fixed logic level of a non-operation by an internal signal at the time of the refreshing mode. CONSTITUTION:For an address signal input circuit, an inverter 5 and a NAND gate 6 are provided at the gate input of an N channel MOS FETQN2 and a P channel MOS FETQP2. At the time of the refreshing mode (the inverse of REF=L), the circuit can be fixed to the inverse of Ai=L, and the address signal input circuit and the circuit part following the address signal input circuit are not operated. Thus, the semiconductor memory device to be able to decrease the power consumption can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device equipped with a refresh function capable of reducing power consumption.

[Advanced Technology] Some dynamic RAMs have a freshness: L function such as CAS before, 几X1 refresh, and self-refresh. Note that CAS represents a column address strobe, and R and As represent a row address strobe. The operation of the conventional dynamic RAM will be explained below.

FIG. 2 is a diagram showing an overview of the functions of a conventional dynamic RAM. In this figure, 1 is a memory cell array, 2 is a memory cell array, and 2 is a memory cell array.
is a row decoder, 3 is an address buffer, 4 is an address counter to which RAS decoding and CAS signals are added, 几gF,R
EF is refresh, non-fresh signal, AOI
At... is an address signal (hereinafter, A+ will be used in general use). Q again. ,Ql,...
. . . indicates the output signal of the address counter 4.

Furthermore, FIGS. 3(a) and 3(b) show the signal waveforms of the main parts in the normal mode, CAS before, and RAS refresh mode (hereinafter simply referred to as refresh mode) of the dynamic I'LAM shown in FIG. It is something.

Next, the operation of the circuit shown in FIG. 2 will be explained with reference to FIG.

In normal mode, the REF signal is 'L' as shown in Figure 3 (al), so the FET to which it is applied is turned off.On the other hand, the LgF signal is the same ('L', as in Figure 3), so the FBT to which it is applied is Therefore, the address signal A.+ AI Data is written and read using the

Next, in the refresh mode, the waveform of the main part is as shown in FIG. 3(b), at the time when the Ic and RAS signals fall, the EF signal falls and the REF signal rises.

Therefore, the output of the address counter 4 becomes a row address, refresh is performed for each row, and when this cycle goes through, it is determined that the refresh operation has been performed on every memory cell.

In normal mode and refresh mode, whether to input the row address to the external address input or the output of the 7-address counter 4 depends, for example, on the internal signal ratio E.
It is determined by an address signal input circuit as shown in FIG. 4 which receives inputs F and EF.

In Fig. 4, QNI to QN4 are N-channel MO8F
IT%Qpl, Q□ is a P-channel MO8FET.

EXI and AH indicate external address input.

However, the address signal input circuit shown in FIG. 4 uses external address input Ext even in the refresh mode.

It operates according to A1.

[Problem that the invention seeks to solve]

In the conventional semiconductor memory device as described above, in the refresh mode, the address signal input circuit (that is, each MO8F
ETQ□ * Qpt + Qvts * Qwt part) and the circuit parts that operate following this address signal input circuit operate unnecessarily, so there is a problem that it is not possible to reduce the power consumption of the semiconductor memory device. Ta.

The present invention was made to solve such problems, and an object of the present invention is to obtain a semiconductor memory device that can reduce power consumption.

[Means for solving problems]

The semiconductor memory device according to the present invention has a 51C configuration in which an input circuit to which signals that are unnecessary in the refresh mode are input is set to a fixed logic level of inactivation by an internal signal in the refresh mode.

[Effect]

In this invention, in the 7 retrieval mode.

The input circuit to which unnecessary signals are input and the circuit portion following this input circuit do not operate.

〔Example〕

FIG. 1 is a diagram showing an embodiment of a 7-dress signal input circuit of a semiconductor memory device of the present invention. This figure 1111-
The same symbols as in FIG. 4 indicate the same parts, 5 is an inverter,
6 is Nantes Gate.

The address signal input circuit shown in FIG. 1 is composed of the address signal input circuit shown in FIG. 4 and an N-channel MOS F E
This is because the gate input signals of TQ+n and P channel MO8FETQp* are different. That is, even in the refresh mode (⇠BF="L"), the cycle can be fixed at @L", and this address signal input circuit and the circuit portion following this address signal input circuit do not operate.

In the above embodiment, the address signal input circuit has been described, but the same applies to circuits to which other unnecessary signals 1 such as data input, read/write control input signals, etc. are input.

〔Effect of the invention〕

As explained above, the present invention is configured such that the input circuit to which unnecessary signals are input in the refresh mode is set to a fixed logic level that is inactive by an internal signal in the refresh mode, so that unnecessary signals are input to the input circuit. This has the effect that the input circuit and the circuit portion following the input circuit do not operate, thereby reducing the power consumption of the semiconductor memory device.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an address signal input circuit of a semiconductor memory device according to the present invention, and FIG. 2 is a schematic diagram showing the configuration of a conventional dynamicle AM. Figure 3 (a) and (b) are conventional dynamic RA
FIG. 4 is a diagram illustrating a conventional 7-dress signal input circuit. In the figure, 1 is a 7-ray memory cell, 2 is a row decoder, 3 is an address buffer, 4 is a 7-address counter, 5 is an inverter, 6 is a Nant gate, QNI to Q) 14 is N
Channel MO8PET%QPI e Qp2 is P-channel MO8PET. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 (JIPI, (Apt P sensor MO5FET No. 2)
Figure 3 (a) (Normal mode)

Claims (1)

[Claims] A dynamic RAM having a refresh function using an external control signal, characterized in that an input circuit to which unnecessary signals are input in the refresh mode is configured to have a fixed logic level inactive by an internal signal in the refresh mode. A semiconductor storage device.