JPS62179774A - Manufacture of image sensor - Google Patents
Manufacture of image sensorInfo
- Publication number
- JPS62179774A JPS62179774A JP61022342A JP2234286A JPS62179774A JP S62179774 A JPS62179774 A JP S62179774A JP 61022342 A JP61022342 A JP 61022342A JP 2234286 A JP2234286 A JP 2234286A JP S62179774 A JPS62179774 A JP S62179774A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- electrodes
- type
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 5
- 239000000758 substrate Substances 0.000 abstract description 24
- 239000011521 glass Substances 0.000 abstract description 4
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 3
- 238000001312 dry etching Methods 0.000 abstract description 3
- 230000001681 protective effect Effects 0.000 abstract description 2
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 abstract 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
Abstract
Description
【発明の詳細な説明】
〔概要〕
電極を片面に形成した受光素子を、裏面セル構造(基板
裏面より受光する構造)に形成する方法を提起し、イメ
ージセンサの製造プロセスの簡略化をはかる。[Detailed Description of the Invention] [Summary] A method of forming a light-receiving element with electrodes formed on one side in a back-side cell structure (a structure that receives light from the back side of a substrate) is proposed to simplify the manufacturing process of an image sensor.
本発明は裏面セル構造のプレーナ型イメージセンサの製
造方法に関する。The present invention relates to a method for manufacturing a planar image sensor having a back cell structure.
アモルファスシリコン(以下a−3iと略記する)は在
来の単結晶シリコンに比べて低価格で量産性にとむため
、近年、各種デバイスに実用化されるようになってきた
。Amorphous silicon (hereinafter abbreviated as a-3i) has been put into practical use in various devices in recent years because it is cheaper and easier to mass produce than conventional single crystal silicon.
とくに、a−5tを用いた受光素子は、太陽電池や、フ
ァクシミリ用イメージセンサ等に利用されている。In particular, light receiving elements using a-5t are used in solar cells, facsimile image sensors, and the like.
イメージセンサはシステムの大規模、高性能化にともな
い、それを構成するセルアレイの特性向上と高倍転化が
要望されている。As image sensor systems become larger and more sophisticated, there is a demand for improved characteristics and higher conversion rates of the cell arrays that make up the systems.
第2図(1)〜(4)は従来例によるイメージセンサの
製造工程を説明する断面図である。FIGS. 2(1) to 2(4) are cross-sectional views illustrating the manufacturing process of a conventional image sensor.
第2図(1)において、21は基板でガラス基板、また
はセラミック基板を用い、
この上に通常の気相成長(CVD)法により成膜した後
、通常のりソグラフィを用いてパターニングし、素子形
成領域上に窒化珪素(SiJ<)層22を形成する。In Fig. 2 (1), 21 is a substrate, which is a glass substrate or a ceramic substrate, and a film is formed thereon by the usual vapor phase epitaxy (CVD) method, and then patterned using ordinary lithography to form the element. A silicon nitride (SiJ<) layer 22 is formed over the region.
第2図(2)において、プラズマCVD法によりi型(
真性) a−3i層23、p型a−3i層24を連続し
て成長する。In Figure 2 (2), an i-type (
Intrinsic) The a-3i layer 23 and the p-type a-3i layer 24 are successively grown.
つぎに、反応ガスとしてCF、、+O□によるドライエ
ツチングを用いたパターニングにより、素子形成領域以
外(素子分離領域)のp型a−3i層24、i型a−8
i層23を除去する。Next, by patterning using dry etching using CF, +O□ as a reactive gas, the p-type a-3i layer 24 and the i-type a-8
The i-layer 23 is removed.
第2図(3)において、p型a−3i層24をパターニ
ングして分離し、p型a−3i層24Aとp型a−3i
層24Bを形成する。In FIG. 2(3), the p-type a-3i layer 24 is patterned and separated into a p-type a-3i layer 24A and a p-type a-3i layer 24A.
Form layer 24B.
第2図(4)において、p型a−5i層24Aとp型a
−5i層24B」二に、それぞれ5n02層よりなる電
極(透明電極) 25A 、25Bを形成する。In FIG. 2 (4), the p-type a-5i layer 24A and the p-type a
-5i layer 24B'', electrodes (transparent electrodes) 25A and 25B each consisting of a 5n02 layer are formed.
以上のように形成された受光素子は、1対の電極を基板
表面に有し、かつ基板表面より受光する型のものである
が、この場合は素子表面が露出しているため素子は性能
上、あるいは信頼性上不利である。The light-receiving element formed as described above has a pair of electrodes on the substrate surface and receives light from the substrate surface, but in this case, since the element surface is exposed, the element performance may be affected. , or it is disadvantageous in terms of reliability.
これに対して、本発明人は光電流と温度特性を向上させ
るため、素子のプレーナ化を検討した。In response, the present inventors have considered making the device planar in order to improve the photocurrent and temperature characteristics.
従来例の製造工程に準拠して、裏面セル構造にしてプレ
ーナ化を行った場合、p型a−3i層24の分離が出来
ないため、電極間で短絡してしまうことになり、素子形
成が不可能であった。If planarization is performed with a back cell structure according to the conventional manufacturing process, the p-type a-3i layer 24 cannot be separated, resulting in a short circuit between the electrodes, which prevents device formation. It was impossible.
上記問題点の解決は、基板(11上の素子形成領域に、
2個の凸部(1A、1B)を形成する工程と、該凸部(
1A、1B)上に電極(2A、2B)を形成する工程と
、該電極(2A、2B)を覆って基板(1)上全面に、
一導電型半導体層(3)と、真性半導体層(4)とを順
次成長する工程とを含む本発明によるプレーナ型イメー
ジセンサの製造方法により達成される。To solve the above problem, in the element formation region on the substrate (11),
A step of forming two convex portions (1A, 1B), and a step of forming the two convex portions (1A, 1B).
forming electrodes (2A, 2B) on the substrate (1A, 1B), and covering the electrodes (2A, 2B) on the entire surface of the substrate (1);
This is achieved by the method for manufacturing a planar image sensor according to the present invention, which includes the steps of sequentially growing a semiconductor layer (3) of one conductivity type and an intrinsic semiconductor layer (4).
本発明は基板上に形成された凸部の段差により電極、お
よびp型a−3i層を分離し、この上に基板全面にi型
a−5i層を成長することにより、裏面セル構造にした
プレーナ化素子が形成できるようにしたものである。In the present invention, an electrode and a p-type a-3i layer are separated by a step of a convex portion formed on a substrate, and an i-type a-5i layer is grown on the entire surface of the substrate, thereby creating a back cell structure. This allows for the formation of planarized elements.
第1図(11〜(4)は本発明によるイメージセンサの
製造工程を説明する断面図である。FIGS. 1 (11 to 4) are cross-sectional views illustrating the manufacturing process of an image sensor according to the present invention.
第1図illにおいて、1は基板でガラス基板を用い、
この上全面に厚さ1000人の5n02層を被着し、パ
ターニングして電極2^、2Bを形成する。In Figure 1 ill, 1 is a substrate, using a glass substrate,
A 5n02 layer with a thickness of 1000 layers is deposited on the entire surface and patterned to form electrodes 2^, 2B.
第1図(2)において、電極2A、2Bをマスクにして
、反応ガスとしてCF、、またはCCI□pz+ozに
よるドライエツチングにより、素子形成領域に高さ20
0Å以上の2個の凸部1A、1Bを形成する。In FIG. 1 (2), using the electrodes 2A and 2B as a mask, dry etching is performed using CF or CCI□pz+oz as a reactive gas to form a layer with a height of 20 mm in the element formation area.
Two protrusions 1A and 1B with a thickness of 0 Å or more are formed.
第1図(3)において、プラズマCVD法により一導電
型半導体層として厚さ200人のp型a−3i層3、真
性半導体層として厚さ1ooo〜5000人のi型a−
3i層4を連続して成長する。In FIG. 1 (3), a p-type a-3i layer 3 with a thickness of 200 nm as a one conductivity type semiconductor layer and an i-type a-
3i layer 4 is grown continuously.
第1図(4)において、基板全面に保護膜として、厚さ
50Å以上のSi3N4層5を被着する。In FIG. 1(4), a Si3N4 layer 5 with a thickness of 50 Å or more is deposited as a protective film over the entire surface of the substrate.
以上のようにして形成された受光素子は、1対の電極を
基板と素子間に埋め込み、かつ基板裏面より受光する型
のもので、この場合は素子表面が埋め込まれたプレーナ
型である。The light-receiving element formed as described above has a pair of electrodes embedded between the substrate and the element and is of a type that receives light from the back surface of the substrate, and in this case is a planar type in which the surface of the element is embedded.
また、従来例に比しリソグラフィ工程が少なくなり、製
造プロセスが簡略化できる。Furthermore, the number of lithography steps is reduced compared to the conventional example, and the manufacturing process can be simplified.
以上詳細に説明したように本発明の製造工程により、受
光素子を裏面セル構造にしてプレーナ化を行うことがで
き、イメージセンサの製造プロセスの簡略化が達成でき
る。As described above in detail, the manufacturing process of the present invention allows the light receiving element to have a back cell structure and is planarized, thereby simplifying the manufacturing process of the image sensor.
第1図(1)〜(4)は本発明によるイメージセンサの
製造工程を説明する断面図、
第2図(1)〜(4)は従来例よるイメージセンサの製
造工程を説明する断面図である。
図において、
1は基板でガラス基板、
2A、2Bは電極で5n02層、
3は一導電型半導体層でp型a−3A層、4は真性半導
体層でi型a−5A層、
5は保護膜でSi3N4層
本発明l述な面図
桔 1図
一\ −X
<AC’コFigures 1 (1) to (4) are cross-sectional views explaining the manufacturing process of an image sensor according to the present invention, and Figures 2 (1) to (4) are cross-sectional views explaining the manufacturing process of an image sensor according to a conventional example. be. In the figure, 1 is a substrate, which is a glass substrate, 2A and 2B are electrodes, which are 5N02 layers, 3 is a single conductivity type semiconductor layer, which is a p-type A-3A layer, 4 is an intrinsic semiconductor layer, which is an I-type A-5A layer, and 5 is a protection layer. 1 Figure 1 \ -X <AC'co
Claims (1)
B)を形成する工程と、 該凸部(1A、1B)上に電極(2A、2B)を形成す
る工程と、 該電極(2A、2B)を覆って基板(1)上全面に、一
導電型半導体層(3)と、真性半導体層(4)とを順次
成長する工程 とを含むことを特徴とするイメージセンサの製造方法。[Claims] Two convex portions (1A, 1
A step of forming electrodes (2A, 2B) on the convex portions (1A, 1B); A method for manufacturing an image sensor, comprising the steps of sequentially growing a type semiconductor layer (3) and an intrinsic semiconductor layer (4).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61022342A JPS62179774A (en) | 1986-02-04 | 1986-02-04 | Manufacture of image sensor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61022342A JPS62179774A (en) | 1986-02-04 | 1986-02-04 | Manufacture of image sensor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62179774A true JPS62179774A (en) | 1987-08-06 |
Family
ID=12080011
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61022342A Pending JPS62179774A (en) | 1986-02-04 | 1986-02-04 | Manufacture of image sensor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62179774A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107546106A (en) * | 2016-06-28 | 2018-01-05 | 朗姆研究公司 | SnO 2 thin film sept in semiconductor devices manufacture |
US11088019B2 (en) | 2017-02-13 | 2021-08-10 | Lam Research Corporation | Method to create air gaps |
US11322351B2 (en) | 2017-02-17 | 2022-05-03 | Lam Research Corporation | Tin oxide films in semiconductor device manufacturing |
US11355353B2 (en) | 2018-01-30 | 2022-06-07 | Lam Research Corporation | Tin oxide mandrels in patterning |
US11551938B2 (en) | 2019-06-27 | 2023-01-10 | Lam Research Corporation | Alternating etch and passivation process |
-
1986
- 1986-02-04 JP JP61022342A patent/JPS62179774A/en active Pending
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107546106A (en) * | 2016-06-28 | 2018-01-05 | 朗姆研究公司 | SnO 2 thin film sept in semiconductor devices manufacture |
US20180012759A1 (en) * | 2016-06-28 | 2018-01-11 | Lam Research Corporation | Tin oxide thin film spacers in semiconductor device manufacturing |
CN107546106B (en) * | 2016-06-28 | 2020-12-25 | 朗姆研究公司 | Tin oxide thin film spacer in semiconductor device fabrication |
US11031245B2 (en) * | 2016-06-28 | 2021-06-08 | Lan Research Corporation | Tin oxide thin film spacers in semiconductor device manufacturing |
US11183383B2 (en) | 2016-06-28 | 2021-11-23 | Lam Research Corporation | Tin oxide thin film spacers in semiconductor device manufacturing |
US11784047B2 (en) | 2016-06-28 | 2023-10-10 | Lam Research Corporation | Tin oxide thin film spacers in semiconductor device manufacturing |
US11088019B2 (en) | 2017-02-13 | 2021-08-10 | Lam Research Corporation | Method to create air gaps |
US11637037B2 (en) | 2017-02-13 | 2023-04-25 | Lam Research Corporation | Method to create air gaps |
US11322351B2 (en) | 2017-02-17 | 2022-05-03 | Lam Research Corporation | Tin oxide films in semiconductor device manufacturing |
US11355353B2 (en) | 2018-01-30 | 2022-06-07 | Lam Research Corporation | Tin oxide mandrels in patterning |
US11551938B2 (en) | 2019-06-27 | 2023-01-10 | Lam Research Corporation | Alternating etch and passivation process |
US11848212B2 (en) | 2019-06-27 | 2023-12-19 | Lam Research Corporation | Alternating etch and passivation process |
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