JPS62179750A - 樹脂封止型半導体装置 - Google Patents

樹脂封止型半導体装置

Info

Publication number
JPS62179750A
JPS62179750A JP61023110A JP2311086A JPS62179750A JP S62179750 A JPS62179750 A JP S62179750A JP 61023110 A JP61023110 A JP 61023110A JP 2311086 A JP2311086 A JP 2311086A JP S62179750 A JPS62179750 A JP S62179750A
Authority
JP
Japan
Prior art keywords
resin
lead frame
semiconductor element
lead
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61023110A
Other languages
English (en)
Inventor
Takayuki Uno
宇野　隆行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61023110A priority Critical patent/JPS62179750A/ja
Publication of JPS62179750A publication Critical patent/JPS62179750A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49586—Insulating layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置、特にリードフレームを用いて、外
部リード付けを行い樹脂で封止した樹脂封止型の半導体
装置に関する。
〔従来の技術〕
従来、樹脂封止型半導体装置は、セラミック封止型半導
体装置と比べて、安価で、大量生産に向いているという
理由から、主流の半導体装置となっておシ、特にモール
ド樹脂封止方式が多く用いられている。
従来の樹脂封止型半導体装置は、第２図の断面図に示す
ように、上面に金や銀などの内部メッキ４が施されたリ
ードフレームの半導体素子載置部２に半導体素子ｌをろ
う材などで接着し、同じく内部メッキ４の施されたリー
ドフレームのリード部３の内端のボンティング部と半導
体素子ｌの電極パッドとの間をボンディング・ワイヤ６
で電気的に接続した後、モールド樹脂７により封止して
いた。
〔発明が解決しようとする問題点〕
上述のような従来の半導体装置では、モールド樹脂の密
着性が乏しいことにより、半田浸し等の急激な熱ストレ
スを加えると、半導体素子とモールド樹脂との界面に剥
離を生じ、耐湿性が低下するという欠点があった。
〔問題点を解決するための手段〕
上記問題点に対し、種々検討の結果、半導体素子を搭載
したリードフレームの上面側と下面側との表面状態が異
なる場合、換言すれば、上面側と樹脂、下面側と樹脂と
の密着力の差が大きい場合、熱ストレスによる界面剥離
が生じやすいことを見出した。よって本発明では、リー
ドフレームの半導体素子載置部の裏面に、この載置部に
載置した半導体素子表面層と同じ材質の膜を形成してい
る。
〔実施例〕
以下本発明の実施例について、図面を参照して説明する
。
第１図は本発明の一実施例の断面図である。図において
、リードフレームの素子載置部２の裏面には、半導体素
子１の表面と同様なパッシベーション膜、例えば、窒化
シリコン膜５を、それからリードフレームのリード部３
の内端のボンディング部の裏面には、表側と同様な内部
メッキ層４を各々設けである。そのため、リードフレー
ムのリード部ボンディング部およびリードフレームの半
導体素子を含む素子載置部２の上面側と下面側の表面状
態が略同−となり、密着力のバランスがとれ、急激な熱
ストレスを加えても界面剥離が生じにくくなり、耐湿性
の劣化を防止することができる。
〔発明の効果〕
以上説明したように、本発明によれば、封止樹脂で包ま
ｎる内部物体の上下の密着カバランスをとることにより
、半田浸し咎の急激な熱ストレスに起因する耐湿性劣化
を防止でき、高信頼性を有する樹脂封止型半導体装置を
得ることができる。
【図面の簡単な説明】
第１図は本発明の一実施例の断面図、第２図り従来の樹
脂封止型半導体装置の断面図である。 ｌ・・・・・・半導体素子、２・・・・・・リードフレ
ームの半導体素子載置部、３・・・・・・リードフレー
ムリード部、４・・・・・・内部メッキ、５・・・・・
・パッシベーション膜、６・・・・・−ポンディングワ
イヤ、７・・・・−・封止樹脂。

Claims (1)

    【特許請求の範囲】
  1. リードフレームの半導体素子載置部に半導体素子を載置
    し樹脂封止した半導体装置において、前記半導体素子の
    表面層と同じ材質の膜が前記半導体素子載置部の裏面に
    形成されていることを特徴とする樹脂封止型半導体装置
    。
JP61023110A 1986-02-04 1986-02-04 樹脂封止型半導体装置 Pending JPS62179750A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61023110A JPS62179750A (ja) 1986-02-04 1986-02-04 樹脂封止型半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61023110A JPS62179750A (ja) 1986-02-04 1986-02-04 樹脂封止型半導体装置

Publications (1)

Publication Number Publication Date
JPS62179750A true JPS62179750A (ja) 1987-08-06

Family

ID=12101332

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61023110A Pending JPS62179750A (ja) 1986-02-04 1986-02-04 樹脂封止型半導体装置

Country Status (1)

Country Link
JP (1) JPS62179750A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5455453A (en) * 1991-07-01 1995-10-03 Sumitomo Electric Industries, Ltd. Plastic package type semiconductor device having a rolled metal substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5455453A (en) * 1991-07-01 1995-10-03 Sumitomo Electric Industries, Ltd. Plastic package type semiconductor device having a rolled metal substrate
US5643834A (en) * 1991-07-01 1997-07-01 Sumitomo Electric Industries, Ltd. Process for manufacturing a semiconductor substrate comprising laminated copper, silicon oxide and silicon nitride layers

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