JPS62176369A - Picture signal processor - Google Patents

Abstract

PURPOSE:To convert a scan line density into any magnification that an arithmetic circuit being hardware can accelerate with less distortion of converted data by converting input data into data at a desired scan line density after it is converted into data with high density scan lines. CONSTITUTION:The input data with scan line density l lines/mm is converted into interpolation data with 2<n>.l line/mm multiplied by 2<n>, and made into data with m lines/mm by thinning or iteration. With 4l>m given by four-fold interpolation, the quantized input picture signal of an input terminal 1 is converted into the data in a main scan direction multiplied by four in a main scan data interpolation circuit 2. The data in a subscan direction entering a subscan data interpolation circuit 3 is multiplied by four. A main scan data thinning circuit 4 thins the data in the main scan direction to m/4l, and a subscan data thinning circuit 5 thins the data in the subscan direction to m/4l, whereby the data turns out to be the output picture signal of an output terminal 6. Respective circuits 2-5 are controlled by respective timing signals from a timing signal generator circuit 7.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention converts an image signal with a low scanning line density into an image signal with a high scanning line density, for example, converts an image received by a photoelectric transmission device into a halftone image. The present invention relates to an image signal processing device that can be used in a device that records images stored in a storage device, television images, and the like.

Conventional technology The photographic electrotransmission equipment often used by newspaper companies has a low scanning line density of 4.7 lines/mm, while newspaper halftone images have a scanning line density of 454.54 lines, although it varies depending on the company.
54LPi (179 keys/mm), 602.0202
LPi (23.7 wells/W), 681.8181LP
i (26.8 valves/mm), 727.2727LPi
Halftone dot images are created at a high scanning line density such as (28.6 lines/mm), and the image signals received by photoelectronic transmission are recorded on photographic paper and then scanned again using an image input device. The density is scanned to create a halftone image. In images recorded on photographic paper, sub-scanning lines appear as density unevenness in the recorded image, which can cause moiré fringes during the rescanning process, and further increase noise during the rescanning process, which may affect the quality of the reproduced image. decreases. Furthermore, in many cases, image data file systems can only input images with low scanning line density due to file capacity. In order to solve the above problems, it is conceivable to directly convert an image signal with a low scanning line density into an image signal with a high scanning line density for recording.

The following two methods can be considered for scanning line density conversion. Method 1: Enlarge/reduce by repeating or thinning input data. Method 2: Enlarge/reduce by interpolating or averaging input data. To explain the expansion/reduction in Figure 9 N, ([3), the solid line circle data dlld13d15 d31 in the hole in the figure
If you use d33 a3s as input data and enlarge it twice in both the main and sub-scanning directions using method 1, it will smell like dll"d12"d21".

d+3=dt4=d23=d24. on the other hand,
Method 2 formula %) +d33)/2. ······become that way. Same figure β)
Similarly, when enlarging by 3 times, in method 1, all ”
d12 ” d13 ” d21:d22:d23=d
31-d32=d33. ...but method 2
For example, to calculate d22 by interpolation, d11+d1
4+d41. Each input data of d43 is added with weighting inversely proportional to the spatial distance from d22,
Calculations become complicated. In the case of reduction, in the same figure hole, (in I3, all the data is input data and the solid line circle is the reduced data, in method 1, the dotted line circle data is thinned out, and in method 2, in the same figure hole, do = (do
+d12 +d2t +d22 )/4, same figure (B)
Then mountain 1 = (d11 + d12 + d13 + d21 + d22
+d23+d31+d32+d33)/9.

Problems to be Solved by the Invention Method 1 allows arbitrary magnification conversion to be configured using a simple algorithm, and thus can speed up the hardware arithmetic circuit, but has the disadvantage that the converted data is highly distorted.

On the other hand, in method 2, the distortion of the converted data is small, and for magnification conversion of 210 times (n is a positive integer), 2 times or 1/
The calculation algorithm is simple, since it is sufficient to repeat 2 times, but it becomes complicated for other magnifications, and it is difficult to increase the speed of the calculation circuit compared to method 1.

The present invention solves the above problems, and provides an image signal processing device that can perform arbitrary magnification conversion of the scanning line density in which the distortion of the converted data is small and the speed of the hardware arithmetic circuit can be increased.

Means for Solving the Problems The present invention converts input data with a scanning line density of e lines/mm to m lines/1.
In order to convert to uL data, data is converted to interpolated data of 2nl data/mm by multiplying the antenatal input data by 2n, and further reduced to m data/mm by thinning or repeated data conversion.
By using data in mm, the above objective is achieved.

According to the above configuration, the present invention converts input data into high-density scanning line data with small distortion using a simple algorithm, and then converts it into desired scanning line density data using an even simpler algorithm. This allows simple scanning line density conversion with less distortion.

The reason for the small number of types mentioned above will be explained using one-dimensional signals for simplicity using FIGS. (5) - (The mouth is an example of 3 times enlargement. The analog image signal f of the hole in the figure is SO - S4
When quantized at the point, the quantized signal in the shaded area is obtained. The signal obtained by converting this quantized signal to a scanning line density three times higher by the method 1 described above has a distortion (error) that is smaller than the signal (dotted line) which is normally quantized at a scanning line density three times higher. The same figure (I3) shows the case where the scanning line density is converted to 3 times the scanning line density using method 2. Although the distortion is small, the arithmetic circuit is complicated because it is not a 2n times conversion.
In particular, the arithmetic circuit for two-dimensional signals) is as described above. Figures n to i in the same figure show embodiments of the present invention, and figure q shows a signal obtained by quadruple data interpolation using method 2. Figure p) shows a signal thinned out to 3/4 using method 1 with respect to the signal in figure 0, and figure ■ is a diagram in which the signal ◎ in the figure is rewritten to equal intervals. In C) of the same figure, 3
It can be seen from the comparison with the hole in the figure that the distortion of the converted signal according to the present invention (shaded area) is smaller than that of the signal quantized at twice the scanning line density (dotted line).

Example An embodiment of the present invention will be described below.

FIG. 1 is a block diagram of an image signal processing apparatus in an embodiment of the present invention.

In FIG. 1, 1 is an input terminal for a quantized input image signal, 2 is a main scanning data interpolation circuit, 3 is a sub-scanning data interpolation circuit, 4 is a main scanning data thinning circuit, 5 is a sub-scanning data thinning circuit, 6 7 is an output terminal for output image signals, and 7 is a timing signal generation circuit.

In this embodiment, the scanning line density obtained by interpolating the input image signal is larger than the scanning line density of the final output image signal, but if it is smaller, the circuits 4 and 5 are repeating circuits instead of thinning out. becomes.

Now, let us assume that the scanning line density of the input image signal is 1 line/mm, the scanning line density of the output image signal is m lines/M, and 41>m with 4 times interpolation.
The operation will be explained below in the case where the following occurs.

The input image signal at the input terminal 1 enters the main scanning data interpolation circuit 2, where the data in the main scanning direction is increased by four times, and then entered into the sub-scanning data interpolation circuit 3, where the data in the sub-scanning direction is further increased by four times. After that, the main scanning data thinning circuit 4 thins out the data in the main scanning direction to □, and the sub scanning data thinning circuit 5
Then, the data in the sub-scanning direction is thinned out to "a" and becomes an output image signal at the output terminal 6. Note that each of the circuits 2 to 5 is controlled by each timing signal from the timing signal generation circuit 7. More detailed examples of each of the circuits 2 to 5 described above will be shown below. The input/output lines of each processor (for example, there are multiple quantized data lines for input image signals) are shown as a single line for the sake of simplicity, as long as the signal flow can be understood.

2(8) and (81) are a detailed configuration diagram of the main scanning data interpolation circuit 2 of FIG. 1 and a timing diagram of the same circuit.

8 is a signal line for the input image signal sequence D1, 9.10 is a latch,
11 is an averaging circuit, 12 is a selector circuit, 13゜14
is a latch, 15 is an averaging circuit, 16 is a selector circuit,
17 is the signal line of the output image signal sequence D2, 18° 19, 20
are PI, P2., respectively. This is a signal line for the P4 timing signal. On the other hand, Fig. 2 (f31 (1) is P11 times, (
2) is P22 times, (3) is P44 times, (4) is latch 9
(5) represents the output signal of the latch 10, and (6) represents the output signal of the latch 13. Note that the circuit shown in FIG. 2 performs quadruple interpolation by configuring double interpolation in 2siI series, and the timing diagrams (1) to (6) in FIG. 2e are only for the first half.

The operation of the above configuration will be explained below.

First, input image signal string D1 (dl, d2゜d3...) of signal ls8 is set to latch 9, and the output of latch 9 is set to launch 10 in synchronization with the rise of timing signal P1 of signal line 18. The averaging circuit 11 outputs the averaging of the output of the latch 9 and the output of the latch 10.When the timing signal P1 of the signal line 18 is 1, the selector circuit 12 outputs the output signal of the I check 0 as Pl. When is O, the output signal of the averaging circuit 11 is outputted.The latch 13 outputs the output signal of the averaging circuit 11.The latch 13 outputs the output signal of the averaging circuit 11.
2 output signals are set, and their contents are shown in Figure 2 (B
) as shown in (6), dl・dl+d2, ct2
．． ct2, d3, R3, . . . appear in this order, resulting in a data string that has been interpolated twice. Similar action 13~
The signal string D2 on the signal line 17, which is the output of the selector circuit 16, is converted into the timing signal P on the signal line 20.
If data is captured at the rising edge of 4, a data string interpolated by 4 times will be obtained.

3A and 3B are detailed configuration diagrams and timing diagrams of the sub-scanning data interpolation circuit 3 shown in FIG. 1. Figure 3 (
In 5), 21 to 23 are line memories for image data. 24 is a selector circuit which outputs the data string D2 entering the 17 signal lines to one of the line memories 21-23. 25 is an address control circuit, which is composed of two counters and a counter output selector, and is connected to each line memory 21.
The address signal is output to .about.23. A selector circuit 26 outputs two signals, for example, A and B among the output signals A, B, and C of each line memory 21 to 23. 27 is a signal line for the selection signal S1, and the selection signal 81 is connected to the selector circuit 24.
26 and address control circuit 25. 28 is a signal line for a selection signal S2, which controls a selector circuit 37, which will be described later. 29 is a signal line of the timing signal P16, and the timing signal P16 and the timing signal P4 of the signal line 20 serve as input clock pulses for two counters in the address control circuit 25, respectively. Timing signals R4 and R are applied to signal lines 30 and 31, respectively, and timing signal R is applied to signal lines 16.
4 and RtL51, the contents of the counters of the input clocks P4 and P16 in the address system circuit 25 are cleared to O, respectively. The signals P4 and R4 are sent to the line memories 21 to 23.
For data writing, the signals P16 and at6 correspond to the pixel clock and scan synchronization signal for data reading, and the selection signals 81. Timing signal generation circuit 7 along with S2
Supplied from. Reference numerals 32 and 33 are output signal lines of the selector circuit 26, and the figure shows a state in which output signals A and B from the line memories 21 and 22 are selected and output. 34. Reference numerals 35 and 36 denote averaging circuits, which respectively calculate the averaging of the output signals A and B of the selector circuit 26, the averaging of the output signal A and the output signal of the averaging circuit 34, the output signal of the averaging circuit 34, and the averaging circuit. A signal obtained by adding and averaging B is output. 37 is a selector circuit which, in response to the selection signal S2 on the signal line 28, sequentially outputs the signal A on the output signal line 32 of the selector circuit 26 and the output signal of the averaging circuit 35;

The output signal of the averaging circuit 34 and the output signal of the averaging circuit 36 are output. 38 is an output signal line of the selector circuit 37, and D3 is its signal train. On the other hand, in Figure 3 (8)
1) to (4) are each timing signal P4. P16. R4°Rt6 is shown, and while writing the C data to the line memory 23, the data A and B of the line memory 21 to 22 are read out for 4 lines in the order shown in (4) of CD in Figure 3. This shows how the output signal of is outputted as a data string D3.

The operation of the above configuration will be explained below.

The line memories 21 to 23 are cyclically controlled so that one line is written and the other two lines are read. Expressing the relationship between line memory data ABC, assuming that the write state of line memories 21 to 23 is WS and the read state is R8, (ws=c, Rs=AB) → (WS=A, R8
=BC)→(WS=B, R8=CA) is repeated in this order. In the same figure (WS=C.

几5=AB)state is shown. The signal string D2 of the signal line 17 passes through the selector circuit 24 and is input to the line memory 23.
4 timing signal. During this time, the signals in the line memories 21 and 22 are repeatedly read out four times using the timing signal of PI3, and are output to the selector circuit 26. The input signals of the selector circuit 37 are A, (3A+
B)/4. (A+B)/2゜(A+3B)/4,
are output in that order to form a signal sequence D3. In the next cycle after D3, B, (3B+C)/4, (B10)/2, C13+3 C)/4, and in the next cycle, C, (3C+A)/4. (C+A)/2.
(C+3A)/4, and the cycle is repeated from the beginning.

FIG. 4(5) shows an example of thinning by the main scanning data thinning circuit 4 of FIG.

In Figure 4 (5), M is an arithmetic register, A and B are constant registers, and the reduction rate of the 1-thinning circuit is expressed as A/B (A≦B
).

The operation flow will be explained in order below.

39 is the starting point of image processing calculation for one line.

40 clears the register M to initialize it, and 41 inputs one pixel data. 42 subtracts the contents of register A from the contents of register M and determines whether the result is negative. If it is not negative, it goes to the determining section 44, which will be described later, and if it is negative, it goes to the calculating section 43, which will be described later.

43 outputs one pixel data input by the data input 41, and adds the contents of register B to the contents of register M.
44 determines whether the image processing operation for one line has been completed, and if it is not completed, it goes to the data input 41, and if it is completed, the input data string is 1.2 to the end point 45 for the image processing operation for one line.
．． When inputting 3.4.5.6..., the contents of the calculation register M as the calculation result of the flow 42 become -2,
It changes as -1, 0, -2, -1, 0... Since data is output only when the contents of register M are negative, the output data string is 1.2.4.5...
Therefore, one out of every three pieces of input data cannot be thinned out, and the data that has been reduced to five pieces is output.

FIG. 5 is a detailed configuration diagram and timing diagram of the main scanning data thinning circuit 4 shown in FIG. 1.

In the figure, reference numeral 46 denotes a register M, which selects an output signal from a selector 51 (described later) with an output pulse from an OR gate 55 (described later). 47 is register A.

48 is register B. 49 is a subtracter, register M
The contents of register A47 are subtracted from the contents of register A46. 50
is an adder that adds the contents of register M46 and the contents of register 848. 51 is a selector which selects the output of the subtracter 49 when the timing signal P16 on the signal line 29 is 1;
When I3 is 0, the output of adder 50 is sent to register M46.
give to A comparison circuit 52 outputs 1 when the contents of the register M45 are negative. , 53 is an O data register, which supplies 0 data to the comparator circuit 52. 54 is AN
At D gate.

The logical product of the output signal of the comparison circuit 52 and the timing signal PA of the signal line 57, which will be described later, is output. 55 is an OR gate that outputs the logical sum of the output signal of the gate 54 and a timing signal Ps of a signal line 56, which will be described later.

56 is a signal line for the timing signal Ps, and 57 is a signal line for the timing signal PA, into which the signals PS and PA are inputted from the timing signal generation circuit 7 shown in FIG. 58 is the PSM signal line which is the output signal of the AND gate 54; PSM
is the data string D3 sampling pulse of the signal line 38. On the other hand, (1) in FIG. 5 is the timing pulse P16.
In the same figure (2), the timing pulse Ps is synchronized with the PI3 with the phase shown in the figure, and in the same figure (3), the timing pulse PA is synchronized with the PI3 with the phase shown in the figure.

In the above configuration, the circuit operation will be explained below.

The register M46 is initially set to O by the timing signal R16 on the signal line 31. Thereafter, when the timing signal P16 on the signal line 29 is 1, the selector circuit 51 supplies the output of the subtracter 49 to the register M46.

At this time, when the timing signal Ps is input to the signal line 56, Ps becomes a write pulse for the register M46 via the OR gate 55, and the contents of the register M46 are changed to the register A4.
Only the contents of 7 will be subtracted. Then signal line 2
When the timing signal P16 of 9 becomes O, the selector circuit 51 gives the output of the adder 50 to the register M46. Further, if the contents of the register M46 are negative, the comparator circuit 52 outputs 1, and therefore the timing signal P is sent to the signal line 57.
When A is input, PA becomes a write pulse for register M46 through AND gate 54 and OR gate 55, and the contents of register M46 are added by the contents of register B48. The fact that the output of the comparator 52 is 1 means that the fourth
This is the same as the instruction to go from 42 to 43 in the flow of the drawing, and therefore the signal PS on the output signal line 58 of the AND gate 54
By sampling the signal string D3 of the signal line 38 at M, a thinned output signal string can be obtained.

FIG. 6 shows the operation flow of the sub-scanning data thinning circuit 5 of FIG. 1.

In the figure, S is an arithmetic register. C and D are constant registers, and the reduction rate of the 1-decimation circuit 5 is C/D (C≦D).
It is expressed as

The operation flow will be explained in order below.

59 is a starting point for image processing calculations. 60 clears the register S to 0 and makes initial settings, and 61 inputs one line of data. 62 subtracts the contents of register C from the contents of register S and determines whether the result is negative. If it is not negative, it goes to a determination unit 64, which will be described later.If it is negative, it goes to a calculation unit 63, which will be described later.

63 outputs one line of data inputted by the data input 61, and adds the contents of register D to the contents of register S.

64 determines whether all lines of image processing have been completed, and if not, it goes to the data manual 61, and if it is finished, it goes to 65.
Go to the end point of the image processing operation.

The difference in the operation is that the processing is performed for each pixel in FIG. 4, whereas the processing is performed for each line.

The second page of FIG. 7 shows a detailed configuration diagram and timing diagram of the sub-scanning data thinning circuit 5 shown in FIG.

In the seventh drawing, 66 is a register S, which converts the output signal of a selector 71 (described later) into an output pulse of an OR gate 75 (described later). to 67 is a register C168 is a register D. 69 is a subtracter that subtracts the contents of register C67 from the contents of register S66. An adder 70 adds the contents of the register 866 and the contents of the register D68. 71 is a selector which selects the output of the subtracter 69 when a timing signal Ss on a signal line 78, which will be described later, is 1;
When s is O, the output of adder 70 is given to register 866. A comparison circuit 72 outputs 1 when the contents of the register 866 are negative. 73 is a 0 data register, which supplies 0 data to the comparison circuit 72. 74 is an AND gate that outputs the logical product of the output signal of the comparator circuit 72 and a timing signal QA of a signal line 81, which will be described later. 75 is an OR gate that outputs the logical sum of the output signal of the gate 74 and a timing signal Qs of a signal line 80, which will be described later.

76 is a flip-flop, which is set by the output signal of the gate 74 and reset by the timing signal Qs of the signal a80, which will be described later.
It will be sorted. 77 is an AND gate which outputs the logical product of the Q output signal of the free-knob flop 76 and the sampling pulse PSM of the signal line 57. 78 is a timing signal S
s signal line, 79 is a timing signal Rs signal line, 80
1 is a signal line for the timing signal Qs, and 81 is a signal line for the timing signal QA, which receives the signals Ss, Rs, and Qs from the timing signal generation circuit 7 in FIG.

Small enters. 82 is an output signal line of the gate 74, and the signal on this line becomes a sub-scanning synchronization signal of the output image signal. 83
is the output signal line of the gate 77, and the signal on this line is the sampling pulse of the data string D3.

On the other hand, (1) in FIG. 7(C) shows the timing pulse 16.
, the same figure (2) is synchronized with the timing pulse Ss with the phase shown in the figure, and the same figure (3) is the timing pulse Q.
s synchronizes with Ss with the phase shown in the figure, and (4) in the same figure synchronizes with R16 and SS with the phase shown in the figure with a timing pulse.

In the above configuration, the circuit operation will be explained below.

Register 866 is initially set to 0 by the timing signal on signal line 79. Thereafter, when the timing signal Ss on the signal line 78 is 1, the selector circuit 71 gives the output of the subtracter 69 to the register 866, and when the timing signal Qs is input to the signal line 80 at this time, Qs is input to the OR gate 75.
becomes a write pulse for register 866 via register/
The contents of 1S66 are subtracted by the contents of register C67. After that, the timing signal S on the signal line 78
When S becomes 0, selector circuit 71 provides the output of adder 70 to register 866. Further, when the contents of the register 866 are negative, the comparator circuit 72 outputs 1, and therefore, when the timing signal QA is input to the signal line 81, the QA
becomes a write pulse for register 866 via AND gate 74 and OR gate 75, and the contents of register 866 are added to the contents of register D68.

The fact that the output of the comparator 72 is 1 is the same as the instruction to go from 62 to 63 in the flow of FIG. 6, and therefore, one line of data is output after the timing signal QA is output to the AND gate 74. Therefore, the output of gate 74 becomes a sub-scanning synchronization signal.

Since the flip-flop 76 is reset by the output signal of the gate 74 and reset by the signal QA of the signal line 80, the timing signal PSM of the signal line 57 is gated by the gate 77 using the Q terminal output signal of the flip-flop 76 for data sampling. When a pulse is created, it becomes this sampled pulse.

As mentioned above, the timing pulse PA in FIG. 5 becomes the timing pulse PSM thinned out in the main scanning direction in the figure, and PSM becomes the data sampling pulse thinned out in the sub-scanning direction in FIG. If the data string D3 of the signal line 58 in the figure is sampled using this sampling pulse, a desired data string in which both the main and sub data are thinned out can be obtained. In addition, from the above-mentioned 1/M to m/
Effects of the invention on B As described above, the present invention can realize arbitrary magnification conversion of image data with small distortion using a simple algorithm, and can speed up image processing operations because the hardware calculation circuit can be configured in a pipelined manner. It can be done, and the effects are great.

[Brief explanation of drawings]

FIG. 1 is a block wiring diagram of an image signal processing device according to an embodiment of the present invention, FIG. A), (f3 is connected to the same device, ■ is a connection diagram and timing diagram of the main scanning data thinning circuit in the same device, and Figure 6 is an operation flowchart of the sub-scanning data thinning circuit in the same device. , 7th drawing, (
B) is a diagram of side dishes in the same device. 2... Main scanning data interpolation circuit, 3... Sub-scanning data interpolation circuit, 4... Main scanning data thinning circuit, 5... Sub-scanning element-twilight thinning circuit. Name of agent: Patent attorney Toshio Nakao Haka1 prestigious family
Register H times Ko, ZaU @Pikuri - Jin 5 - Regisf 5 4I 6 Figure
Q: L2' space CD registration space p Fig. 8 Ss 51 51 bl % Fig. 9

Claims (1)

[Claims] When converting an input image signal with a low scanning line density of l lines/mm to an image signal with a high scanning line density of m lines/mm, the l lines/mm
a first converting means for converting the input image signal of 2^n times into an image signal of 2^nl lines/mm of interpolated data;
A second step for converting the image signal of ^n·l lines/mm into the image signal of m lines/mm by data conversion of reduction or enlargement.
An image signal processing device having a conversion means.