JPS63102468A - Converting device for resolution of picture data - Google Patents

Abstract

PURPOSE:To obtain an output picture quality which is higher than the resolution stored in a picture memory, by providing a one-dimensional and two-dimensional arithmetic circuits which successively calculate the density mean value of each picture element in the one-dimensional and two-dimensional directions in one block, respectively. CONSTITUTION:Data which are converted to have resolution of 1/4 and data before conversion are respectively represented by A and a, b,.... From the picture data of a density of eight bits per one picture element inputted from a scanner 1, the mean value in the one-dimensional direction in one block is calculated by an one-dimensional arithmetic circuit 2 in the following way: a'=(a+b+c+d)/4, f'=(f+g+h+i)/4, k'=(k+l+m+n)/4, and p'=(p+q+r+s)/4. A two-dimensional arithmetic circuit 3 two-dimensionally averages the mean value density in the one-dimensional direction calculated by the circuit 2. Namely, A=(a'+f'+k'+p')/4 is calculated and the mean density A in a prescribed block is written in a picture memory 4. Then the resolution is converted to four times more accurate at the memory 4.

Description

[Detailed description of the invention] “Industrial application field” The present invention relates to an image data resolution conversion device.

[Background Art] In recent years, with the development of computer technology, image processing by computers has been actively performed.

By the way, since one image data is a huge amount of data,
In image processing systems, data capacity and processing speed are major issues. On the other hand, due to the demand for inputting and outputting clearer images, there is a trend toward higher resolution in image input/output devices, and the amount of image data is increasing.

Conventionally, when connecting an image input/output device and an image processing system, a memory area is secured to store the amount of data for the resolution of the input/output device, or the method shown in FIG. 9 is adopted. .

The method shown in Figure 9 is applicable to input/output devices that input and output data larger than the image memory capacity (for example, when the input/output device has four times the resolution of the image memory).
As shown in Fig. 9 (1), the input data is thinned out and stored in the image memory, and the output data is high-resolution by overprinting the same data as shown in Fig. 9 (2). It is compatible with image output devices.

However, the above method has a problem in that it is not possible to obtain an output quality higher than the resolution stored on the image memory.

[Object 1 of the Invention] The present invention has been made by paying attention to the problems of the above-mentioned conventional devices, and provides image data that connects a high-resolution image data input device and an image memory that stores low-resolution image data. It is an object of the present invention to provide an image data resolution conversion device that performs human output of an image while maintaining a quality higher than the resolution of an image memory.

[Embodiment of the Invention] FIG. 1 is an explanatory diagram of converting the resolution to 174 in the present invention. In other words, this is an explanatory diagram in the case where an input/output device has a resolution four times that of the image memory, and the resolution of the output image data of the input/output device is reduced to 1/4 before being stored in the image memory.

In this case, the average density within a block of 4x4 pixels in the input image data is calculated, and this average density is stored in the image memory, thereby performing the 1/4 resolution conversion.

The data converted to 1/4 resolution (1 pixel data to be stored in the image memory) is defined as A, and the data before conversion is a, b, C1... (each in a 4 x 4 pixel block). pixel), then A-(a+b+C+d+f+g+h+i++1+m+
n+p+q+r+s)/16, and the average density thus determined is data A whose resolution has been converted to 1/4.

FIG. 2 is a diagram showing an example of a circuit for realizing the above resolution conversion.

This circuit includes an image scanner 1, a latch 5 that latches pixel data one by one, a one-dimensional calculation circuit 2 that averages pixel data in one dimension within a predetermined block, and -
A latch 8 that latches the output data of the dimension calculation circuit, and -
It has a two-dimensional arithmetic circuit 3 that averages the pixel data in two-dimensional directions based on the output data of the dimensional arithmetic circuit 2, and an image memory 4.

In other words, the -dimensional arithmetic circuit 2 uses the adder 6 and the latch 7 to sequentially calculate the average density value of each pixel in the one-dimensional direction within an l block composed of N×N pixels (N is an integer of 2 or more). , ', which is an example of a circuit for calculating, and the two-dimensional calculation circuit 3 sequentially calculates the density average value of each pixel in the two-dimensional direction within one block using the line buffer 11, adder 9, and latch 10. , is an example of a circuit that performs calculations.

In Figure 2, image data input from image scanner l (8-bit density data per pixel)
The -dimensional calculation circuit 2 calculates the average value in the one-dimensional direction within the block.

That is, a' = (a+b+c+d)/4f'=
(f+g+h+i)/4'= (k+l+m+n
)/4 p' = (p + q + r + S) /
4, the average value in the -dimensional direction is calculated.

The two-dimensional calculation circuit 3 is a circuit that two-dimensionally averages the one-dimensional average density calculated by the -dimensional calculation circuit 2.

That is, the calculation A=(a'+f'+'+p')/4 is performed, and the average density A within a predetermined block is written into the image memory 4.

Further, the -dimensional arithmetic circuit 2 has an adder 6 and a chi 2 chia, and the two-dimensional arithmetic circuit 3 has an adder 9, a latch 10, a line buffer 11, and an address counter 12.

The latch 5 receives the density data output from the image scanner 1 in a -dimensional manner (i.e., a, b, c, d, e,
. . . , f, g, h, . Furthermore, the latch 7 is cleared at each block break (that is, every four pixels).

Therefore, when Chi2Chi5 is outputting data a, since latch 7 is cleared, adder 6 outputs data a, and latch 7 latches the output data a of adder 6. Subsequently, when the latch 5 outputs data b, the adder 6 inputs the output data b of the latch 5 and the output data a of the latch 7, so the adder 6 outputs a+b.

By repeating the same operation as above four times, the adder 6 outputs a+b+c+d, and this output is transferred to the latch 8.
latches.

By the way, the latch 8 is connected by shifting its input by two bits. As a result, latch 8 latches the value obtained by dividing the input by four. That is, (a+b+c+d)/
Latch the value of 4.

Here, it will be a break in one block, so latch 7
is cleared, and the same operation as above is repeated for the next block (blocks after e), and the average values in the one-dimensional direction within the block are sequentially latched into the latch 8.

Next, the two-dimensional calculation circuit 3 will be explained.

The two-dimensional arithmetic circuit 3 includes an adder 9, a latch 10, a line buffer 11, and an address counter 12.

The latch 10 is cleared when the block changes in the two-dimensional direction [1 (that is, 166 pixels), and the period during which it is cleared is a period corresponding to l lines (4 pixels).

The latch 8 outputs the average density in the one-dimensional direction within the l block, and the two-dimensional calculation circuit 3 calculates this in the two-dimensional direction. In this case, the data for the next line is not sent until all the data for that line has been sent, so the calculation result is held in the line buffer 11. The line buffer 11 executes two cycles of reading and writing during one cycle of address counting by the address counter 12.

That is, while the average value of the first line of l block is being output, there is a read cycle and a write cycle in which the calculation results of the block of the previous line are transferred to the image memory 4. If the outputs of the latch 8 are input to the two-dimensional arithmetic circuit 3 in the order of a', eo, ..., the latch 10 is cleared at this time, so the outputs of the adder 9 are a', eo, etc. , . . . and this data is sequentially written in the write cycle.

The period during which the second to fourth lines in the l block are being output is a read cycle. In this read cycle, the contents of the line buffer 11 are read to the latch 10, and the result of adding the data read in the read cycle and the output data of 7chi8 is loaded into the line buffer 11 in the write cycle, that is,
In the first line of Fig. 1, a゛, eo, ... of the first line is read in the read cycle, and (a'+f'), (e+j'), ... are written in the write cycle. .

By repeating this, the addition operation in the two-dimensional direction within the l block is executed, and the result is transferred to the image memory 4 in the processing cycle of the next line (the first line of the lower block). At this time, as before, by shifting the connection by 2 bits and transferring it, A= ('+p' to a'+f'+)/4= (a+b+
c + d + f + g + h + i + + 1 + m + n +
p+q+r+S)/l6 is realized.

Next, the operation of converting the resolution by four times when outputting the stored contents of the image memory 4 will be explained.

FIG. 4 is an explanatory diagram of interpolating an intermediate point from four points A, B, and C1D in the above embodiment.

Here, -dimensional linear interpolation of an arbitrary point E between two points A and B (point E is shown in FIG. 4) is E= (1-t)A
+tB・・・・・・・・・・・・・・・(1) Note that O≦[≦1, therefore, the fifth
G of arbitrary α between the four points A, B, C, and D on the grid shown in the figure
For two-dimensional linear interpolation, if the point on AC is E and the point on BD-I is F, then G = (1-s)E+5F E= (1-t)A+tc F= (1-t)B+LD・・・・・・・・・・・・・・・
...It is expressed as (2). Note that 0≦S≦1 and O≦t≦1.

Here, when converting the resolution by four times, s and t take only four values: 0, Si, and 54%, as shown in FIG.

In the above equation (1), when t takes the value of 0, C, island, remainder, E
A4 is as follows.

When shi=0, E is A, when t=storm, E is (3A/4+B/4), when t=station, E is (A/2+B/2), and when t-%, E is (A
/4+3B/4)・・・・・・・・・・・・・・・・・・
......(3).

FIG. 6 is a block diagram showing an example of a one-dimensional linear interpolation circuit 30 that implements the above equation (3).

This -dimensional linear interpolation circuit 30 includes multiplexers 21 and 22 that select one line from four 8-bit lines, and
It consists of bit adders 24, 25, and 26 and a 2-bit counter 23.

The multiplexers 21 and 22 are an example of a selection means that divides the density data of a predetermined pixel in stages and selects one from a plurality of values. The 2-bit counter 23 is an example of a counting means that supplies a selection signal to these selection means. The adder 26 is an example of an adding means that adds the output data of these two selection means.

1/2.1/4 of the human power density in the above equation (3) can be realized by bit shifting and wiring, and 3/4
can be realized by adding 7 dars 24 or 25 to l/2 and l/4.

These (U's) are sequentially selected and outputted by the multiplexers 21 and 22 under the control of the 2-bit counter 23 (by the select signal outputted by the 2-bit counter 23), and these values are added by the adder 6. -Dimension linear interpolation can be realized.

FIG. 7 is a diagram showing an example of a circuit that realizes the two-dimensional linear interpolation circuit 40 by configuring the -dimensional linear interpolation circuits 41 and 42 in two stages.

The two-dimensional linear interpolation circuit 40 includes a -dimensional linear interpolation circuit 41 .
42, 43, an input latch 44, and an output latch 45. Further, each of the -dimensional linear interpolation circuits 41, 42, and 43 is the same as the one-dimensional linear interpolation circuit 30 shown in FIG.

Then, the two-dimensional linear interpolation circuit 40 realizes equation (2). In other words, by inputting the densities of four points A, B, and C1D shown in FIG. 3, the D of each pixel in the block is
I'f (4/4 picture; density of each pixel in k) is expressed by the formula (
Interpolate as shown in 2).

FIG. 8 is a diagram showing a circuit that performs resolution conversion using the two-dimensional linear interpolation circuit 40.

This embodiment is composed of a buffer circuit 50 and a two-dimensional linear interpolation circuit 40, and the buffer circuit 50 includes an address counter 51 and a ? Line buffer 52, Chi2chi53.
54, 55, 56. The 2-line buffer γ52 contains data for 2 lines (4 points A, B, C,
D) and latches 53, 54 .
55 and 56 are for simultaneously supplying the four-point data to the two-dimensional linear interpolation circuit 40.

Next, the operation of quadrupling the resolution will be described.

2947 of the image data read from image memory l
data are buffered in a two-line buffer 52, and the values of four points A, B, C, and D surrounding the point to be interpolated are input to a two-dimensional linear interpolation circuit 40. Then, in the two-dimensional linear interpolation circuit 40, the densities of the interpolation points are sequentially calculated and sent to the printer 60.

The above embodiment employs an operation of calculating the average value within a block when converting resolution from a high-resolution input device to a low-resolution memory, and this operation is performed for high-resolution input. Then, smooth filtering is performed and sampling is performed at a low frequency. This filtering operation removes input noise and removes high frequency components of the image data that cause aliasing noise when low sampling is performed.

Furthermore, at this time, even if an image expressed as a tint point, which is a problem in image processing, is input, the image data is smoothed and converted into a smooth gradation image.

Furthermore, by using linear conversion when converting the resolution from low-resolution memory to high-resolution output device, it is possible to alleviate edge elision (jaggies) that occurs due to lower resolution and achieve smooth gradation expression. .

In the above embodiment, the high-resolution image input/output device and the low-resolution image memory are connected by a resolution conversion circuit that uses density averaging and linear interpolation. The input/output of image data is carried out in rotation, and it is easy to configure an economical and efficient image processing system.

In the embodiment 1-, the resolution of the human image is converted to l/4 and then converted to four times the resolution, but it may be converted to a resolution of another ratio. In Figure 2, the resolution is converted to 1/4, but the resolution may be converted to l/N, and the embodiment shown in Figure 8 is an example of converting the resolution to 4 times. is M times (
(M is an integer between 2 and 7). Then, after converting the resolution by l/N times, M8
When converting into , the value of N and the value of M may be the same or different.

Further, in the two-leg embodiment, the density data is expressed in 8 bits, but the density data may be expressed in other bit lengths (data lengths).

[Effect of oscillation lη] According to the present invention, in an image data resolution conversion device that connects a high-resolution image data input device and an image memory that stores low-resolution image data, it is possible to maintain a quality higher than the resolution of the image memory. It has the effect of being able to input and output images.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram when converting the resolution to 1/4. FIG. 2 is an example of a circuit that converts the resolution to 1/4. FIG. 3 is an explanatory diagram when converting the resolution four times. FIG. 4 is an explanatory diagram of one-dimensional linear interpolation in the above embodiment. FIG. 5 is an explanatory diagram of two-dimensional linear interpolation in the above embodiment. FIG. 6 is a circuit diagram showing an example of a one-dimensional linear interpolation circuit in the embodiment described in E. FIG. 7 is a circuit diagram showing an example of the two-dimensional linear interpolation circuit in the above embodiment. FIG. 8 is an example of a circuit that quadruples the resolution using two-dimensional linear interpolation in the two-legged embodiment. FIGS. 9(1) and (2) are based on the conventional resolution conversion theory 1j11. 2... -dimensional arithmetic circuit, 3... two-dimensional arithmetic circuit, 21.22... multiplexer, 30. 41-43... -dimensional linear interpolation circuit, 40...
・Two-dimensional linear interpolation circuit, 42...4977 circuit. Patent Applicant Canon Co., Ltd. Agent Arata Yokubo - Fig. 3 Fig. 4 CD r---"-- 1111 --- Figure 7 Figure 9

Claims (1)

[Claims] In an image data resolution conversion device that connects a high-resolution image data input device and an image memory that stores low-resolution image data, an adding means and a latch means convert N×N pixels (N is a one-dimensional arithmetic circuit that sequentially calculates the density average value of each pixel in a one-dimensional direction in one block consisting of 2 or more integers); An image data resolution conversion device comprising: a two-dimensional calculation circuit that sequentially calculates the density average value of each pixel in two-dimensional directions within a block;