JPH0311880A - Picture element density converter - Google Patents

Abstract

PURPOSE:To apply excellent picture density conversion to a picture with an optional multiple, to reduce the hardware scale and to improve the processing speed by applying projection method processing and error diffusion processing to a binary picture. CONSTITUTION:An output device 1 sends a binary picture synchronously with a synchronizing signal, a projection method processing section 2 adopts the projection method so as to increase/decrease picture element number with an optional multiple, its output signal is interleaved periodically by an interleave processing section 3 and number of picture elements is decreased to one over an integral number. An error diffusion processing 4 applies error diffusion processing to the processing signal and binarized by a prescribed threshold level at a simple binarizing circuit 5. Then according to a command from a mode changeover switch 7, a multiplexer 6 selects and sends outputs of the processing section 4 and the circuit 5.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a pixel density conversion device, and particularly to a pixel density conversion device, which is a pixel density conversion device, and in particular, a pixel density conversion device for converting pixel density.
The present invention relates to a pixel density conversion device that converts a value image into a pixel density at an arbitrary magnification.

[Prior Art] When communicating between facsimiles of different resolutions or enlarging or reducing image data using an image editing device, etc., it is necessary to convert the pixel density of the image.

Conventionally, various methods have been proposed as pixel density conversion methods for binary images, such as the SPC method, the logical sum method, the 9-division method, the projection method, the linear interpolation method, and the distance inverse proportional method (Information Processing Society of Japan Journal V
o1.26 rh5). Among these, the projection method is known as a method for converting pixel density well at any magnification.

[Problems to be Solved by the Invention] However, when converting the number of pixels in this projection process, especially when the number of pixels is reduced, the smaller the magnification, the more pixels before conversion overlap with one pixel after conversion. will increase. Therefore, a large number of line buffers are required to store images for when the magnification is small, and a large number of multipliers and adders are also required, resulting in an increase in hardware scale and a reduction in processing speed.

The present invention has been made in view of these points,
It is an object of the present invention to provide a pixel density conversion device that satisfactorily converts the pixel density of an image at an arbitrary magnification by projection method processing, and also reduces the hardware scale and increases the processing speed.

[Means for Solving the Problem] In order to solve this problem, the pixel density conversion device of the present invention is a pixel density conversion device that converts the pixel density by increasing or decreasing the number of pixels, and which converts the pixel density by increasing or decreasing the number of pixels. The image forming apparatus includes a first scaling means that performs scaling processing, and a second scaling processing means that changes the number of pixels for each predetermined pixel.

Here, the second scaling means changes the number of pixels by thinning processing.

Further, the second magnification changing means changes the number of pixels by averaging value processing.

Further, the second magnification changing means changes the number of pixels by majority decision processing.

[Operation] In such a configuration, the first
By including a scaling means and a second scaling processing means that changes the number of pixels for each predetermined pixel, it is possible to satisfactorily convert the pixel density of an image at any magnification by projection method processing, and to reduce the hardware scale. Increased pressing processing speed.

[Embodiments] Hereinafter, several embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(First Example) FIG. 1 is a block diagram showing the configuration of a pixel density conversion device of this example. In the books and figures, 1 is an image output device that stores binary images and outputs images in synchronization with a synchronization signal;
2 is a projection method processing unit that increases or decreases the number of pixels at an arbitrary magnification using a projection method, and 3 is a projection method processing unit that periodically thins out the signal output from the projection method processing unit 2 to reduce the number of pixels to an integral number. A thinning processing section 4 performs error diffusion processing on the signal output from the thinning processing section 3; 5 binarizes the signal output from the interrogation processing section 3 at a certain threshold level; 6 is an error diffusion processing unit 4.
and a multiplexer for selecting the signal of the simple binarization circuit 5,
7 is a mode changeover switch that outputs a select signal for the multiplexer 6, and 8 is a crystal oscillator that generates a basic operating clock.

A detailed explanation of each part is given below.

<Image Output Device> The image output device 1 outputs internally stored image data at the timing shown in FIG. Note that the image data stored in the image output device 1 may be data read from an image reading device or data transmitted from outside. The image output device operates in synchronization with the rising edge of the input signal, the readout clock. First, when the first line read pulse is input, the page synchronization signal is set to High and at the same time, the image signal for the first line is output. For each of the second and subsequent line read pulses, 1942 worth of image signals are output. When you have finished outputting the image signal for one page, set the page synchronization signal to Low with the next line read pulse.
Make it. The image signal for one line is output in synchronization with the image clock and the line synchronization signal, which are output directly from the read clock.

Projection Processing Unit> The projection processing unit 2 increases or decreases the number of pixels at an arbitrary magnification in both the main scanning direction and the sub-scanning direction.

FIG. 3 is a diagram showing pixels before and after projection method conversion. In the projection method, the shape of the pixel before conversion is assumed to be a square, and the side length is the length of the side of the pixel before conversion multiplied by the reciprocal of the conversion magnification in both the main scanning direction and the sub-scanning direction (dashed line in Figure 3). This method involves superimposing a rectangle (solid line in FIG. 3) on the pixel before conversion, and using the proportion of the black area included in the rectangle as density information. The projection processing section 5 performs density conversion of fractions other than the density conversion of an integral multiple or a fraction of an integer in the majority decision processing section 28 and the thinning processing section 3.

FIG. 4 is a block diagram showing an example of the configuration of the projection processing section.

In the figure, 101 is a register for setting the magnification in the main scanning direction;
Reference numeral 102 is a register for setting whether the conversion in the main scanning direction is enlargement or reduction, and is set to "1" for enlargement and "0" for reduction.

103 is a register for setting the magnification in the sub-scanning direction; 104
is a register for setting whether the conversion in the sub-scanning direction is enlargement or reduction, and is set to "1" for enlargement and "0" for reduction. Note that the registers 101 to 104 are set by a CPU (not shown). 105 is a calculation unit for reduction in the main scanning direction; 106 is a calculation unit for expansion in the main scanning direction; 107
109 is a calculation unit for reduction in the sub-scanning direction, 1o8 is a calculation unit for expansion in the sub-scanning direction, 109 is a line synchronization signal generation unit that generates a line synchronization signal by frequency-dividing the signal from the crystal oscillator, 11
0 is a read pulse generation unit that frequency-divides the signal from the crystal oscillator and generates a read pulse, and 111 is the output of the register 102 that is “○°”.

When the signal from the main scanning direction reduction calculation unit 105 is
This is a multiplexer that outputs the signal from the main scanning direction enlargement calculation unit 106 when ".

A multiplexer 112 outputs a signal from the sub-scanning direction reduction calculation section 107 when the output of the register 104 is "0", and outputs a signal from the sub-scanning direction enlargement calculation section 108 when the output of the register 104 is "1".

113 is an inverter, 114 is an AND gate, 115 is an OR gate, 116 is an AND gate, and 117 is an OR gate. Also, 118 is an inverter, 119 is an AND
gate, 120 is an OR gate, 121 is an AND gate,
122 is an OR gate. 123 and 124 are constants 25
Constant parts 125 and 126 that output 6 are line buffers, and constitute a double buffer. 127 is 125.
A multiplexer that switches the output of 126, 128 a toggle flip-flop that toggles as if a line synchronization signal is input, 129, 130, 131, and 132 D
It's a flip flop.

First, the operation of the main scanning direction reduction calculation unit 105 will be explained.

The magnification is 200/256. FIG. 5 shows the overlap of the sides before and after the conversion. The main scanning direction reduction calculation unit 105 performs processing according to the magnification set in the main scanning direction magnification register 101. Further, the clock serving as a reference for operation is a clock input from the crystal oscillator 10.

Processing of each line is performed in synchronization with a signal input from line synchronization signal generation section 109. The signals output from the main scanning direction reduction calculation unit 105 are an image clock control signal and a side length output. The image clock control signal is a negative logic signal, and when it is "O", the image clock is enabled.

Further, the length of the side is a value in the range of 1 to 256, and it is a 9-bit parallel signal. Since the conversion magnification is 200/256, "0" is set in the main scanning direction enlargement/reduction register. Therefore, the multiplexer 111 selects and outputs the side length of the main scanning direction reduction calculation unit 105. Also, the lower input of the AND gate 114 becomes High,
Image clock is controlled. Since the lower input of the AND gate 116 becomes Low and the lower input of the OR gate 117 becomes Low, the read clock output is the clock input from the crystal oscillator as it is.

FIG. 6 is a timing chart of 200/256 reduction processing in the main scanning direction.

Next, the actual calculation method for edges will be explained with reference to FIG. First, the length of the side of the first pixel is output as 200. below,
In order, the length of the side is 200- (256-200) = 144200- (2
56-144)=88 200-(256-88)=32.

According to the same calculation, the length of the next side is 200-(256-32)=-24, which is negative, but as you can see from side e in Figure 5, this is the length of the converted pixel. indicates that three pixels overlap before conversion.

Therefore, the length of the side is -24+200=176.

At this time, in order to match the post-conversion prime numbers, as shown in Figure 6, the image processing device clock control signal is set to old gh for one clock of the clock from the crystal oscillator, and the image clock output is thinned out. conduct.

The length of the next side is 200-(256-176)=120, and the subsequent processing is repeated.

Note that the side calculation processing is performed in synchronization with the image clock output.

Next, the operation of the main scanning direction enlargement calculation section 106 will be explained.

The magnification is 700/256, and FIG. 7 shows the overlap of the sides before and after conversion.

The main scanning direction enlargement calculation unit 106 performs processing according to the magnification set in the main scanning direction magnification register 101. The clock that serves as the reference for operation is a clock input from a crystal oscillator. Each line is processed by the line synchronization signal generator 1.
This is done in synchronization with the signal input from 09. The signals output from the main scanning direction enlargement calculation section 105 are a read clock control signal and a side length output. The read clock control signal is a negative logic signal, and when it is 0, the read clock is enabled. The side length is a value in the range of 1 to 256, and the signal is a 9-bit parallel signal. Since the conversion magnification is 700/256, 1 is set in the main scanning direction enlargement/reduction register. Therefore, multiplexer 111
selects the length of the side of the main scanning direction enlargement calculation unit 106.

Output. Also, the lower input of the AND gate 114 is L
ow, and the lower input of the OR gate 115 becomes Low, so that the image clock output is the clock input from the crystal oscillator as it is.

FIG. 8 is a timing chart of 7007256 enlargement processing in the main scanning direction.

Next, the actual calculation method for edges will be explained with reference to FIG. First, the length of the side of the first pixel is output as 256. The length of the next side is 700-256=444>256, so 256 is output. When the above inequality sign is >, the read clock control signal is set to "l" (disabled). Since the length of the next side is 444-256=188≦256, 188 is output. Here, the read clock control signal is set to "0" to enable the read clock and request data for the next pixel from the image output device l.

The length of the next side is (188+700) -256=632>256, so the length of the 0th side that outputs 256 is 632-2
Since 35=376>256, 256 is output.

Thereafter, the same process is repeated. Note that the side arithmetic processing is performed in synchronization with the clock input from the crystal oscillator.

The calculations for the sides of reduction in the main scanning direction and expansion in the main scanning direction have been described above, but calculations are also performed in a similar manner in the sub-scanning direction.

On the block diagram and timing chart, the main scanning is used as the sub-scanning, the clock input from the crystal oscillator is used as the readout pulse, the image clock is used as the line synchronization signal, and the side calculation result A
, B can be replaced with C and D, respectively, and the read clock can be replaced with a line read pulse. - Next, image data control and image signal calculation will be explained. The image data is double-buffer controlled by line buffers 125 and 126, and the image data delayed by (1) line is input to the D flip-flop 129. The data in D flip-flop 129 is transferred to D flip-flop 13.
1 causes a delay of one pixel. Further, the image signal input is inputted as is to the D flip-flop 130. The data of D flip-flop 130 is transferred to D flip-flop 132.
is input and is delayed by one pixel.

Through the above processing, four pixels of 2×2 are referred to.

As shown in FIG. 9, calculate the combined area, AXC, BXCAXD, BXD, by multiplying the side calculation results A and B in the main scanning direction and the side calculation results C and D in the sub-scanning direction.
Further, the corresponding image data v, w, x, and y are multiplied together, and the added value becomes the density level of the pixel after conversion. When all bits of the 9-bit side data are operated, the result is 17 bits. The reason why it is not 18 bits is because the maximum value of 9-bit side data is 100Hex. For the image signal output, the necessary number of bits from the higher order of the 17 bits of the calculation result may be adopted.

As explained above in the case of a reduction in the number of pixels, if the magnification of the number of pixels is 1/2 or more but less than 1, it is possible for 3 pixels before conversion to overlap one side of the pixel after conversion. can be,
When conversion is performed at this magnification in both the main scanning direction and the sub-scanning direction, a maximum of nine pixels before conversion overlap one pixel after conversion.

Further, when the magnification is less than 1/2, even more pixels overlap. Performing calculations on all these pixels increases the hardware scale.

Therefore, in the projection method processing section 2 of this embodiment, the reference pixels are up to 4 pixels in total, 2 pixels in the main scanning direction and 2 pixels in the sub-scanning direction. Therefore, when the number of reference pixels exceeds four pixels, approximation processing is performed.

For example, in both the main scanning direction and the sub-scanning direction shown in FIG.
An example of correspondence between pre-conversion pixels and post-conversion pixels when the number of pixels is reduced by a magnification of 136/6 will be explained. There are 9 pixels before conversion that overlap pixel P after conversion, and this area is divided into a, b,
c, d, e, f.

Represented by g, h, i. Let the area of a-1 be S, ~S 1. a
-S color to 1. 〜Il. ■ is set to °°1 when it is black and "0" when it is white.The approximation method is that area C is the same color as the other areas, area g is the same color as area d, and areas f, h, and i are the same color as area e. According to this method, the density Ip of the pixel P is approximated as follows.

Ip □ (S-・I-” (Sc in Sb)・Ib◆<
sa+st＞”tn” (S−+Sr”Sh+S+
)・1. )/256・256= ((136÷40)・
80 + (136◆40)・(136440) )7
It becomes 256・256 0.6875.

On the other hand, in the case of an increase in the number of pixels, there is no need for approximation because the number of pixels before conversion that overlap one pixel after conversion is four or less, regardless of the magnification.

Note that the length of one side after conversion is not limited to 256 and may be calculated using any value. However, the length of one side is 2".
', division can be done by a shift process when performing concentration calculations, which not only makes it easier to configure hardware and reduces the hardware scale, but also has the effect of increasing processing speed. Also, in this example, the approximation was performed by limiting the position of the reference pixel, but for example,
Two pixels with large overlap may be taken out as reference pixels.Furthermore, the reference pixels are not limited to 2×2, and depend on the balance between the reproducibility of the reproduced image, the hardware scale, and the processing speed.

Thinning Processing Section> FIG. 11 is a block diagram showing an example of the configuration of the thinning processing section. In FIG. 11, 301 is an image clock control section, 302 is a line synchronization signal control section, and 303 is a D flip-flop. The image clock control unit 301 performs control to thin out image clocks in accordance with the mode signal. This thinned-out image clock is input to the D flip-flop 303 and synchronized with the image signal. In addition, the line synchronization signal control section 3
02 performs control to thin out line synchronization signals in accordance with the mode signal.

FIG. 12 is a timing chart when the number of pixels is reduced by half in the sub-scanning direction in the majority decision processing section and the thinning processing section. In the same figure, the number of lines is reduced to half by thinning out the line synchronization signal and image signal output.
decrease to

Further, FIG. 13 is a timing chart when the number of pixels is reduced by half in the main scanning direction.

In the figure, the number of pixels is reduced by half by thinning out the image clocks to be output.

Error Diffusion Processing Unit> Next, the error diffusion processing unit will be explained. When the projection method is applied to an image that has undergone pseudo-halftone processing using the dither method, etc.,
When the calculation result is simply binarized (that is, binarized using a fixed threshold value), moiré is emphasized due to the quantization error, resulting in severe deterioration of image quality. In this embodiment, in order to prevent image quality deterioration due to such quantization errors, binarization processing is performed using an error diffusion method.

FIG. 14 shows a block diagram showing an example of the configuration of the error diffusion processing section. The pixel density or brightness of the projection method output is determined by the difference between the two pixels previously generated in surrounding pixels while passing through the one pixel delay elements 51a to 51d, the delay element 53 which is one pixel less than one line, and the adders 52a to 52d. A valuation error of 8!1%84 is added. The density value or luminance including the binarization error of the surrounding pixels is binarized by the binarization processing unit 54 using a constant threshold value, and the value becomes the density or luminance of the pixel to be determined.

Next, the quantization error caused by this binarization is calculated by the binarization error calculation section 55 and distributed as 01 to e4 by the error distribution processing section 56. The binarization error calculation unit 56 calculates the binarization error by e.
, the input density to the binarization processing unit is In, the threshold value is T, and the binarization output is “Bi” or “0”. Also, in the error distribution unit 56, e1 to e4 are calculated as follows, for example. .

e, to e4 are distributed to the surrounding pixels of the pixel of interest as shown in FIG.

Note that although the examples shown in FIGS. 14 and 15 are cases in which the error is diffused to four surrounding pixels, the present invention is not limited to this, and the determination may be made in consideration of image quality and circuit scale.

However, in order to eliminate moiré well, the binarization error should be set to 10.
0% needs to be diffused to the surrounding area. That is, Σe, :FE
eo is determined so as to satisfy (n: the number of surrounding pixels to which the error is distributed).

Binarization processing using the minimum average error method> Also, instead of the error diffusion processing section, the
The same is true even if a value processing section is used.

FIG. 16 is a block diagram showing the configuration of a density preserving binarization section using the minimum average error method. The density of the pixel converted by the interpolation method is determined by applying a weighting coefficient α specified by the weighting generator 61 to the error data ε1° between the previously generated input data xlJ and the output data YIJ stored in the error buffer memory 60. 5. The multiplied value is normalized, adder 6
2 is added. Writing this as a formula is as follows.

An example of weighting coefficients is shown in FIG.

Next, the correction data XIJ' is compared with a threshold value in the binarization circuit 63, and output data YIJ is output. Here YIj
is binary data such as Y, 18, or Ymln (for example, 1 and O).

On the other hand, the arithmetic unit 64 calculates the difference ε-1 between the correction data XIJ and the output data YIJ, and this result is stored in the corresponding pixel position 65 of the error buffer memory 60(7). By repeating this operation, binarization processing using the minimum average error method is executed.

Binarization Process Using a Constant Threshold In the simple binarization processing section 5, the density of the converted pixel obtained by the projection method or the projection method is binarized using a constant threshold.

Each block has been explained above.

Switching of Multiplexer 6> The overall flow of signals is switched by the mode changeover switch 7 depending on the nature of the image output from the image output device 1.

The multiplexer 6 selects the signal output from the error diffusion processing unit 4 when the image output from the image output device 1 is an image subjected to pseudo-halftone processing. Furthermore, if the image output from the image output device 1 is a simple binarized image, the signal output from the simple binarization circuit 5 is selected. If the projection method processing section performs conversion of a fractional magnification that is not an integral multiple on an image that has been subjected to pseudo-halftone processing, moiré will occur if the image is processed by the simple binarization circuit 5.

Therefore, the error diffusion processing section 4 performs processing to prevent the occurrence of moiré. Furthermore, when the projection method processing section performs fractional multiplication on a simple binarized image, the error diffusion processing section 4
If you process with
Edges may become blurred. Therefore, the simple binarized image is processed by the simple binarization circuit 5 to prevent image quality deterioration in the text portion.

The switching of the multiplexer 6 depending on the nature of the image to be processed has been explained above, but the switching may be performed by switching the multiplexer or from an operation panel (not shown), or by using the CPU.
etc. may manage the characteristics of the image output from the image output device 1, and the CP LJ may output a control signal based on the information to switch. For example, a method of separating the pseudo halftone processing part and the simple binarization part based on the number of change points, pattern structure, etc. can be considered.

(Second Embodiment) FIG. 18 is a block diagram showing the configuration of a pixel density conversion device of this embodiment. In this figure, like reference numbers refer to the same components as in FIG. In FIG. 18, instead of the thinning processing section 3, an averaging processing section 3' is provided which averages the signals output from the projection method processing section 2 and reduces the number of pixels to an integer of -.

Averaging Processing Unit> The averaging processing unit 3' reduces the magnification by an integer in both the main scanning direction and the sub-scanning direction.

FIG. 19 is a block diagram showing an example of the configuration of the averaging processing section 3'. In the figure, 401 is a line buffer, 404 to 407
is an N-bit D flip-flop, 420 is an image clock control section, 421 is an average value calculation section, and 422 is a line synchronization signal control section. In this averaging processing section, first, the line buffer 401 buffers one line of image data, refers to a total of two lines of image data including the line currently being input, and then shifts the data using each D flip-flop. and refer to 4 pixels of 2×2. The four-pixel data is manually input to an average value calculating section 421 and outputs an image signal. A mode signal is also input to the address line, and the magnification can be changed simply by switching the mode signal. The image clock control unit 420 thins out the image clock according to the main scanning magnification selected by the mode signal. The line synchronization signal control unit 422 thins out the line synchronization signals in accordance with the sub-scan magnification selected by the mode signal.

Although the above description has been made with a configuration capable of reducing the size by 1/2 in the main scanning direction and 1/2 in the sub-scanning direction, the reduction rate may be increased by further using a line buffer and a D flip-flop.

The timing chart for reducing the number of pixels by half in the sub-scanning direction and the timing chart for reducing the number of pixels by half in the main scanning direction are the same as the first example of the first embodiment.
This is the same as FIGS. 2 and 13. For example, when the image signal is reduced by half in both the main scanning direction and the sub-scanning direction, n of 4 pixels in a block of 2 pixels in the main scanning direction and 2 pixels in the sub-scanning direction is
The average value of multi-value data of bits is calculated and outputted as an n-bit signal.

(Third Embodiment) FIG. 20 is a block diagram showing the configuration of a pixel density conversion device of this embodiment. In this figure, the same reference number
Refers to the same component as in the figure. In FIG. 20, the thinning processing section 3
Instead, the projection method processing section 2 further reduces the number of pixels of the signal output from the majority processing section 3'' which has been thinned out by an integer.

Majority decision processing unit> The majority decision processing unit reduces the number of pixels by an integer minus magnification in each of the main scanning, direction, and sub-scanning directions. Fig. 21 is a block diagram showing an example of the configuration of the majority decision processing unit. be. In the figure, 2'O1, 202° 203 is a line buffer, 204
219 is a D flip-flop, 220 is an image clock control section, 221 is a majority data ROM, and 222 is a line synchronization signal control section.

In the main majority decision processing section, first, the line buffers 201 to 20
．． 3, buffers the image data for 3 lines, refers to the image data for a total of 4 lines including the line being manually input, and then shifts the data with each D flip-flop to refer to 166 pixels of 4 × 4. do. The 166 pixel data is input to the majority data ROM 221 and outputs an image signal. The content of the ROM data is that when "1" is greater than or equal to "O°" for 166 pixels input to the address line, "1" is output as data, and when "1" is less than "O", "O" is output. It is written to output.

A mode signal is also input to the address line, and it is possible to change the magnification simply by putting data for various conversions into the same ROM and switching the mode signal.

The image clock control unit 220 thins out the image clocks in accordance with the main scanning direction magnification selected by the mode signal. For example, if the image clock is multiplied by 1/2, the image clock is thinned out every other clock, and if it is multiplied by 1/4, the image clock is subtracted by 3 clocks and 1 clock is output.

The line synchronization signal control unit 222 thins out the line synchronization signals in accordance with the magnification in the sub-scanning direction selected by the mode signal.

Although the above description has been made with a configuration capable of reduction at a speed of 1/4 in the main scanning direction and 1/4 in the sub-scanning direction, the reduction rate may be increased by further using a line buffer and a D flip-flop. Moreover, the majority decision data ROM 221 may be constructed from a logic circuit.

Setting the magnification> Next, the magnification settings for each part will be explained.

The thinning processing section, the averaging processing section, and the majority processing section have a function of decreasing the number of pixels by an integer, and the projection processing section has a function of increasing the number of pixels and decreasing the number of pixels by an arbitrary magnification. The projection method processing section has up to four reference pixels, and when performing a process of reducing the number of pixels, the area in which approximation is used increases, and the deterioration of image quality due to approximation errors increases. Therefore, when the magnification exceeds 1/2, only the projection processing section performs processing.

When the magnification exceeds 1/3 and is less than 1/2, the decimation processing section, averaging processing section, or majority decision processing section performs 1/2 processing, and the fractional magnification is processed by the projection method processing section. Process. Thereafter, similarly, processing for multiplying by an integer is performed by the thinning processing section, averaging processing section, or majority processing section, and processing for multiplying by an integral number is performed by the projection method processing section. Although the thinning processing unit 9 average processing unit and majority decision processing unit are capable of processing 1 times the integer, the decimation processing unit, the average processing unit, and the majority decision processing unit are capable of processing 1 times the nth power of 2. It may be possible to perform double (1/2°) processing, or it may be one that has only a specific magnification.

Furthermore, to explain the magnification settings in detail, the thinning processing section, averaging processing section, and majority decision processing section have a function of reducing the number of pixels by an integer, and the projection processing section has a function of reducing the number of pixels by an integer, and the projection processing section has a function of reducing the number of pixels by up to 4 reference pixels. It was mentioned earlier that approximation is used when processing reductions. Therefore, as the scaling factor decreases, the number of regions to be approximated increases, and the deterioration of image quality due to approximation errors increases. Therefore, it is preferable to set the magnification of the thinning processing section, the averaging processing section, or the majority processing section so that the conversion performed by the projection processing section is 0.6 times or more. For example, in the case of 0.7 times, the projection processing section only performs the conversion, and in the case of 0.55 times, the conversion is performed in the decimation processing section, the averaging processing section, or the majority processing section.
The projection method processing section performs 1.1 times the processing. Also, 0435 times field 6 is the thinning processing section.

The average processing section or the majority decision processing section performs 1/3 processing, and the thinning processing section performs 1.05 processing. As mentioned above, if the thinning processing section, the averaging processing section, and the majority decision processing section are configured to be able to process 1 times the nth power of 2 (1/2''), when the processing is 0.35 times, the thinning processing is performed. The average processing section or the majority decision processing section may perform 1/2 processing, and the projection processing section may perform 0.7 processing.

In the above explanation, the magnification processed by the projection method processing section is 0.6
Although the above description has been made as 0.55 times or more, the processing magnification of the projection method processing section may be set to any value such as 0.55 times or 047 times or more, depending on the characteristics of the printer that outputs the converted image information.

In this way, when performing pixel number reduction processing, the thinning processing unit limits the conversion magnification by the projection method to a certain value or more so that it stays within that range.

Setting the magnification of the average processing section or the majority processing section has the effect of suppressing approximation errors and reducing deterioration of image quality.

[Effects of the Invention] According to the present invention, it is possible to provide a pixel density conversion device that can satisfactorily convert the pixel density of an image at an arbitrary magnification by projection method processing, and that can reduce the hardware scale and increase the processing speed.

In detail, (1) If the binary image to be converted is an image that has been subjected to pseudo-halftone processing, projection processing and error diffusion processing are effective in suppressing the occurrence of moiré even when converting a fractional magnification. be.

(2) When the binary image to be converted is a simple binarized image, performing projection processing and simple binarization processing has the effect of suppressing deterioration of edge portions of characters or figures.

(3) When the magnification of pixel count reduction is 1/2 or less, by using the projection method processing section and the averaging processing section together, the burden of projection method processing can be reduced and the hardware can be made smaller. .

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the configuration of the pixel density conversion device of the first embodiment, Fig. 2 is a timing chart of input and output signals of the image output device, Fig. 3 is a diagram showing the principle of the projection method, Fig. 4 is a block diagram showing the configuration of the projection method processing section, FIG. 5 is a diagram showing the overlap of the sides of the pre-conversion pixels and post-conversion pixels when the number of pixels in the projection method is reduced, and FIG. Fig. 7 is a diagram showing the overlap of the sides of pre-conversion pixels and post-conversion pixels when the number of pixels in the projection method is increased. Fig. 8 is a timing chart in the case of an increase in the number of pixels in the projection method processing section. Fig. 9 is a diagram showing approximated reference pixels in the projection method processing section, Fig. 10 is a timing chart of 13/256 in the main scanning direction and sub-scanning direction.
A diagram showing an example of the correspondence between pre-conversion pixels and post-conversion pixels when the number of pixels is reduced by a magnification of 6. Figure 11 is a block diagram showing an example of the configuration of the thinning processing section. Figure 12 is a 2-minute image in the sub-scanning direction. Figure 13 is a timing chart of the input and output signals of the majority processing unit 1 averaging processing unit and thinning processing unit when the number of pixels is reduced to 1 in the main scanning direction. A timing chart of input and output signals of the processing section, the averaging processing section, and the thinning processing section; FIG. 14 is a block diagram showing the configuration of the error diffusion processing section; FIG. 15 is a diagram showing an example of the diffusion matrix of the error diffusion processing section; Fig. 16 is a block diagram showing the configuration of a binarization processing unit using the minimum average error method, Fig. 17 is a diagram showing an example of a weighting matrix for the minimum average error method, and Fig. 18 is a pixel of the second embodiment. FIG. 19 is a block diagram showing the configuration of the average processing unit; FIG. 20 is a block diagram showing the configuration of the pixel density conversion device of the third embodiment; FIG. 21 is majority voting processing. FIG. 3 is a block diagram showing an example of the configuration of the section. In the figure, ■... image output device, 2... projection method processing unit,
3... Thinning processing section, 3'... Average processing section, 3''.
...Majority processing unit, 4...Error diffusion processing unit (binarization processing unit using the minimum average error method) 5...Simple binarization circuit, 6...Multiplexer, 7...Mode changeover switch, 8...Crystal oscillator.

Claims (4)

[Claims] (1) A pixel density conversion device that converts pixel density by increasing or decreasing the number of pixels, which comprises a first scaling means that performs scaling processing using a projection method, and a second scaling means that changes the number of pixels for each predetermined pixel. 1. A pixel density conversion device comprising: magnification processing means. (2) The pixel density conversion device according to claim 1, wherein the second scaling means changes the number of pixels by thinning processing. (3) The pixel density conversion device according to claim 4, wherein the second scaling means changes the number of pixels by averaging processing. (4) The pixel density conversion device according to claim 1, wherein the second scaling means changes the number of pixels by majority voting.