JPS62173754A - Memory cell - Google Patents

Abstract

PURPOSE:To further increase the electrostatic capacity of a capacitor by forming a groove obliquely with respect to the main surface of a semiconductor substrate, and forming the capacitor directly under the main surface utilized for other object. CONSTITUTION:A memory cell is formed of a semiconductor substrate 1, an element separating field oxide film 2, a groove 3a, a gate oxide film 5, a cell plate 6, word lines 8a, 8b, and a polycrystalline silicon film 9 for filling the groove 3. The groove 3a is dug inward in an oblique direction from the main surface of the substrate 1, and formed by ion etching by determining the ion direction from the upper right side to the lower left side. With this construction, the portion of the substrate 1 under an MOS transistor 20 can be utilized as a part of a capacitor 30.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a one-transistor, one-capacitor type memory cell that utilizes a groove dug in an oblique direction.

[Conventional technology]

FIG. 2 is a cross-sectional view showing the structure of a conventional memory cell.
(1) A T4 semiconductor substrate, here a p-type silicon substrate, (2) an element isolation field oxide film with a thickness of about 0.5)tm selectively formed on the surface of the substrate (1), ( 3)
is a groove dug vertically inward from the surface of the substrate (1), (
4) is the first n-shaded area formed on the surface of the groove (3) and a part of the original surface of the substrate (1), and (5) is the first n-shaded area (
4) a first gate oxide film of about 0.03 pm formed on the Ilm; (6) a first gate oxide film of about 0.5 pm formed on the first gate oxide film (5); A cell plate (4t
), (5t), and (6t) are the first n shadow regions (4
), the first gate oxide film (5), and the cell plate (6) are all part of the groove (3), and the 7'L first electrode, dielectric layer, second electrode, ( 7) has a thickness of approximately 0.04 mm formed on the surface of the substrate (1) and cell plate (6).
Second gate oxide film of voice m, (8a).

(8b) are mutually adjacent word lines formed of molybdenum silicide @ with a thickness of about 0.5 μm formed on the second gate oxide film (7), and (9) are for planarization. , second polycrystalline silicon film filling groove (3), (1
0a) and (1ob) are the second n shadow regions constructed on the surface of the substrate (1), and α1) is the thickness approximately covering the surface of the substrate (1) after the above is formed. A 1 μm overlay oxide pattern (1>5 consists of an approximately 1.2 mm thick aluminum layer formed on the overlay oxide @Qυ, and a bit line connected to the second n shadow region (1011,) K; The gate of j is wa L.

line ('81M), source, drain or the second G line n shadow region 0L) a), (], Oh), which is an insulated gate sparrow effect transistor (hereinafter MO9) which is a part of the memory cell.
(abbreviated as T), ■ is the first electrode (41
), a third electrode (6t), and a dielectric layer (5t), the memory is composed of at least a second electrode (6t), and a dielectric layer (5t); Ni 7) 2(
It is configured as ・)'', 4 (3) is set to 4 (3), and 4 (3) is set to 0. Nui no Ashi wo Dai K t,,
tl: Briefly explain one work as a memory that makes memories more concrete.
) is unselected and low level (,Q,,jisuke MOofE
Since T is disconnected from '1ljF, the charge accumulated in the capacitor (to) is preserved regardless of the write or read refresh mode, and the charge is stored between the word line (8a) and the bit line 0.
When (2) is selected at the same time, the word line (8a) is at a high level and MOST (a) is conductive, and the bit line 02 is connected to the data input circuit in the write mode and to the data output circuit in the read mode. Therefore, when writing, the potential of the first capacitor (to) of the capacitor (to) is set to a high level or a low level (5-), keeping in mind the external data.・[When reading from the memory, the synopsis 'F') is given (4) Ic and 1.
Take the difference in potential to the outside, put it out, logic 2 (direct!,
' = 4r is read out, and, to add, = oq memory is selected without selecting the mode (τ function) N, and the memory of the space connected to the 1-digit word line (8a) is selected. t5: Even if the A bit line is not selected, each bit line is prepared.
A logical two-level signal with an extremely small difference in position appearing on the bit line is amplified by charges released from each memory cell, and the potential applied to the memory cell is reproduced, that is, refreshed. ! When there is no bit line that has been returned to near normal, it is a refresh mode, and in read mode, the refreshed pit voltage potential is output through the output circuit. , take it out to the outside, and select the 6-bit line at 1 in write mode. Exceptionally, the drive capacity of the input circuit is selected to be larger than the memory sensor and the amplifier, but the input circuit is selected before the increase @ starts. are connected to each other, and through this bit line, a potential corresponding to external data is applied to the memory cell regardless of the original message, so that old data can be stored. After that, the MO8T of each memory cell is cut off, and the data that has been refreshed or written is retained in each memory cell.

[Problem that the invention seeks to solve]

In a conventional memory cell like the one above, its capacitor (
7) is extended only directly downward from the main surface of the semiconductor substrate (1), and the other MO8T fJ- and the part of the substrate (1) under the field oxide pattern (2) are not utilized. there were.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a memory cell in which a capacitor (7) is formed using the above-mentioned unused portion.

[Means for solving problems]

The memory cell according to the present invention is composed of an insulated gate field effect transistor and a capacitor, and the capacitor is composed of a first electrode, a second electrode, and a dielectric. The dielectric layer and the second electrode are provided inside the semiconductor substrate along a groove formed in the substrate in an oblique direction so as to go under the main surface of the semiconductor substrate, and the dielectric layer and the second electrode are disposed on the surface of the groove. [Function] In this invention, the groove is provided in a diagonal direction with respect to the main surface of the semiconductor substrate, and a capacitor is placed directly below the main surface, which is used for other purposes. to be able to form.

[Heavenly example]

FIG. 1 is a sectional view showing an embodiment of the present invention;
3a) is a groove dug diagonally inward from the main surface of the substrate (1), and other symbols are the same as or equivalent to the conventional one shown in FIG.

The groove (3a) is formed by ion etching with the ion direction determined from the upper right to the lower left in the paper.

Since this embodiment is configured as described above, in this example, M
It is clear that the part of the substrate (1) below the O8T m can be used as part of the capacitor 2, and the above problems can be solved.

Also, since this memory cell is circuit-wise the same as the conventional one, it goes without saying that it will operate without any problems like the conventional one. (3a
), but as shown in FIG.
Although the case where the n-type region (4) is formed in the first polycrystalline silicon (6) may be used, the channel portion formed in the substrate (1) may also be used. ) formed in the groove (3a
), but as shown in Figure 4 <p,
A groove (3a) may be provided within the well (1a).

In this case, there is another effect that is advantageous in countering soft errors caused by alpha rays, as described below. In other words, FIG.
This is a cross-sectional view showing the principle of making it difficult for the above-mentioned soft error to occur in a semiconductor device in which a well is provided, in which an electron-hole pair generated along the trajectory of an α particle has a length of several tens of μm.
However, considering the electron-hole pairs generated within the substrate (1), the substrate (1) is
Since a positive potential is given, the electrons are in the p-well (1a)
Only the holes can enter the p-well (1a) due to the so-called funnel effect, but since these are majority carriers, the electron-holes in this part eventually become polarized into the n-region 00 of the semiconductor device. Therefore, in terms of soft error prevention, the smaller the depth of the p-well (1a), the greater the effect.If the groove length is the same, it will be more effective than the conventional vertical groove. It is clear that it is contained in a shallow p-well (1a). In place of the p-well in this modification, p
Similar results can be obtained using a full epitaxial layer.

In addition, in the above embodiment, the case where the MO8T wire of the memory cell is an n-channel type is described, but by reversing the conductivity types described so far to p and n and reversing the positive and negative potential relationships, it is possible to create a p-channel type. Needless to say, the same thing can be said about shape.

〔Effect of the invention〕

As described above, the present invention provides a groove in the substrate marked with # in a diagonal direction with respect to the main surface of the semiconductor substrate, so that a capacitor can be formed directly under the main surface used for other purposes, This has the effect of further increasing the capacitance of the capacitor.

[Brief explanation of drawings]

Figure 1 of the cylinder is a sectional view showing an embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a conventional memory cell, and FIGS. 3, 4, and 5 are all cross-sectional views explaining the present invention in detail, in which (1) is a semiconductor substrate. ,
(3a) is a groove, (4t) is a first electrode, (5t) is a dielectric layer, (6t) is a second electrode, and a wire is an insulated gate field effect transistor, and a 00 capacitor. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] (1) An insulated gate field effect transistor and a capacitor, the capacitor comprising a first electrode, a second electrode, and a dielectric layer, the first electrode directed from the main surface of a semiconductor substrate toward the inside of the substrate. The dielectric layer and the second electrode are sequentially laminated on the surface of the groove, and the depth direction of the groove is the main part of the substrate. A memory cell characterized by being oblique to the surface.