JPS62172624A - Chip device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application This invention relates to improvements in chip elements such as chip fuses and chip resistors used in small electronic devices and the like.

(B) Conventional technology Conventionally, a chip fuse used in a relay control circuit using a chip element, such as an IC, has a pair of electrodes in a four-body pattern on both ends of an insulating substrate.
It is known that wire bonding is performed between the two electrodes using a wire, and a resin material is further applied onto the substrate so as to cover the entire wire.

(c) Problems to be Solved by the Invention In the conventional chip device described above, unless the electrodes made of the conductor pattern formed on the chip substrate reach the side surfaces of the chip substrate, the chip device cannot be connected to the circuit board. There is a problem in that it is difficult to solder between the four-body pattern on the circuit board and the electrodes of the chip element.

Therefore, in order to form an electrode on the chip substrate that reaches the side surface of the chip substrate, the electrode must be formed for each chip element, which is disadvantageous in that productivity is low.

The present invention was made in view of the above-mentioned disadvantages, and an object of the present invention is to provide a chip element that can be easily mounted on a circuit board and has high productivity.

(d) Means for solving the problems In order to solve the above-mentioned disadvantages, the chip element of the present invention has the following features:
A chip substrate obtained by cutting and disassembling an insulating substrate into predetermined sections along a dividing line, and a conductive pattern formed on the periphery and inner wall of a through hole provided at the intersection of the dividing lines of the insulating substrate are divided by the dividing line. It consists of a set of electrodes, and electrical bridging means for connecting predetermined parts between these electrodes.

(E) Function In the chip device of the present invention, the conductor pattern formed on the inner wall of the through hole is exposed on the side surface of the chip device when the insulating substrate is cut and divided along the dividing line to become a single chip device. Therefore, soldering to a conductor pattern on a circuit board can be easily performed.

In addition, since the conductor pattern is formed on the periphery and inner wall of the through hole drilled in the insulating substrate at the same time, there is no need to form electrodes for each chip element as in the past, and This makes it possible to form electrodes all at once.

(f) Embodiment An embodiment of this invention is shown in FIGS. 1, 2, and 3 (al.
This will be explained below based on FIG. 3(b).

In this embodiment, the present invention is applied to a chip fuse. FIG. 1 shows an external perspective view of this chip fuse 1. As shown in FIG. 2 is an insulating and fireproof chip substrate made of ceramic or the like.

At the four corners of this chip substrate 2, cylindrical recesses 3a, 3b, and 3C13d divided into quarters are provided. Electrodes 4a, 4b, 4c, and 4d made of conductive patterns are formed on the inner surface of each of the recesses 3a, 3b, and 3C13d. Each of the electrodes 4a, 4b, 4c, and 4d also covers the upper edges of the recesses 3a, 3b, and 3C13d on the surface of the chip substrate, and serves as bonding electrodes 5a'-5b, 5c, and 5d to which wires to be described later are bonded. There is.

A pair of conductor patterns 5a and 6b are formed on the surface of the chip substrate 2 so as to be in contact with the side edges of the surface of the chip substrate 2. Between the bonding electrode 5a and the conductor pattern 6a, between the bonding electrode 5b and the conductor pattern 5a, between the bonding electrode 5C and the conductor pattern 6b, and between the bonding electrode 5d and the conductor pattern 6b are wires 7 such as gold wires that melt when an overcurrent flows. ..., wire bonding is performed by 7. Note that the bonding electrodes 5a and 5b
It is also possible to bond 5C and 5d with straight wires, but most of the parts where wires 7, . . . , 7 melt due to overcurrent are wires 7, .
Bonding points 7a to bonding electrodes 5a, 5b, 5c, 5d or conductor patterns 6a, 6b of No. 7,...
. . , 7a, the circuit protection function of the chip fuse 1 is enhanced by increasing the number of bonding points by configuring it as described above.

Further, the surface of the chip substrate 2 is coated with a transparent silicone resin N8 having elasticity, and the bonding electrodes 5a,
5b, 5c, 5d, conductor patterns 6a, 6b, and wires 7, . . . , 7 are protected.

The reason why the silicone resin layer 8 has elasticity is that the wire 7,
......, when excessive current flows through wire 7,
This is to prevent the silicone resin N8 from being damaged due to rapid thermal expansion caused by the heat generated by the parts 7. In addition, the silicon resin JW8 is transparent because the wire 7,
This is to make it easier to confirm whether or not 7 has fused.

For reference, an example of the size of this chip fuse 1 is that the chip board 2 is 1.6+wa+(width) X3.2
It has a size of 111 m (length) xO, 6 mm (rg, length), and the layer thickness at the center of the silicone resin Tr18 is approximately 1
．． It is 5mm.

Next, how to use this chip fuse 1 will be explained below based on FIG. 2.

FIG. 2 shows a side view of the chip fuse 1 mounted on the circuit board 21. 22a and 22b are conductive patterns formed on the circuit board 21, respectively.

The chip fuse 1 is placed on the circuit board 21, and the electrodes 4a and 4b (not shown, but also the electrode 4C14d as needed) of the chip fuse 1 are soldered 23a to the conductor patterns 22a and 22b on the circuit board 21, respectively. , 23b, the electrodes 4a, 4b (4C14d) and the conductive patterns 22a, 22b are electrically connected, and the chip fuse 1 is fixed on the circuit board 21.

Note that the chip fuse 1 of this embodiment has electrodes 4a and 4b.
Two sets of fuses are provided between the two circuits and between the electrodes 4C and 14d, but these two sets of fuses can be used individually as protection fuses for two circuits, or connected in series (
For example, short-circuiting electrodes 4b and 40) and using them as one fuse, or using only one fuse, etc.
The degree of freedom in using this chip fuse 1 is great.

Next, the manufacturing process of the chip fuse 1 according to this embodiment will be explained below with reference to FIGS. 3(a) and 3(b).

FIG. 3(a) is a perspective view of an insulating substrate 12 having fire resistance such as ceramic. Vertical division lines V for dividing each chip substrate 2, ..., 2 of the insulating substrate 12,
. . . , ■ and the horizontal dividing line h, .
..., 13 are drilled and arranged in a grid pattern. Note that the through holes 13, . . . , 13 do not necessarily have to be circular.

In the next step, as shown in FIG. 3(b), the surroundings of the through holes 13, . . . , 13 on the surface of the insulating substrate 12 and the horizontal dividing lines h, . Conductor patterns 15, . . . , 15 and 16, .
..., 16 are formed. At this time, the through hole 13,
・・・・・・Conductor pattern 14 is also applied to the inner wall of 13 at the same time.
, . . . , 14 are formed.

After wire bonding is performed on the insulating substrate 12 on which the electrodes are formed, a laser beam or the like is applied along the vertical dividing lines V, ..., ■ and the horizontal dividing lines h, ..., h. The chip substrate 2 is then cut and divided into the chip substrate 2 shown in FIG. 1 described above.

At this time, the conductor patterns 14 and 15 are divided into four parts by the vertical dividing line V and the horizontal dividing line, and each conductor pattern 14 and 15 is divided into four by the vertical dividing line V and the horizontal dividing line.
, 4b, 4c, 4d, bonding electrodes 5a, 5b, 5
It becomes C15d. Further, the conductor pattern 16 is also divided into two parts by a horizontal dividing line to form conductor patterns 5a and 5b.

A silicone resin liquid is dropped (potted) onto the surface of the cut and divided chip substrate 2, and as this silicone resin liquid solidifies, a silicone resin layer 8 is formed, and the chip fuse 1 is completed.

Note that the number, shape, and arrangement of the conductor patterns formed on the chip substrate 2 and the wire bonding specifications are not limited to those in the above embodiments, and can be changed in design as appropriate. It has a high degree of freedom in that it is easy to obtain specifications that meet the needs of customers.

(G) Effects of the Invention The chip-nobu element of the present invention includes a chip substrate obtained by cutting and dividing an insulating substrate into predetermined sections along dividing lines, and a through-hole surrounding the through-hole provided at the intersection of the dividing lines of the insulating substrate. The conductive pattern formed on the inner wall is divided by the dividing line and consists of a set of electrodes, and electrical bridging means connecting predetermined ones of these electrodes, so that the conductive pattern is formed on the insulating substrate all at once. After forming a conductor pattern, the insulating substrate can be cut and divided along the dividing lines to obtain individual chip elements, which has the advantage of improving productivity and making it easier to attach to the circuit board. This has the advantage of being easy to install.

[Brief explanation of drawings]

FIG. 1 is an external perspective view of a chip fuse according to an embodiment of the present invention, FIG. 2 is a side view of the chip fuse mounted on a circuit board, and FIG. b
) is a diagram explaining the manufacturing process of the same chip fuse. 2: Chip substrate, 4a, 4b, 4C, 4d: Electrode, 7...7: Wire, 12: Insulating substrate, 13.
...13: Through hole, 14...14.15...15:
' = 7J body hatan. Patent applicant Tateishi Electric Co., Ltd. Agent
Patent Attorney Shigeru Nakamura Figure 1 Figure 5182 Figure % 3 (b) G

Claims (3)

[Claims] (1) A chip substrate obtained by cutting and dividing an insulating substrate into predetermined sections along dividing lines, and a conductive pattern formed around and on the inner wall of a through hole provided at the intersection of the dividing lines of the insulating substrate into the sections. A chip element consisting of a set of electrodes divided by lines and electrical bridging means connecting predetermined ones of these electrodes. (2) The chip device according to claim 1, wherein the chip substrate has fire resistance, and the electrical bridging means is a wire that melts when an overcurrent is applied. (3) The chip element according to claim 2, wherein the wires are a plurality of wires connected through at least one conductor pattern formed simultaneously with the formation of the conductor pattern of the one set of electrodes.