JPS62172592A - Substrate voltage generating circuit device - Google Patents

Abstract

PURPOSE:To obtain the titled device suitable for high circuit integration by forming a coupling capacitance by depletion MOS capacitance and connecting a gate electrode to a charge pump circuit side and a counter electrode to an oscillator output side to reduce the injection of a small number of carriers. CONSTITUTION:The coupling capacitance 2 is formed by depletion MOS capacitance, the gate electrode is connected to a node N1 of a charge pump circuit and the counter electrode (diffusion region) is connected to an output phi signal of an oscillator. The capacitance 2 always has the capacitance between electrodes to apply normal charge pump operation, the potential of the diffusion region and the channel region under the gate is brought to the same level as that of the signal phi and does not reach a negative potential. The diffusion region of the node N1 being the negative potential results from the source-drain region only of transistors 4, 5 and the area of the junction receiving a forward bias is reduced. Thus, the injection of a small number of carriers is reduced and the device suitable for high integrated circuit is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a substrate voltage generation circuit device incorporated in a dynamic integrated circuit memory device.

IEEE J, 5solid-3tatecircu
its, vot, aa-15°P, 672. Au
g, 1980. ) is a circuit diagram showing the conventional substrate voltage generation circuit device shown in FIG.
OS transistor, φ oscillation signal, board snow pressure on VBB,
N1 indicates a node number. I have now enclosed it here with a dashed line (lO
) is called a charge pump circuit.

Next, the charge pump operation shown in FIG. 2 will be explained using the waveforms shown in FIG.

When the power supply voltage vcc is supplied, the '0 oscillator 11+ generates the signal φ. When the signal φ becomes high level, the capacitance (21
Due to the combination of FN1 and FN1, the level will become bright, or the transistor (6) will be turned on.

It rises only to VT (1" voltage of the transistor).Next, when the signal φ becomes low level, also due to capacitive coupling, N1 tries to go low level, but the transistor (41 is ON). state, the electrically floating substrate potential VBB becomes a negative voltage (electrons of Nl are transferred to the substrate), and the node N1
The level is momentarily low (but quickly recovers to KVBB-V7).

The degree of this instantaneous level drop /f is the transistor (4
) and the size of the capacitance (2), but in highly integrated semiconductor devices, there is always a level drop because there is a limit to the size of the transistor (41).

Now, the extent to which the substrate potential 1/BB becomes negative snow pressure in one cycle of the φ signal is determined by the stray capacitance (3) of the substrate and the coupling capacitance (2).
It is determined by Normally, the floating capacitance t (31 times longer than the coupling capacitance t(2) is 100 times longer, so the above-mentioned cycle is repeated as shown in Figure 3, and the substrate potential gradually becomes a negative potential. Then, the substrate potential becomes -(Vcc-2v) for a predetermined time.
T ”) saturates −f” le.

The above describes the principle of a charge pump in which a semiconductor device can be used.In a dynamic memory device where vCC is a single power supply, the purpose of the charge pump is to prevent electron injection by a negative node due to negative input or circuit operation. Tamehiro (I'm not using it.

Conventionally, the coupling capacitance (2) has been composed of a wiring material (for example, At, polysilicon) constituting the semiconductor circuit device rTItf.

However, in recent years, due to the thinning or advancement of the gate layer and the increase in the MO8 visual capacity, it has become possible to obtain a film with a high S concentration.

Figure @4 shows a typical conventional layout of a charge pump circuit. The symbol Ji + in the figure indicates the same thing as in Figure 2.

A coupling capacitance t (21 MO9 capacitance is sufficient), a signal φ is connected to the gate electrode, and a node N1 is connected to the opposing layer # (diffusion region JFc).

Due to the above reasons, the signal φ is always at a high potential with respect to N1, so a channel is generated under the gate and always functions as a capacitor, so that normal charge pumping cannot be performed.

[Problem that the invention seeks to solve]

Now, in a highly integrated dynamic memory device, Vi%As shown in the above-mentioned references, in a high VCC state, the substrate voltage increases to the expected value due to the common current flowing due to hot electrons generated in the internal circuit. In this case, the charge pump circuit always performs a charge pump operation. At this time, the potential of node N1 is instantaneously higher than the substrate potential by 0.6 V or more. As a result, minority carriers are injected from node N1 into the substrate. depends on the magnitude of the forward bias and the length of the junction in no-FN1.In the conventional configuration, the capacitance (21 diffusion chains and the channel head under the gate) As a result, the number of minority carriers injected becomes too large, leading to damage that destroys the storage information of the memory device.

Does this release BJ4 have problems like the upper game? This was done to eliminate fN, and the purpose is to obtain a substrate voltage generation circuit that can reduce the injection of minority carriers from the charge pump circuit even in a high vCC state and is optimal for highly integrated dynamic memory devices.

[Means for solving problems]

The substrate voltage generation circuit according to the present invention includes a coupling capacitor (21) composed of a depletion MO8 capacitor, whose gate 1!l
The output φ signal of the oscillator is connected to the node N1 of the iK charge pump circuit to two opposing electrodes (diffusion@region) to reduce the serum of the junction KM to which a forward bias is applied.

[Function] Since the substrate voltage generating circuit according to the present invention has a junction to which a forward bias is applied in the coupling capacitance portion, it can be used in a high-performance dynamic memory device and the injection of minority carriers can be reduced.

[Example of Implementation of the Invention] A layout diagram of an embodiment of the invention is shown in FIG. 1 below. In the figure, the same reference numerals as in FIG. 2 of the conventional example indicate the same parts.

A coupling capacitor t (consisting of 21 depletion MO8 capacitors, its gate) [no to the pole] N1 is connected, and a signal φ is connected to the counter electrode (diffusion region).

The operation shown in FIG. 1 will be explained below.

Since it is a depletion type capacitor (21 capacitors), there is always a capacitance between the electrical connections, and normal charge pump operation cannot be performed like the conventional circuit.

Further, since the potentials of the diffusion region of capacitor t(2) and the channel region under the gate are at the same level as the signal φ, there is no negative potential. Since the diffusion region of NOI''N1, which has a negative potential, is only the source/drain width region of the transistor (41, fil), the area of the junction that becomes forward biased is significantly reduced, and minority carriers are injected. The interlude by the author has not improved significantly.

In the above practical example, the capacitor (2) is a simple depression type MO3O3 capacitor, but the effect does not change even if it is made into a 1ff type in the same process as the depression process under the cell plate in the memory cell of the dynamic memory device.

〔Effect of the invention〕

As described above, according to the present invention, the coupling capacitance of the charge pump circuit is formed by the depletion MO3 capacitor 11-, and the capacitance has a structure in which there is no junction to which a bias in the direction is applied. Even when used in a device, it is possible to obtain a substrate voltage generation circuit in which injection of minority carriers is reduced and high integration is possible.

[Brief explanation of drawings]

Figure 1 is a layout diagram of a charge pump circuit in one practical example of this invention, Figure '4IJ2 is a circuit diagram showing a conventional substrate voltage generation circuit, and Figure 3 is a normal pressure diagram of each part to implement the entire ILII operating principle. The waveform diagram and FIG. 4 are layout diagrams of a conventional charge pump circuit. In the figure, % (11 oscillators, (2) is MO3 capacity, +
101 phase charge pump circuit, φ oscillator output. In the figures, the same reference numerals do not indicate the same or equivalent parts.

Claims (2)

[Claims] (1) In a device consisting of an oscillator and a charge pump circuit that generates a substrate voltage of a dynamic semiconductor integrated circuit memory device from the output of this oscillator, the coupling capacitance that couples the output of the upper oscillator to the charge pump circuit is a depletion type. What is claimed is: 1. A substrate voltage generating circuit device, characterized in that the gate electrode is connected to the charge pump circuit side, and the counter electrode made of a diffused semiconductor region is connected to the output side of the upper air oscillator. (2) The channel region of the depression type MOS capacitor is a region formed in the same depression process as the region under the plate in the memory cell of the dynamic semiconductor integrated circuit memory device. The substrate voltage generation circuit device according to item 1.