JPS62169520A - Lsi - Google Patents

Abstract

PURPOSE:To obtain a Bi-CMOSLSI which can perform the interface with the outside of an LSI at a high speed by providing an input/output circuit which works at the level of a CMOS or the Bi-CMOS to the LSI. CONSTITUTION:The input/output circuits 11-38 are provided in an LSI chip and at least one of these circuits is equal to a Bi-CMOS input/output circuit of this invention. This input/output circuit can attain a high-speed operation by driving the bipolar transistors TR805 and 806 of an output stage by MOS TRQ801 and 802, extracting the base charges of bipolar TR805 and TR806 of the output stage by MOS TR805 and 806 and then cutting off quickly those bipolar transistors. Then the power consumption is extremely reduced because the CMOS transistors of the input stage and the bipolar transistors of the output stage have complementary actions. In addition, the load depending properties of the delay time show the satisfactory characteristics as shown in a figure 603.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to an LSI suitable for high-speed interfacing between LSIs.

[Conventional technology]

Conventionally, an example in which an input/output buffer circuit serving as an interface between the inside and outside of an LSI is configured with a Hi-BiCMOS circuit is disclosed in Japanese Patent Laid-Open No. 60-142618 (1985), Figure 10, or Nikkei Electronics ('85).

8.12. P, 196 Figure 11). Tokukai Showa 6
The circuit shown in Figure 10 of Publication No. 0-142618 is
As shown in the figure. This input circuit has full TTL compatibility. The signal input from the input terminal 219 is converted to CMOS level by the MoS transistors 202 and 206.
Furthermore, after waveform shaping is performed by MoS transistors 203 and 207, the output stage is driven. Therefore, the time required for level conversion and waveform shaping increases the delay time. Also, Nikkei Electronics ('85.8.12.p.

196 Figure 11) is shown in Figures 3 and 4. The input and output circuits shown in Figures 3 and 4 respectively are fully TTL compatible. The input circuit shown uses lateral PNP transistors at the input. Input low level current I for TTL input!
This is to reduce t by using the current amplification factor of the PNP transistor.

The level of the emitter of the PNP transistor is adjusted to the CM of the subsequent stage.
It is transmitted to the OS inverter and NMO8303, and the NPN transistors 304 and 305 connected to the totem pole in the output stage
is driving. Further, the output circuit shown in FIG. 4 outputs a low level sink current when the input is at the "O" level, that is, when the output is at the "0" level. In order to secure the current, the NMO 5401 continues to supply current to the base of the NPN transistor 404 in the lower stage. When the NPN transistor 404 is turned off, the diode 405 transfers its base charge to the NMO 5402 of the CMOS inverter.
It is provided for rapid withdrawal through the thread.

As described above, the input circuit and output circuit shown in FIGS. 3 and 4 each have a circuit configuration compatible with TTL, which causes an increase in delay time.

That is, in FIG. 3, the PNP transistor and the subsequent 0MO8 configuration for level setting increase the delay time,
In FIG. 4, the CMOS stage for level conversion increases the delay time.

[Problem that the invention seeks to solve]

FIG. 5 of Japanese Unexamined Patent Publication No. 59-175748 shows the relationship between the load and delay time of the 0M08 circuit and the bipolar circuit. This relationship is shown in Figure 5. In Figure 5, 501 is the delay time characteristic of the 0M05 circuit, and 502 is the bipolar 50M
05 circuit delay time characteristics.

As is clear from the figure, the 0M08 circuit has a large load dependence, and the difference in delay time between low and high loads is significant.
This is extremely inconvenient for high-speed operation as an LSI and reliable circuit operation. However, as shown in the diagram, the miniaturized 0MO8 can operate at a high speed equivalent to or higher than that of a bipolar CMOS circuit in a low load region where the load is less than C1. On the other hand, the delay time of the bipolar 50M08 circuit has extremely low load dependence and the difference in delay time between low load and high load is small, so it is extremely convenient for high-speed operation as an LSI and reliable circuit operation.

In this way, the delay time characteristics of the internal basic circuits within the chip demonstrate the superiority of the B i-0M08 circuit over the 0M08 circuit. In this case, c1 is on the order of sub-picofarads, and the Bi-0M08 circuit is faster under normal loads.

Regarding the load dependence of delay time as described above, Bi-
The superiority of the 0M08 circuit over the 0M08 circuit can be applied not only to basic circuits but also to human output buffer circuits that serve as interfaces between LSIS phases. FIG. 6 shows the dependence of the delay time of the output circuit on the load capacitance. In the figure, 601 shows the delay time characteristics of the 0M08 circuit, and 602 shows the delay time characteristics of the conventional Bi-CMO5 output circuit with full TTL compatibility. CMO as well as basic circuit
The delay time characteristics of the 8 output circuit and the delay time characteristics of the Bi-CMO5 output circuit intersect at load C2, and Bi-0
This shows the superiority of the load dependence of the M05 circuit. In this case, C2 is on the order of several PF to about 20 PF, and
The B i -0M05 circuit is faster under normal loads. However, even higher speeds are required. This will be explained next. FIG. 7 shows the state of access between LSI chips.

The LSI chip 701 is a high-speed LSI whose internal circuit is composed of Bi-0M08 circuits.
At least one of the SI chips has an internal circuit of Bi-0
This is a high-speed LSI composed of M05 circuits. An LSI whose internal circuit is constructed from a B1-CMOS circuit operates at a very high speed. Therefore, the interface between LSIs having a Bi-CMO3 circuit configuration is required to have high speed corresponding to the operation of the B1-CMOS internal circuit. In other words, in addition to speeding up the internal operation of the LSI chip,
By increasing the speed of the interface between I, the speed of the entire system can be increased. For example, 10
M I P S (Million Instruction)
When designing a microcomputer with high-speed performance of ons per 5 seconds, it is necessary to set the execution time including the access time between LSI chips to 50 ns.

On the other hand, the access time of the TTL compatible Bi-CM OS input/output circuit as shown in FIG. 6 602 is about 20 ns at maximum. If the delay time of the input/output circuit section is around 20 ns for the required performance of 50 ns, it is difficult to achieve the required performance, and the high speed inside the Bi-0MO3 configured LSI is canceled out.

As mentioned above, the conventional Bi-CMOS input/output circuit has T
It is TL or ECL compatible. Therefore, Bi-CM
In order to interface O3LSI and external LSI at TTL level or ECL level, in the input circuit, B1-CMO is connected from TTL or ECL level.
The circuit part required for level conversion to S level increases the delay time, and the output circuit requires B1-CMOS.
The circuitry required for level conversion from a level to a TTL or ECL level increases the delay time. Therefore, the Bi CMO3LSI has a problem in that the delay time required for the interface between the LSIs is larger than that for the internal circuit.

An object of the present invention is to provide an i-CMOS LSI that can interface with the outside of the LSI at high speed.

[Means for solving problems]

The above object is achieved by configuring an input/output circuit that operates at the 0MO3 or Bi-CM OS level without making the input/output circuit compatible with TTL or ECL, and providing this in an LSI.

That is, the conventional TTL compatible B1-CMOS input/output circuit shown in FIGS. 2, 3, and 4.

The delay time increases due to the circuit configuration for compatibility with TTL. In Figure 2, the TTL level is CM
MOS transistor 202 for conversion to OS level,
The signal is transmitted to the output stage through a level conversion stage constituted by 206 and a waveform shaping stage that shapes the level-converted signal to a perfect CMOS level. Therefore, the delay time obviously increases due to level conversion and waveform shaping. In addition, the input/output circuits shown in FIGS. 3 and 4 are designed to have TTL compatibility as described in detail above, but this causes an increase in delay time.

Without TTL compatibility, the circuit is greatly simplified. In other words, NPN with totem pole connection in the output stage
The structure includes only a transistor, a MOS transistor for driving the transistor, and an extraction circuit for extracting the base charge of the bipolar transistor. The load dependence of the delay time in the case of such a circuit configuration is shown in FIG.
It can be seen that the delay time characteristic 603 of the output circuit is significantly faster. The same applies to the input circuit.

Furthermore, the reason why it is possible to increase the speed by simplifying the circuit without TTL compatibility will be explained with reference to FIG.

As mentioned above, the LSI 701 is composed of Bi-0 MO8. Other LSIs, for example LSI702, are Bi-
LSI configured by 0MO5, 703 is LS1 configured by TTL, 704 is LSI configured by ECL, 705 is LS configured by 0MO8
Let it be I. Since the 701 LSI has at least one high-speed Bi-CMO8 input/output circuit according to the present invention, B
It is possible to speed up the interface with i-0MO5LSI702. Conventionally, LSI701 had only TTL compatible input/output circuit or ECL compatible input/output circuit, so B i between LSI701 and LSI702
- The interface between CMO3LSI is also TTL or E
This has no choice but to be performed at the CL level, and therefore the delay time at the interface section is large. However, according to the present invention, L
SI701 contains at least one Bi-CM according to the invention
Since it has an O8 input/output circuit, LSI701 and LS
I702 can be accessed using the B1-CMOS interface, making it possible to speed up the system. That is, by simplifying the circuit configuration by eliminating the TTL or ECL compatibility of the conventional TTL or ECL compatible input/output circuit, and by using an LSI configuration having at least one input/output circuit according to the present invention, Bi -CMO8L
By making it possible to interface between SIs at the B1-CMOS level.

Speeding up the interface between LSIs is realized.

[Operation] The Hi-BiCMO8 input/output circuit according to the present invention is composed only of a totem-pole connected NPN transistor in the output stage, a MoS transistor for driving the transistor, and an extraction circuit for extracting the base charge of the bipolar transistor. There is.

This simplification of the circuit eliminates the increase in delay time caused by the complexity of level conversion, waveform shaping, and other circuits in conventional TTL compatible input/output circuits, making it possible to increase speed. Ta. Its characteristics are as described in the sixth
As shown in the figure. Compared to the TTL compatible Bi-CMO8 delay time characteristics of 602, the Hi-B according to the present invention of 603
The iCMO3 delay time characteristics are faster in the entire load range. It can be seen from FIG. 6 that the Bi-CMO8 input/output circuit according to the present invention is capable of achieving higher speeds that could not be achieved with the prior art in the load range where output circuits are often used.

The effectiveness of the present invention is also demonstrated in the system application example described above. That is, in order to realize a 10MIPS high-performance microcomputer, the execution time including access between LSIs needs to be 50ns.

The access time for the conventional TTL compatible Bi-CMO8 input/output circuit is 20 ns, and the even faster ECL compatible Bi-C
Even the MO5 input/output circuit requires about 16 ns, making it difficult to achieve 50 ns. On the other hand, the Bi-CMO of the present invention
The access time of the 8 input/output circuit is approximately 8 ns, and it is possible to increase the speed by more than twice, and there is a prospect of achieving 50 ns. This can be realized by having at least one of the following.

〔Example〕

FIG. 1 shows an LSI chip. There are 11 in the chip
As shown in 38, a plurality of input/output circuits are provided. At least one of these input/output circuits is a Bi-CMO8 input/output circuit according to the present invention as described below.

40 has an internal circuit. In this way, by providing at least one Bi-CMO3 input/output circuit according to the present invention in a chip, an inter-LSI interface i is provided.
-0MO8 can be used to speed up the system.

FIG. 8 shows a first embodiment of the input/output circuit according to the present invention, which is disclosed as an internal basic circuit in European Patent Application Publication No. 0145004. A first NPN bipolar transistor 805 whose collector is connected to the power supply terminal 809 and whose emitter is connected to the output terminal 808, whose collector is connected to the output terminal 808 and whose emitter is connected to the ground terminal 81.
0, a P-type MOS transistor 801 whose gate is connected to the input terminal 807, and whose source and drain are connected to the collector and base of the first NPN transistor 805, respectively; an N-type MO8)-transistor 802 whose gate is connected to the input terminal 807, and whose drain and source are connected to the collector and base of the second NPN transistor 806, respectively; An N-type MOS transistor 803 is connected to the base of the first NPN transistor 805 and the ground terminal 810, its gate is connected to the output terminal 808, and its drain and source are connected to the base and ground terminal 810 of the second NPN transistor 806, respectively. N type M connected to
It is composed of an oS transistor 804.

The feature of this circuit is that the bipolar transistor in the output stage is driven by MOS transistors 801 and 802.
The MOS transistors 803 and 804 draw out the base charge of the bipolar transistors in the output stage, and cut off the bipolar transistors quickly, thereby increasing the speed. Furthermore, since the CMO3 configuration in the input stage and the bipolar transistor in the output stage perform complementary operations, power consumption is extremely low. The load dependence of the delay time of this circuit exhibits good characteristics as shown at 603 in FIG.

FIG. 9 shows a second embodiment of the input/output circuit according to the present invention, which is disclosed as an internal basic circuit in Japanese Patent Application Laid-Open No. 59-41034. Collector is power terminal 909
, a first NP whose emitter is connected to the output terminal 908
a second NPN bipolar transistor 904 whose collector is connected to the output terminal 908 and whose emitter is connected to the ground terminal 910; and a first NPN bipolar transistor whose gate is connected to the input terminal 907 and whose source and drain are connected to the ground terminal 910, respectively. P-type MOS transistor 901 connected to the collector and base of 903
and an N-type MOS transistor 902 whose gate is connected to the input terminal 907 and whose drain and source are connected to the collector and base of the second NPN transistor 904, respectively, and the terminals at both ends are the first NPN bipolar transistor. The resistor connected to the base of 903 and the output terminal 908, and the terminals at both ends connected to the second N
It is composed of a resistor connected to the base of the PN bipolar transistor 904 and a ground terminal 910.

The feature of this circuit is that the bipolar transistor in the output stage is driven by MOS transistors 901 and 902.
The point is that the base charge of the bipolar transistor in the output stage is extracted by the resistors 05 and 906, and the bipolar transistor is cut off quickly, thereby increasing the speed.

Compared to the input/output circuit shown in FIG. 8 above, the power consumption is slightly larger due to the through current, but the delay time shows the same load dependence as in FIG. 8.

FIG. 10 shows a third embodiment of the input/output circuit according to the present invention, which is disclosed as an internal basic circuit in Japanese Patent Application Laid-Open No. 60-27227. Collector is power terminal 10
8, the first N whose emitter is connected to the output terminal 107
A second NPN bipolar transistor 105 whose collector is connected to the output terminal 107 and whose emitter is connected to the ground terminal 109, whose gate is connected to the input terminal 106 and whose source and drain are connected to the first N P N bipolar transistor 104
A P-type MO5)-transistor 101 whose gate is connected to the collector and base of the transistor 101, whose gate is connected to the input terminal 106, and whose drain and source are connected to the base of the first NPN bipolar transistor and the base of the second NPN bipolar transistor, respectively. An N-type MOS transistor LO2 is connected to the NPN bipolar transistor, and has a gate connected to the base of the first NPN bipolar transistor, and a drain and source connected to the base of the second NPN bipolar transistor and the ground terminal 109, respectively.

It is constituted by a diode 110 whose cathode terminal is connected to the base of the first NPN bipolar transistor and whose anode terminal is connected to the output terminal 107.

The feature of this circuit is that the bipolar transistor in the output stage is driven by the MoS transistor 101 and the MOS transistor 102, and the base charge of the bipolar transistor in the output stage is extracted by the MoS transistors 102 and 103 to quickly cut off the bipolar transistor, thereby increasing the speed. It's in the point of measurement. This circuit also exhibits good delay time characteristics like the circuits shown in FIGS. 8 and 9 above.

FIG. 11 shows a fourth embodiment of the input/output circuit according to the present invention. A first Schottky clamp NPN bipolar transistor 111 whose collector is connected to the power supply terminal 809 and whose emitter is connected to the output terminal 808; and a second Schottky clamp whose collector is connected to the output terminal 808 and whose emitter is connected to the ground terminal 810. type NPN bipolar transistor 112, the gate of which is connected to the input terminal 807,
A P-type MOS transistor 80 whose source and drain are respectively connected to the collector and base of the first Schottky clamp type NPN bipolar transistor 111.
1, the gate is connected to the input terminal 807, and the drain and source are respectively connected to the second Schottky clamp type NPN.
An N-type MO8) transistor 802 is connected to the collector and base of the bipolar transistor 112, its gate is connected to the input terminal 807, and its drain and source are connected to the base and ground terminal 810 of the first Schottky clamp type NPN bipolar transistor 111, respectively. and an N-type MOS transistor 803 whose gate is connected to the output terminal 8.
08, the drain and source are respectively the second clamp type NPN bipolar transistor 112.
This is an input/output circuit composed of an N-type MOS transistor 804 connected to the base of the MOS transistor 804 and a ground terminal 810.

The feature of this circuit is that by clamping the NPN bipolar transistor in the output stage with a Schottky diode, the storage time of the bipolar transistor is eliminated and the speed is increased. Note that Fig. 11 shows an example of the same configuration circuit as the circuit shown in Fig. 8, but in addition to the single circuit, NPN bipolar The transistor can be replaced with a Schottky clamp type NPN bipolar transistor.

FIG. 12 shows a fifth example of the input/output circuit according to the present invention, which is a circuit having the circuit configuration shown in FIG. is configured by adding a first resistor 121 connected to the output terminal 808 and a second resistor 122 whose one end is connected to the output terminal 808 and the other end is connected to the ground terminal 810.

The feature of this circuit is that by adding a resistor in parallel to the bipolar transistor in the output stage, the amplitude of the output signal is reliably lowered and the speed is increased.

In the case of the capacitive loads shown in FIGS. 8 to 11, if the output level changes due to leakage current, noise, etc., it is maintained at the same level. On the other hand, in the circuit shown in Figure 12, a DC bus is formed between the power supply terminal and the ground terminal by the resistor connected to the output terminal, so the output high level is V
cc -V BH, output low level is V EE + V
Always clamped to BH. Here, Vcc is a power supply potential, VEE is a ground potential, and VBE is a base-emitter voltage of an NPN bipolar transistor. This idea can also be applied to the circuit shown in FIG.

FIG. 13 shows the sixth example of the input/output circuit according to the present invention, and is an example of an input/output circuit in which the amplitude of the output signal is reduced by Darlington connection of bipolar transistors. A first NPN transistor 139 whose collector is connected to the power supply terminal 143 and whose emitter is connected to the output terminal 142; whose collector is connected to the output terminal 142 and whose emitter is connected to the ground terminal 1
a second NPN connected to 44)--transistor 140.

The collector is connected to the power supply terminal 143, and the emitter is connected to the first N
a third NPN connected to the base of the PN transistor
A transistor 137, the collector of which is connected to the output terminal 142,
a fourth NPN transistor 138 whose emitter is connected to the base of the second NPN transistor 140;
The gate is connected to the input terminal 141, and the source and drain are connected to the power supply terminal 143 and the third NPN transistor 1, respectively.
P-type MoS transistor 1 connected to the base of 37
31', the gate is connected to the input terminal 141, and the drain and source are connected to the output terminal 142 and the fourth NPN, respectively.
An N-type MoS transistor 132 connected to the base of the transistor, a gate connected to the input terminal 141, and a drain and source connected to the third NPN transistor 13, respectively.
N-type MoS connected to the base of 7 and the ground terminal 144
A transistor 133, an N-type M whose gate is connected to the output terminal 142, and whose drain and source are connected to the base and ground terminal 144 of the fourth NPN transistor, respectively.
An OS transistor 134, an N-type MoS transistor 135 whose gate is connected to the input terminal 141, whose drain and source are respectively connected to the base of the first NPN transistor 139 and the ground terminal 144, and whose gate is connected to the output terminal 1
42, the drain and source are each connected to the second NP.
It is constituted by an N-type MOS transistor 136 connected to the base of the N transistor and the ground terminal 144.

The feature of this circuit is that the bipolar transistors in the output stage are connected to Darlington, thereby reducing the amplitude of the output signal and increasing the speed. In other words, the high level of the output signal is Vcc-2VBE! The low level of the output signal is clamped to VEe+2Vag.

FIG. 14 shows an example of the input/output circuit according to the present invention having a 3-state buffer configuration.
When the 0-wire circuit disclosed in Japanese Patent No. 67 is used as a normal buffer, it exhibits excellent delay time characteristics similar to the above-mentioned input/output circuit. In the case of high impedance state, the base and emitter of the bipolar transistor are Mo8
Since the bipolar transistor is short-circuited and the bipolar transistor is turned off, a high impedance state equivalent to a three-state circuit composed of MOS transistors can be realized.

Fig. 1S shows a cross section of the Hi-BiCMO8LSI, 50 is an N0 buried layer, 51 is an N well region, 52 is a P- type semiconductor substrate, 53 is a P10 buried layer, 54 is a P well region, 55 is an isolation oxide film, 56 is a P-type base layer, 57 is an N-type emitter layer, 58 is an N-type source and drain region, 59 is a gate oxide film, 60 is a gate electrode, 61 is a P-type source and drain In each region, an NPN transistor is formed in a region 62, an N-type MOS transistor is formed in a region 63, and a P-type MOS transistor is formed in a region 64. The circuit example described in this patent can be made using Hl BiCMO5LSI having the cross-sectional structure shown in this figure. Further, with this device, it is of course possible to configure an interface circuit having TTL compatibility, ECL compatibility, etc.

FIG. 7 is an example of a system application of the present invention. LSI70
1 is B1-CMOS LS1.702 is B1-CMOS LSI outside 701, 703 is TTL L
S1.704 is ECL LSI, 705 is CMo8
The LSIs 701 and 702 each have at least one B1-CMOS input/output circuit.

Therefore, between LSIs 701 and 702, the Bi
- CMOS input/output circuit allows high-speed interface. In addition, if the LSI701 also has TTL and ECL compatible input/output circuits, the LSI701 will have 702, 70
Needless to say, it is possible to interface with all LSIs of 3°704.705. In this manner, by providing an LSI with at least one B i -CMOS input/output circuit according to the present invention, it is possible to use the LSI 701 and 702 in critical parts of the system, for example, to increase the speed of the system.

FIG. 16 shows a second system application example of the present invention.

Several LSIs 161 to 164 are connected to a data bus 169. In such a case.

For example, if it is desired to send data from LS 1161 to LS I 164, the other LSs 1162 to 163 act as a load. Therefore, in the case of a system like this example, it is necessary to drive a large load at high speed, and the B1-CMOS
The interface becomes valid. Therefore, the Bi-C according to the present invention is used in the LSI constituting the system as shown in this example.
Providing a MOS input/output circuit is effective in speeding up the system.

171, 172, and 173 in FIG. 17 respectively indicate wafers on which circuits are formed by wafer scale integration.In the future, circuits will be integrated at the wafer level by wafer scale integration instead of the current chip level LSI. There is a possibility that In that case, the entire system will consist of several wafers, and an interface between the wafers will be required.

The interface between the wafers is the Bi-CMO of the present invention.
This can be done using an S input/output circuit.

Further, although the input circuit described above has been described using an inverter circuit for six or more circuits in which a normal protection circuit may be provided, it is clear that a durable NANAD or multi-input NOR circuit can be configured. In other words, it can also be used as an input/output interface circuit of logic materials.

〔Effect of the invention〕

According to the present invention, since the circuit configuration of the input/output circuit can be simplified, there is an effect of increasing the speed, and by using an LSI equipped with this, the speed of the system can be increased.

It is not a TTL or ECL compatible Hi-Bi CMO3 input/output circuit like conventional input/output circuits, but a Hi-Bi CMO3 input/output circuit.
Since it is an input/output circuit that interfaces between CMO8, a level conversion function is not required.

The circuit has been simplified. This simplification improved the speed performance of the circuit. The situation is shown in FIG.

In the figure, 601 is the delay time characteristic of 0MO8 (Bi-0MO5
602 is the delay time characteristic of the conventional Bi-0MO5, and 603 is the delay time characteristic of the Bi-0MO5 according to the present invention.
The speed has been increased to 03.

Furthermore, by using an LSI equipped with the input/output circuit according to the present invention, a high-speed system is realized.For example, when creating a high-performance IOMIPS microcontroller, the execution time including access between LSIs must be 50 ns. .

Conventional TTL compatible Bi-CMOS input/output circuit has an access time of 20 ns, and even faster ECL compatible Bi-CMOS input/output circuit has an access time of 20 ns.
-The B1-CMOS input/output circuit of the present invention has an access time of 8 ns, which is more than twice as fast as the -CMQS input. This speeds up the system and increases the IO
It becomes possible to design a high-performance MIPS microcontroller.

[Brief explanation of drawings]

FIG. 1 is a diagram of an LSI showing an embodiment of the present invention, FIG. 2 is a diagram of a conventional input circuit, FIG. 3 is a diagram of a conventional input circuit, FIG. 4 is a diagram of a conventional output circuit, and FIG. Figure 5 shows the delay time characteristics of the basic circuit, Figure 6 shows the delay time characteristics of the input/output circuit, Figure 7 shows the first system application example, and Figure 8 shows the delay time characteristics of the basic circuit.
The figure shows an input/output circuit that is a first embodiment of the invention, FIG. 9 shows an input/output circuit that is a second embodiment of the invention, and FIG. 10 shows an input/output circuit that shows a third embodiment of the invention. 11 is an input/output circuit according to a fourth embodiment of the present invention, FIG. 12 is an input/output circuit according to a fifth embodiment of the present invention, and FIG. 13 is a circuit according to a sixth embodiment of the present invention. An input/output circuit. FIG. 14 shows a three-state circuit according to the seventh embodiment of the present invention.
FIG. 15 is a cross-sectional view of the device structure, FIG. 16 is a diagram showing a second system application example, and FIG. 17 is a diagram showing a third system application example of the present invention. 11-38...Bi-CMOS input/output circuit, 40...
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Claims (1)

[Claims] 1. A first bipolar transistor whose collector is connected to a power supply terminal and whose emitter is connected to a first terminal; and a first bipolar transistor whose collector is connected to the first terminal and whose emitter is connected to a fixed potential terminal. a first MOS transistor having a gate connected to a second terminal, a source and a drain connected to a collector and a base of the first bipolar transistor, respectively, and a gate connected to the second terminal; Consisting only of a second MOS transistor whose drain and source are connected to the collector and base of the second bipolar transistor, respectively, and a charge extraction circuit connected to the bases of the first and second bipolar transistors. An LSI comprising at least one input circuit and one output circuit. 2. In claim 1, a first bipolar transistor is provided between the collector of the first bipolar transistor and the first terminal.
An LSI comprising at least one input circuit and an output circuit, each of which has a second resistor between the collector of the second bipolar transistor and a fixed terminal. 3. A first bipolar transistor whose collector is connected to the power supply terminal and whose emitter is connected to the first terminal; and a second bipolar transistor whose collector is connected to the power supply terminal and whose emitter is connected to the base of the first bipolar transistor. a third bipolar transistor whose collector is connected to the first terminal and whose emitter is connected to the fixed terminal; and a third bipolar transistor whose collector is connected to the first terminal and whose emitter is connected to the base of the third bipolar transistor. a first MOS transistor whose gate is connected to a second terminal, whose source and drain are respectively connected to the collector and base of the second bipolar transistor; and a second MOS transistor whose sources are respectively connected to the collector and base of the bipolar transistor shown in FIG. An LSI comprising at least one input circuit and one output circuit composed only of circuits. 4. Claims 1, 2, or 3 provide that the first, second, third, and fourth bipolar transistors include at least one input circuit and output circuit made of Schottky transistors. L characterized by having
S.I.