JPS6021626A - Output circuit - Google Patents

Abstract

PURPOSE:To prevent the operating speed due to a load capacitance from being lowered by adding a bipolar transistor (TR) having a large current driving capability to an output circuit comprising CMOS logical circuits so as to reduce the occupied area of the output circuit. CONSTITUTION:A drain of a P-channel MOS TRQ31 is connected to a base of a PNP bipolar TRQ33 and a drain of an N-channel MOS TRQ32 is connected to a base of a PNP bipolar TRQ34 respectively. When a low level input voltage is applied to an input terminal 31, a low level output voltage appears at an output 32. When a high level input is applied to the input terminal 31, a high level output voltage appears at the output 32. Since each collector current of the TRs Q33, Q34 charges/discharges the load capacitor with the capability being hFE times the current applied to the base when they are conducted, the response of the output is quickened accordingly.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an output circuit that combines a 51n MOS C (hereinafter abbreviated as CMO8) and a bipolar transistor.

In the output circuit of a CMO8 logic circuit, the CMO8
The current drive capability of the transistor is smaller than that of a bipolar transistor of equivalent size, resulting in a reduction in speed due to capacitive loading. To compensate for this, it is necessary to make the output transistor thicker (increase the W/L ratio), but this has the disadvantage of increasing the ratio of the output circuit to the entire circuit and reducing the degree of integration. Ta.

On the other hand, by adding a bipolar transistor with a large current drive capability to the CMO8 output circuit, an output circuit is known that reduces the reduction in operating speed due to load capacitance even if the area occupied by the output circuit is small. .

FIGS. 1 and 2 are examples of a CMO8/bipolar transistor hybrid output circuit having a high current drive capability by adding bipolar transistors.

In FIG. 1, bipolar transistors Qls and Q
Even if a large amount of capacitive load CL is added to the output terminal 12, the so-called push-pull circuit configured with 10 has a low signal propagation speed due to current draining by the bipolar transistor Q1sK and current sucking by the bipolar transistor Q+4. It is possible to suppress the decrease in

In FIG. 2, a so-called complementary push-pull circuit is constructed by using a PNP transistor Q24 as the transistor on the current intake side.
This is an example of improving the speed of current intake.

The circuit example described above is extremely useful as it shows a significant improvement in current driving ability and capacitive load driving ability over an output circuit made only of CMOS.゛However, due to the added bipolar transistor, its output is CMO
This is different from the 8 output circuit. Normally, in an output circuit with only a CMO8, the high 17-bell output voltage VOI (is approximately equal to the high-level power supply 3 and the low-level output voltage oL is approximately equal to the low-level power supply 4, respectively. In the example, the high 17-bell output voltage VOH is equal to the base-emitter forward voltage VB of the bipolar transistor QH+ Qts.
Only E is lower than the high-level power supply 3, and the low-level output voltage VOf is the bipolar transistor QI41 Q24.
The base-emitter direction voltage VBE of the lower side power supply 4
It gets really expensive.

In this way, the conventional CMO as shown in Figures 1 and 2
8/In the pieborate syndistor hybrid output circuit,
Although the current drive capability was improved, the output voltage did not satisfy the rating of 0MO8, so it was difficult to use it as a so-called external output circuit.

In general, compared to other logic circuits such as transistor-transistor logic (hereinafter abbreviated as TTL), 0MO8 has advantages such as low power consumption and large noise margin, as well as slow operation speed. It also has the disadvantage of low current drive capability, so it is difficult to operate digital devices at zero.
It is not configured only with MO8, but is often used in combination with TTL or other logic circuits. Therefore, recently, in order to facilitate the TTL-0MO8 interface, many products have been seen that allow the input voltage standard of 0MO8 to be set to match the TTL output, as TTL is often used in conjunction with 0MO8. Ta. Conversely, this means that the output of 0MO8 can be a TTL output, and the 0MO8-T has excellent current drive ability and capacitive load drive ability.
Facilitates interfacing of TL, 0MO8-0MO8.

An object of the present invention is to provide an output circuit that satisfies TTL output standards without impairing current drive capability and capacitive load drive capability by adding a polar transistor to the 0M08 circuit.

According to the present invention, there are provided a P-channel MO8) transistor whose source is connected to a high-potential power supply and whose gate is connected to an input terminal, and an N-channel MO transistor whose source is connected to a low-potential power supply and whose gate is connected to the input terminal. MO8) In the transistor, a first non-polar transistor whose base input is the do1/in of the P-channel transistor which is cut off when the transistor is turned on and turned on when the transistor is turned off; Channel MO8) Such a channel is cut off when the transistor is conductive and conductive when the transistor is cut off.
Channel MO8) It has a second bipolar transistor whose base input is the drain of the transistor, and the output of the second bipolar transistor is directly connected to the output of the first bipolar transistor No. 411, or An output circuit is obtained which is characterized in that four bipolar transistors are connected as a Darlington output, and the connected terminal is used as an output.

The present invention will be explained in detail below according to embodiments and with reference to the accompanying drawings.

FIG. 3 is a circuit connection diagram showing an embodiment of the present invention.

P channel MO8) transistor Q31, N channel MO
8) Both gates of transistor Qst are connected to input 31. The do1/in of Qss is connected to the base of the PNP type bipolar transistor Qss, the do1 twin of Qst is connected to the base of the NPN type bipolar transistor Q34, and the collector/input of Qss and the QB4
Both of the output terminals 1 and 2 are connected to the output terminal 34. Further, R, , R, are resistors, and R, & are inserted between the terminal 35 and the power supply 4, and RR is inserted between the terminal 36 and the power supply #3.

Here, if a low level input voltage is applied to the input terminal 31, the transistor Qs+ is conductive, so that the potential of the terminal 35 is approximately equal to that of the FfL source 3, and the transistor Qss is cut off. Transistor Q3 again! is cut off, so transistor QA4 is made conductive by resistor R2, and output 12 has a low 1 novel output voltage VoL=Vc
=Q3. (However, VCEQ, , is the transistor Q3
4 collector-emitter voltage) is generated.

When a high 17-bell input voltage is then applied to input terminal 31, transistor Q0 becomes conductive, so that the potential at terminal 36 becomes approximately equal to power supply 4, and transistor Q34 is cut off. Also, since the transistor Q3□ is cut off, the resistor R
1, the potential of the terminal 35 rises and falls, and the transistor (Q'
Conducts 13g. Therefore, output 32 has a high 17-pel output potential VOH-Vll-VCEQ33 (however, V
CEQ3s is the collector-emitter voltage of the transistor Qsa.

In the above description, transistors Qsa and Q34
The respective collector current, or drive current, when conductive has a capacity hFE times the current supplied to the base. This means that transistor Qss + Q! 4
By adding transistor Qss + Q
The power that st has! This means that the load capacitor MCL is charged or discharged with a capacity that is nearly h F E times as large as the IIt current, and the output response is correspondingly faster.

Also, the output voltage of a normal TTL output circuit is ij:'G
9) The voltage between the base and emitter of the transistor is twice as low as the voltage between the base and emitter of the transistor, and the voltage between the collector and emitter of the transistor is 1 at low 1/Bell. It is clear that the output in the circuit shown fully satisfies the TTL output standard.

Figures 4 and 5 are circuit connection diagrams showing other examples of firearms according to the present invention, in which the current drive capability and capacitive load drive capability are further improved compared to the output circuit shown in Figure 3. It is something.

As described above, according to the present invention, by adding a bipolar transistor to the conventional CMO8 output circuit, it is possible to provide an fTL output circuit without sacrificing the %6fj driving ability or capacitive load driving ability. Furthermore, by reducing the area occupied by the output circuit with respect to the entire circuit, the size of the chip 1Iiii can be reduced, which has a large effect.

4. Figure m o f'ai 11ift Explanation Figure 1 is a circuit connection diagram showing an embodiment of a CMO8/bipolar transistor hybrid output circuit with the addition of a conventional bipolar transistor. FIG. 2 is a circuit connection diagram showing another embodiment of a conventional CMO8/bipolar transistor hybrid output circuit with the addition of bipolar transistors. FIG. 3 is a circuit connection diagram showing an embodiment of the output circuit of the present invention. Figure 4 and Funeral Figure 5 are
FIG. 7 is a circuit connection diagram showing another embodiment of the output circuit of the present invention.

11.21, 31.41, 51... Input cat,
12.22, 32, 42.52... Output terminal,
3...High-side power supply, 4...Low-side power supply, Qu l 'Q211Qs+ eQ411 QB+
...P channel MOS transistor, Qu t
l Q22 + Qst + Q42 r Qa2・
・Group/N channel MO8) transistor, QIA + Q
14 r Q23 + Qa41 Q441Q46 p
Ql+41 Qii + Q, sa ・・・・・・I
MaP rJ ) J bibolar transistor, Q24
I Qa31 Q4+l + Q45I Qu3...
・・l) f・JI' type bipolar transistor, R1~
J(,2...Resistance, CL...Negative IJ'
h k, 35... Drain of Qa 1 and (J3
The connection point of the base of ゜, the contact point of the drain of 36...Q3□ and the base of Q34.

1--1 □, + Bud/I! r Kaya 2TI! J Tea 3 diagram Kaya 4 Darkness - Mustard 5 diagram

Claims (5)

[Claims] (1) A P-channel MOS transistor and an N-channel MO8) transistor connected in series between power supplies, and a double twin of the P-channel transistor that is cut off when the P-channel MO8) transistor is conductive and is made conductive when the P-channel MO8) transistor is turned on. a first bipolar transistor having a base input of the N-channel MO8I- transistor, which is cut off when the transistor is conducting, and which is turned on when the transistor is turned off;
) has a second bipolar transistor whose base input is the drain of the transistor, and the output is obtained from the output of the second bipolar transistor and the output of the first bipolar transistor. output circuit. (2) The first bipolar transistor is a PNP transistor whose base is connected to the domain 1 of the P-channel MO8) synristor and whose emitter is connected to the high-potential power supply directly or through a resistor; The second bipolar transistor has a base connected to the N-channel M
Claim 1, characterized in that it consists of an NPN) transistor which is connected to the input terminal of the OS) transistor and whose emitter is floated directly or through a resistor to the lower side. The output circuit according to item 1. (3) The collector of the first bipolar transistor and the collector of the second bipolar transistor are connected to provide an output.
The output circuit described in section 2). (4) a third PNP type bipolar transistor whose base is the emitter of the first bivorous transistor, and whose base is connected to the high-level power supply either directly or through a resistor; The emitter of the transistor is the base, and the emitter is connected to the low level (flu source).
a fourth NPN bipolar transistor,
The output circuit according to claim 2, characterized in that the collector of the fourth bipolar transistor is connected to the collector of the third bipolar transistor to provide an output. . (5) an NPN type bipone transistor whose base is the collector of the first bipolar transistor, and whose collector is directly or directly connected to the high-temperature conductor through a resistor; The emitter base and emitter of the Ibora transistor (in Section 2 of 1) has a fourth NPN type bipone transistor connected to the low power supply, and the fourth NPN type bipone transistor has the 2. The output circuit according to claim 2, wherein the output circuit is configured such that the emitter of the third bipolar transistor and the third bipolar transistor are connected to each other and output.