JPS62169326A - Masking method - Google Patents
Masking methodInfo
- Publication number
- JPS62169326A JPS62169326A JP1054586A JP1054586A JPS62169326A JP S62169326 A JPS62169326 A JP S62169326A JP 1054586 A JP1054586 A JP 1054586A JP 1054586 A JP1054586 A JP 1054586A JP S62169326 A JPS62169326 A JP S62169326A
- Authority
- JP
- Japan
- Prior art keywords
- film
- conductive
- wafer
- mask
- conductive film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000873 masking effect Effects 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 title claims description 11
- 238000004544 sputter deposition Methods 0.000 claims abstract description 10
- 238000000059 patterning Methods 0.000 claims abstract 2
- 239000011248 coating agent Substances 0.000 abstract description 22
- 238000000576 coating method Methods 0.000 abstract description 22
- 230000000694 effects Effects 0.000 abstract description 9
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 150000002500 ions Chemical class 0.000 description 2
- 239000000615 nonconductor Substances 0.000 description 2
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- 230000001464 adherent effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明はマスキング方法、特にウェハ平面上にパター
ニングされた膜厚方向にステップ状の導電膜を、スパッ
タリング法にょる成膜で部分的に被咎する場合に用いら
れるマスキング方法に関するものである。[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a masking method, in particular, a method for partially covering a conductive film patterned on a wafer plane with steps in the film thickness direction by forming a film using a sputtering method. This relates to a masking method used when blaming others.
一般に、第2図に示すようにウェハ(1)の平面上に、
膜厚方向にステップ状の導電膜(2)全パターニングす
るとともに、この導電膜(2)をスパッタリング法によ
り同程度の被@膜(8ンで被覆する場合、ウェハ(1)
側にタイミングよくマイナス電位全印加し、いわゆる逆
スパツタ全行ないながらスパッタリング成膜を行ない、
被覆膜(3)にき裂が発生しないようにしている。Generally, on the plane of the wafer (1) as shown in FIG.
When the conductive film (2) is entirely patterned in a step-like manner in the film thickness direction, and the conductive film (2) is coated with a film of the same extent (8 nm) by sputtering, the wafer (1) is
A fully negative potential is applied to the side at the right time, and a sputtering film is formed while performing so-called reverse sputtering.
This prevents cracks from occurring in the coating film (3).
すなわち被覆膜(8)は、ターゲット(4)側がマイナ
スの電位に印加されたとき、チャンバ(5)内の不活性
ガス正イオン(6)がターゲット(4)に衝突したとき
に物理的に飛び出す分子(7)が、対面するウェハ(1
)表面に物理的に付着堆積することによって形成される
。In other words, the coating film (8) physically reacts when positive ions (6) of the inert gas in the chamber (5) collide with the target (4) when a negative potential is applied to the target (4) side. The molecules (7) that fly out are attached to the facing wafer (1).
) is formed by physically adherent deposition on a surface.
この被覆膜(8)は・、ウェハ(1)側にマイナス電位
全印加しない場合には被覆膜(3)にき裂が発生する。This coating film (8) will cause cracks in the coating film (3) if the full negative potential is not applied to the wafer (1) side.
一方つエバ(1)側にマイナス電位を印加した場合には
、第2図に示すようにウェハ(1)側にマイナス電位が
印加された瞬間、チャンバ(5)内の不活性ガス正イオ
ン(6)はウェハ(1)平面上の被覆膜(8)表面に衝
突して被覆膜表面分子(9)が飛び出し、次の瞬間ター
ゲット(4ンにマイナス電位が印加され、被覆膜分子(
γ)が飛来すると、一度被覆膜(8)の表面から飛び出
した分子(9)は、上記き袋部分に入り込むように再付
着してき裂の発生が防止される。On the other hand, when a negative potential is applied to the wafer (1) side, as shown in FIG. 6) collides with the surface of the coating film (8) on the plane of the wafer (1), the coating film surface molecules (9) fly out, and the next moment a negative potential is applied to the target (4), and the coating film molecules (
When γ) comes flying, the molecules (9) that have once jumped out from the surface of the coating film (8) re-adhere so as to enter the above-mentioned bag portion, thereby preventing the occurrence of cracks.
ところで従来、導電膜(2)ヲマスクを用いてマスキン
グする場合、第3図(a) 、 (b)に示すように導
電体マスクαo+’を用い、しかもウェハ(1)平面に
非接触で配している。Conventionally, when masking the conductive film (2) using a mask, a conductive mask αo+' is used, as shown in FIGS. ing.
上記のような従来のマスキング方法では、導電体マスク
(至)を用いてマスキングを行なっているため、ウェハ
(1)側に印加したマイナス電位が導電体マスクαO)
表面上に印加され、上述したような逆スパツタ効果が得
られず、被覆膜(8)にき裂(8)が発生するという問
題がある。In the conventional masking method as described above, since masking is performed using a conductive mask (to), the negative potential applied to the wafer (1) side is applied to the conductive mask αO)
There is a problem in that the reverse sputtering effect as described above cannot be obtained and cracks (8) occur in the coating film (8) because the application is applied onto the surface.
また、導電体マスクαQはウェハ(1)平面に非接触と
なっているため、ウェハ(1)表面に対し斜めに飛来し
てきた被覆膜分子(2)は、導電体マスク(至)により
物理的に遮られてしまい、ために成膜速度が著しく低下
するという問題もある0
この発明はかかる問題点を解決するためになされたもの
で、導電膜をマスクを用いてマスキングした後にスパッ
タリング成膜で被覆する場合でも、被覆膜にき裂が発生
するおそれがないマスキング方法を得ることを目的とす
る。In addition, since the conductive mask αQ is not in contact with the plane of the wafer (1), the coating film molecules (2) that come obliquely to the surface of the wafer (1) are physically removed by the conductive mask (to). There is also the problem that the film formation rate is significantly reduced due to the conductive film being blocked by the mask. It is an object of the present invention to provide a masking method that does not cause any risk of cracks occurring in the coating film even when the coating is coated with a coating film.
この発明に係るマスキング方法は、導電膜を非導電体の
マスクを用いてマスキングするようにしたものである。In the masking method according to the present invention, a conductive film is masked using a non-conductive mask.
この発明においては、導電膜全非導電体のマスクでマス
キングするようにしているので、フェノ−側に印加した
マイナス電位がマスク上には印加されず、この結果上述
し九ような逆スパツタ効果が得られ、被覆膜にき裂を生
じさせることがない0〔実施例〕
第1図(−)、(b)はこの発明の一実施態様金示すも
ので、図中、第2図および第3図(−) 、 (b)と
同一符号は同−又は相当部分金示す。叫は非導電体マス
クで、導電膜(2)の部分?除きウェハ(1)の平面上
に接触している。この非導電体マスク四としては、例え
ばガス放出の少ない耐熱有機絶縁テープが用いられる。In this invention, since the conductive film is masked with a mask made entirely of non-conductors, the negative potential applied to the phenol side is not applied to the mask, and as a result, the reverse spatter effect as described in 9 above occurs. [Example] Figures 1 (-) and (b) show one embodiment of the present invention. The same reference numerals as in Figures 3 (-) and (b) indicate the same or equivalent parts. The shout is a non-conductive mask, and is it the conductive film (2) part? except for the wafer (1). As this non-conductive mask 4, for example, a heat-resistant organic insulating tape that releases little gas is used.
上記のように構成されたマスキング方法においては、ま
ずウェハ(1)の平面上に膜厚方向にステップ状の導電
膜(2)がパターニングされ、次いで導電膜(2)が非
導電体マスク(旧によりマスキングされる。In the masking method configured as described above, first, a step-like conductive film (2) is patterned in the film thickness direction on the plane of the wafer (1), and then the conductive film (2) is patterned as a non-conductive mask (formerly known as masked by
このマスク(旧は、ウェハ(1)の平面に接触するよう
に施される。次いで、導電膜(2)上にスパッタリング
法による成膜で被覆膜(8)が施される。This mask (formerly) is applied so as to be in contact with the plane of the wafer (1). Next, a coating film (8) is applied on the conductive film (2) by sputtering.
この際、導電膜(2)ヲ非導電体マスク明によりマスキ
ングしているので、ウェハ(1)側に印加したマイナス
電位が非導電体マスク叫上に印加されることはなく、シ
たがって充分な逆スパツタ効果が得られて被覆膜(8)
にき裂を生じさせることがない。At this time, since the conductive film (2) is masked with a non-conductive mask, the negative potential applied to the wafer (1) side is not applied to the non-conductive mask, and therefore, the negative potential applied to the wafer (1) side is not applied to the non-conductive mask. A coating film with a reverse spatter effect (8)
Does not cause cracks.
また非導電体マスク叫は、ウェハ(1)の平面上に接触
しているので、ウェハ(1)表面に対し斜めに飛来して
きた被覆膜分子a(1)がマスク(層によって物理的に
遮られることが少なくなり、成膜速度の低下を有効に防
止できる。In addition, since the non-conductive mask layer is in contact with the plane of the wafer (1), the coating film molecules a (1) that have come obliquely to the surface of the wafer (1) are physically caused by the mask (layer). There are fewer interruptions, and a decrease in the film formation rate can be effectively prevented.
なお上記実施の態様では、非導電体マスク(旧ヲウエハ
(1)の平面上に接触させるものについて示したが、成
膜速度を問題にしなければ、マスク(2)全ウェハ(1
)に非接触で配してもよい。In the embodiment described above, the non-conductive mask (old wafer) is brought into contact with the flat surface of the wafer (1), but if the film formation rate is not an issue, the mask (2) can be used to contact the entire wafer (1).
) may be placed without contact.
この発明は以上説明したとおり、導電膜を非導電体のマ
スクでマスキングするようにしているので、ウェハ側に
印加したマイナス電位がマスク上には印加されず、この
結果充分な逆スパツタ効果が得られて被覆膜にき裂が発
生することを完全に防止できる等の効果がある。As explained above, in this invention, since the conductive film is masked with a non-conductive mask, the negative potential applied to the wafer side is not applied to the mask, and as a result, a sufficient reverse spatter effect can be obtained. This has the effect of completely preventing cracks from occurring in the coating film.
第1図(a)はこの発明の一実施態様を示す斜視図、同
図(b)はその断面図、第2図は逆スパツタ効果の説明
図、第3図(a)は従来のマスキング方法を示す第1図
(、)相当図、同図(b)はその断面図である。
(1)m−ウェハ (2)や−導電膜(8)・・
被覆膜 (12J−−非導電体マスクなお各図中
、同一符号は同−又は相当部分全示すものとする。FIG. 1(a) is a perspective view showing one embodiment of the present invention, FIG. 1(b) is a sectional view thereof, FIG. 2 is an explanatory diagram of the reverse spatter effect, and FIG. 3(a) is a conventional masking method. 1(a), and FIG. 1(b) is a sectional view thereof. (1) m-wafer (2) and conductive film (8)...
Coating film (12J--Nonconductor mask) In each figure, the same reference numerals indicate the same or corresponding parts.
Claims (2)
をパターニングするとともに、この導電膜を非導電体の
マスクを用いてマスキングし、次いで導電膜スパツタリ
ング法による成膜で被覆することを特徴とするマスキン
グ方法。(1) Patterning a step-like conductive film in the film thickness direction on the wafer plane, masking this conductive film using a non-conductive mask, and then covering it with a conductive film sputtering method. Featured masking method.
平面に接触していることを特徴とする特許請求の範囲第
1項記載のマスキング方法。(2) The masking method according to claim 1, wherein the non-conductive mask is in contact with the wafer plane except for the conductive film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1054586A JPS62169326A (en) | 1986-01-21 | 1986-01-21 | Masking method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1054586A JPS62169326A (en) | 1986-01-21 | 1986-01-21 | Masking method |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62169326A true JPS62169326A (en) | 1987-07-25 |
Family
ID=11753227
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1054586A Pending JPS62169326A (en) | 1986-01-21 | 1986-01-21 | Masking method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62169326A (en) |
-
1986
- 1986-01-21 JP JP1054586A patent/JPS62169326A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4533624A (en) | Method of forming a low temperature multilayer photoresist lift-off pattern | |
JPS61171131A (en) | Formation of patterned conductive layer on semiconductor | |
JPS5851412B2 (en) | Microfabrication method for semiconductor devices | |
EP1054296A3 (en) | Fine pattern forming method | |
JPS62169326A (en) | Masking method | |
US6686128B1 (en) | Method of fabricating patterned layers of material upon a substrate | |
JP3120596B2 (en) | Method of forming photoresist pattern for manufacturing thin film magnetic head | |
JPH05251314A (en) | Manufacture of double-face absorber x-ray mask | |
JP2580681B2 (en) | Method for manufacturing semiconductor device | |
JPH08264533A (en) | Patterning method | |
JPH01200682A (en) | Manufacture of ferromagnetic magnetoresistance effect device | |
JPS6394424A (en) | Production of thin film magnetic head | |
JPH06104172A (en) | Formation of thin film pattern | |
JPS58161344A (en) | Manufacture of semiconductor device | |
JPS6257218A (en) | Forming method for conducting thin film | |
JPS6185823A (en) | Semiconductor device | |
JPS6255653A (en) | Production of photomask | |
JPH01266545A (en) | Production of reticule | |
JPS61242023A (en) | Formation of fine pattern | |
JPH0279207A (en) | Production of thin film magnetic head | |
JPS6248048A (en) | Manufacture of semiconductor device | |
JPS61224713A (en) | Formation of conductor pattern | |
JPS61114591A (en) | Coating of resist | |
JPS60231331A (en) | Formation of lift-off pattern | |
JPS63255356A (en) | Formation of thin film |