JPS62168254A - Bus control system - Google Patents

Abstract

PURPOSE:To improve the DMA system efficiency by mixing in a prescribed ratio both the bus conflict control which acquires the bus use right after stopping a processor and the bus conflict control which acquires bus use right after the end of a processor cycle. CONSTITUTION:A bus conflict means 15 allows the use of a bus to an input/ output device when a bus use request is received from the input/output device and at the same time outputs a stop request to a processor to confirm the unused state of the processor when a start signal is outputted from the input/ output device for use of the bus. While a bus conflict means 16 confirms the unused state of the processor when a start signal is outputted from the input/ output device and allows the use of bus to the input/output device. Both means 15 and 16 are switched by a switching means 14 in a prescribed ratio for execution of the conflict control.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention, in a direct memory access (hereinafter referred to as DMA) system, allows when an input/output device issues a bus use request, allows the input/output device to use the bus, and also allows a processor to use the bus. a first hash contention means (15) that outputs a stop request to the input/output device, and when a start signal is output from the input/output device, checks whether the processor is in an unused state and causes the processor to use the bus; a second bus contention means (16) that allows bus use by checking the unused state of the processor when an activation signal is output from the input/output device and causes the processor to use the bus; A bus control method is provided that performs bus contention control by switching a second bus contention means at a predetermined ratio.

[Industrial application field]

The present invention relates to a bus control method in a DMA system, and particularly to improvements in bus contention control.

[Conventional technology]

A conventional bus contention control method will be explained based on the drawing illustrated in FIG.

FIG. 3(a) is an explanatory diagram of the first conventional bus contention control method;
FIG. 3 (bl is a time chart diagram thereof, FIG. 3 (C1 is an explanatory diagram of the second conventional bus contention control method, and FIG. 3(d) is a time chart 1 thereof.

In the first hash contention control method, when a DMA request occurs, a stop request is issued to the processor to obtain the right to use the bus.The processor stops operating after the bus cycle in which it is in operation ends. This method reduces waiting time to use the bus.

The details of the lotus competition control system for cylinder 1 will be explained below.

In FIG. 3(a), 1 is a processor, 2 is a memory,
3 is an internal bus contention unit that performs bus contention control on the internal bus 100; 4 is a common bus contention unit that performs bus contention control on the common bus 101 shared by a plurality of input/output devices; 5 is a channel unit for input/output devices, etc.; 6 is a gate provided between the internal bus 100 and the common bus 101, 18 is a gate provided between the processor 1 and the internal bus 100, and 19 is an inverter.

In the above DMA system, the channel unit 5 is the memory 2
When performing a DMA operation on a bus, the following bus contention control is performed. [See FIG. 3(b)] (The 11-channel unit 5 outputs the common bus request signal 50 to the common bus contention unit 4. (Common bus request) (2) The common bus contention unit 4 outputs the common bus request signal 50 to the common bus contention unit 4. 3, and after confirming that the processor 1 and the like are not using the common bus 101, returns the common bus permission signal 52 to the channel unit 5. (Common bus permission) 3) After outputting the common bus permission signal 52, the common bus contention unit 4
outputs a processor stop request signal 53 to the processor 1. (Processor stop request) (4) The channel unit 5 outputs the activation signal 54 to the internal bus contention unit 3 based on the common bus permission signal 52, and also outputs data to the common lot Lot to activate the DMA. (DMA startup) (5) After confirming that the bus of the processor 1 is not in use, the internal bus contention unit 3 opens the gate 6 and uses the internal bus 10.
Force 0 to be used. (DMA start) The above operation is repeated for each byte (or one word).

As described above, this method sends a stop request to the processor 1, so when the input/output device outputs the activation signal 54, the processor 1 is either stopped and no new request signal 61 is issued, or is stopped. The last state is reached, so the latency for DMA initiation is significantly reduced.

The second bus contention method is a method of waiting for use of the internal bus 100 until the end of the bus cycle of the processor 1,
The following bus contention control is performed.

[See FIGS. 3(C) and (d)] (1) The channel unit 5 outputs the common bus request signal 50.

(2) If the processor 1 and the like are not using the common bus 101, respond with the common bus permission signal 52.

(3) The channel unit 5 that has obtained the common bus permission signal 52 outputs the activation signal 54 and activates the DMA, but the processor 1
waits while the internal bus 100 is in use.

(4) The internal bus contention unit 3 determines the end of the bus cycle of the processor 1 by outputting a response signal 62 to the processor 1, opens the gate 6, allows the channel unit 5 to use the internal bus 100, and performs the DMA is started.

The above operation is repeated for each byte (or word).

Note that when the processor 1 uses the internal bus 100, the request signal 61 is sent to the internal hash contention unit 8 every bus cycle.
is output, and the bus cycle is completed using the internal bus 100 in response to the response signal 62 output by the internal bus contention unit 3.

In this method, since the common bus contention unit 7 does not output a stop request to the processor 1, when the activation signal 54 is output, the processor 1 is often still operating, and the channel unit 5 receives the activation signal 54. After outputting , the waiting time until the memory 2 is actually accessed increases on average, and conversely, the waiting time due to DMA of the processor 1 decreases.

[Problem that the invention seeks to solve]

In conventional DMA systems, DM is used for input/output devices, etc.
When there is a request A, a first bus contention method is used in which a stop request is output to the processor to acquire the right to use the bus.

In this first bus contention method, since each byte of DMA is repeated, there is a problem that if the processor is stopped each time, the bus usage ratio of the processor decreases.

For this reason, in recent years, the second bus contention method has been adopted in which the use of the bus is waited until the end of the bus cycle of the processor.

However, as the performance of processors has improved in recent years, the memory access ratio of the processor has increased, so when the channel outputs the activation signal, the processor is almost always using the bus, and the DMA transfer ratio has increased. When a large number of high-speed channels are connected, in the second bus contention method, there is a possibility that a so-called DMA overrun, in which the DMA operation is not completed within a predetermined time, may occur.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a bus control method that improves the usage ratio between memory access and DMA of a processor.

[Means for solving problems]

In order to achieve the above object, the present invention, as shown in the principle explanatory diagram of FIG. a first bus contention means (15) that checks the unused state of the processor and allows the bus to be used when the processor is in use; A second bus contention means (16) that checks the unused state of the processor and uses the bus.
), and a control means (14)' for switching the operations of the first and second bus competition means at a predetermined ratio, and when a bus use request is output from the input/output device, the first and second bus competition means Bus competition control is performed by switching the bus competition means at a predetermined ratio.

[Effect]

A predetermined number of DMA operations are counted, and a processor stop request signal outputted for each lotus use request is reduced to a predetermined ratio.

For example, if a flip-flop is provided that inverts each DMA operation, and its output selects the processor stop request signal, the ratio at which the processor stop request signal is output is l.
/2.

Since the first or second bus contention control is performed depending on whether or not the processor stop request signal is output to the processor, the above means allows the first and second bus contention means to operate at a predetermined ratio. .

〔Example〕

An embodiment of the present invention will be described with reference to FIG.

FIG. 2 (al is a DMA system block diagram of the embodiment, and FIG. 2(b) is an operation time chart.

In FIG. 2(a), reference numeral 9 denotes a common bus contention unit 4 that performs the first bus contention control described above.
A common bus contention unit having the same function as the internal bus contention unit 8 verifies the common bus address information 51 output from the internal bus contention unit 8 with respect to the bus request signal 50 of the channel unit 5, and determines that the common bus 101 is not in use. 8 is an internal bus contention unit which, in addition to the functions of the conventional internal bus contention unit 3, also provides a common bus permission 52 signal to the channel unit 5 and outputs a stop request signal 56 when the DMA is completed. Signal 59 [2nd
10 is a JK flip-flow knob (FF), which counts the DMA end signal 59 and outputs the selection signal 58 shown in FIG. 2(b)-(3). 11 is an AND circuit that performs an AND operation between the selection signal 5B and the stop request signal 56 output from the common bus contention unit 9 and outputs the processor stop request signal 57; other reference numerals as in FIG. Represents the same object.

With the above configuration, FF10 is inverted every DMA end signal 59 and outputs the selection signal 58 for the next DMA operation.

Therefore, the stop request signals 56 output from the common bus contention section 9 are alternately selected by the AND circuit 11 and output as the processor stop request signal 57 to the processor 1.

In this way, the stop request signal 56 output for each DMA operation has a ratio of 1/2, and therefore the aforementioned first bus contention control and second bus contention control are performed at a ratio of 1/2. become.

Another example of ratio setting is shown in FIG. 2(C).

In the figure, 12 is an n-ary counter, and 13 is a comparator that compares the count value A of the n-ary counter 12 with the comparison input value m, and outputs a selection signal 60 when A>m.

The n-ary counter 12 is reset every time the DMA end signal 59 is counted n times, and its output is compared with m, so the stop request signal 56 is selected n-m times out of 0 DMA operations. , a processor stop signal 57 can be output.

Note that the same operation can be performed by using a DMA access signal such as a signal for opening the gate 6 as the DMA end signal.

As explained above, the present invention provides the first
bus contention means and a second method that prioritizes processor access.
Since this is a bus control method that operates the bus competing means at a predetermined ratio, by setting the above ratio according to the DMA system, it is possible to prevent DMA overrun due to expansion of processor functions and speeding up, and also to improve processing of processors. Efficiency can be improved.

〔Effect of the invention〕

The present invention provides a bus control method in which bus contention control in which the processor is stopped to acquire the right to use the bus, and bus contention control in which the right to use the bus is acquired after waiting for the end of the bus cycle of the processor, are mixed at a predetermined ratio. The proposed method has an extremely large effect on improving processing efficiency in a DMA system using a high-performance processor.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 (al is a DMA system block diagram of the embodiment, Fig. 2 (bl is an operation time diagram, Fig. 2 (C)
is a block diagram of another embodiment, FIG. 3 (al is a diagram explaining the first bus contention method, FIG. An explanatory diagram of the bus contention method in Figure 3 (d
) is the second bus contention method operation time chart. In the figure, 1 is a processor, 2 is a memory, 3.8 is an internal bus contention unit, 4.7.9 is a common bus contention unit, 5 is a channel unit, 10 is a JK flip-flop, 11 is an AND circuit, 12 is n decimal counter, 13
is a comparator, 14 is a selection means, I5 is a first bus contention means, and 16 is a second bus contention means. Sheep 2 old ((1) DMA movement leather 2 figure (b) Grass 7's bus competition command muscle goods figure stem 3 figure (a> Figure 3 (,ri)

Claims (1)

[Claims] A processor, a memory, and an input/output device having a direct memory access function that share a bus, and the input/output device that has been granted permission to use the bus in response to a request to use the bus output a bus activation signal. In a direct memory access system, the direct memory access system includes a bus contention means that checks whether a bus is unused by a processor and causes the bus to be used. a first bus contention means (15) for confirming the unused state of the processor and allowing the bus to be used when the activation signal is output; a second bus contention means (16) for confirming the unused state of the processor and allowing the bus to be used when the activation signal of the input/output device is output; and the first and second bus contention means. control means (14) for switching operations at a predetermined ratio; when a bus use request is output from the input/output device, the first and second bus competition means are switched at a predetermined ratio for bus contention control; A bus control method that performs the following.