JPS62165953A - Resin-sealed semiconductor integrated circuit device - Google Patents
Resin-sealed semiconductor integrated circuit deviceInfo
- Publication number
- JPS62165953A JPS62165953A JP831186A JP831186A JPS62165953A JP S62165953 A JPS62165953 A JP S62165953A JP 831186 A JP831186 A JP 831186A JP 831186 A JP831186 A JP 831186A JP S62165953 A JPS62165953 A JP S62165953A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- integrated circuit
- semiconductor integrated
- circuit device
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 230000001681 protective effect Effects 0.000 claims description 5
- 239000011347 resin Substances 0.000 abstract description 8
- 229920005989 resin Polymers 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract 4
- 229910052782 aluminium Inorganic materials 0.000 abstract 4
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 238000007789 sealing Methods 0.000 abstract 1
- 238000000465 moulding Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、樹脂封止形半導体集積回路装置における配
線構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a wiring structure in a resin-sealed semiconductor integrated circuit device.
第８図は、従来の配線構造の一例を示す。（１）はモー
ルド樹脂、（２）は表面保護膜、 （３）（４）は絶縁
膜、（５）は８ｉ基板、（６）はＭ配゛線、（８）はモ
ールド樹脂より加わる横方向のストレスである。FIG. 8 shows an example of a conventional wiring structure. (1) is the mold resin, (2) is the surface protection film, (3) and (4) are the insulating films, (5) is the 8i board, (6) is the M wiring, and (8) is the lateral force applied by the mold resin. It is directional stress.
従来、チップのモールド成型時や、成型後に温度サイク
ルを繰り返した場合、横方向の強いストレス（８）が、
モールド樹脂（１）より、Ｓｉ基板（５）上に突出して
いるＭ配線（６）に加わり、これをスライドさせ、断線
不良を発生していた。Conventionally, when molding a chip or repeating temperature cycles after molding, strong lateral stress (8)
The M wiring (6) protruding from the mold resin (1) onto the Si substrate (5) was joined and slid, causing a disconnection failure.
この発明は、前記のような問題点を解決するためになさ
れたものであり、モールド樹脂によるＭ配線へのストレ
スを弱め、Ｍ配線の断線を防止することを目的とする。This invention was made to solve the above-mentioned problems, and aims to reduce the stress on the M wiring due to the molding resin and prevent disconnection of the M wiring.
この発明に係る樹脂封止形半導体集積回路装置１！は、
Ｍ配線の両側に、選択的に絶縁膜を形成するようにした
ものである。Resin-sealed semiconductor integrated circuit device 1 according to the present invention! teeth,
Insulating films are selectively formed on both sides of the M wiring.
この発明による選択的に形成された絶縁膜は、モールド
樹脂による横方向のストレスからＭ配線を保護し、断線
による不良を抑制する。The selectively formed insulating film according to the present invention protects the M wiring from lateral stress caused by the molding resin, and suppresses defects due to disconnection.
以下、この発明の実施例を図に従って説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第１図は、この発明の一実施例による樹脂封止形半導体
集積回路装置の断面構造を示し、第２図は・その製造フ
ローに従った断面構造の変化を示す。FIG. 1 shows a cross-sectional structure of a resin-sealed semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 2 shows changes in the cross-sectional structure according to its manufacturing flow.
第２図ａは、前もって、シリコン基板Ｃ５）上にＭ配線
する両側をＬＯＣＯ８（ＬＯＣａ Ｉ ０ｘｉｄａｔｉ
ｏｎ ｏｆ ８ｉ１ｉｃｏｎ〕により選択的【酸化し、
絶縁膜（７）を形成した状態である。第２１図すは、絶
縁膜＋３） （４）を形成した状態である。第２図Ｃは
、Ｍ配線（６）を形成し、その上に表面保護膜（２）を
形成した状態である。これら第２図、〜。の工程により
、最終的なＡｌｌ！！８線（６）上の表面保護膜（２）
の昼さけ、選択的に形成された絶縁膜（７）上のそれよ
り低くなる。このような配線構造（第１図）のＡｚ配線
（６）に、モールド樹脂（１）より横方向のストレス（
８）が加わった場合、このストレス（８）は、選択的に
形成された絶縁膜（７）およびこの」−に形成されたＭ
（２１（３） （＋１により弱められる。FIG. 2a shows that both sides of the M wiring on the silicon substrate C5) are connected in advance to LOCO8 (LOCa I Oxidati).
on of 8i1icon] selectively [oxidizes,
This is a state in which an insulating film (7) is formed. FIG. 21 shows the state in which the insulating film +3) (4) has been formed. FIG. 2C shows a state in which an M wiring (6) is formed and a surface protective film (2) is formed thereon. These Figures 2, ~. Through this process, the final All! ! Surface protective film (2) on 8 wire (6)
At around noon, it becomes lower than that on the selectively formed insulating film (7). The Az wiring (6) of such a wiring structure (Fig. 1) is subjected to lateral stress (
8), this stress (8) is applied to the selectively formed insulating film (7) and the M formed on this
(21(3) (Weakened by +1.
上記の配線構造は、横方向のストレスのかかりやすい半
導体集積回路装置の周辺に施すと効果が顕著である。The above wiring structure is most effective when applied around the semiconductor integrated circuit device where lateral stress is likely to be applied.
以上のようにこの発明は、配線の両側に選択的に絶縁膜
を形成したので、モールド樹脂による横方向のストレス
から配線を保護し、配線の断線を抑制することができる
。As described above, in the present invention, since the insulating film is selectively formed on both sides of the wiring, the wiring can be protected from lateral stress caused by the molding resin, and disconnection of the wiring can be suppressed.
第１図はこの発明の一実施例による半導体集積回路装置
の断面図、第２図はその製造工程に従った断面図、第８
図は従来の半導体集積回路装ｊｆの断面図である。
（１）はモールド樹脂、（２）は表面保護膜、（３）
（４１は絶縁膜、（５）はＳｉ基板、（６）はＭ配線、
（７）は選択的に形成した絶縁膜、（８）は横方向のス
トレスで、ｆ）る。
なお、各図中の同一符号は、同一または相当部分を示す
。FIG. 1 is a cross-sectional view of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view according to its manufacturing process, and FIG.
The figure is a sectional view of a conventional semiconductor integrated circuit device jf. (1) is mold resin, (2) is surface protective film, (3)
(41 is an insulating film, (5) is a Si substrate, (6) is an M wiring,
(7) is a selectively formed insulating film, (8) is lateral stress, and f). Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (4)
記配線に加わる横方向のストレスを、上記絶縁膜により
抑制することを特徴とする樹脂封止形半導体集積回路装
置。(1) A resin-sealed semiconductor integrated circuit device, characterized in that an insulating film is selectively formed on both sides along the wiring, and the insulating film suppresses lateral stress applied to the wiring.
の範囲第１項記載の樹脂封止形半導体集積回路装置。(2) A resin-sealed semiconductor integrated circuit device according to claim 1, wherein the wiring is made of Al.
形成したことを特徴とする特許請求の範囲第１項又は第
２項記載の樹脂封止形半導体集積回路装置。(3) A resin-sealed semiconductor integrated circuit device according to claim 1 or 2, characterized in that wiring and an insulating film are formed on the periphery of the semiconductor integrated circuit device.
に延在する表面保護膜の高さより低いことを特徴とする
特許請求の範囲第１〜３項の何れかに記載の樹脂封止形
半導体集積回路装置。(4) The height of the surface protective film extending over the wiring is lower than the height of the surface protective film extending over the insulating film, according to any one of claims 1 to 3. resin-sealed semiconductor integrated circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP831186A JPS62165953A (en) | 1986-01-17 | 1986-01-17 | Resin-sealed semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP831186A JPS62165953A (en) | 1986-01-17 | 1986-01-17 | Resin-sealed semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62165953A true JPS62165953A (en) | 1987-07-22 |
Family
ID=11689604
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP831186A Pending JPS62165953A (en) | 1986-01-17 | 1986-01-17 | Resin-sealed semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62165953A (en) |
-
1986
- 1986-01-17 JP JP831186A patent/JPS62165953A/en active Pending
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