JPS63260039A - Resin sealed type semiconductor device - Google Patents
Resin sealed type semiconductor deviceInfo
- Publication number
- JPS63260039A JPS63260039A JP9435887A JP9435887A JPS63260039A JP S63260039 A JPS63260039 A JP S63260039A JP 9435887 A JP9435887 A JP 9435887A JP 9435887 A JP9435887 A JP 9435887A JP S63260039 A JPS63260039 A JP S63260039A
- Authority
- JP
- Japan
- Prior art keywords
- film
- photoresist
- bonding pad
- glassivation
- strain buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 239000011347 resin Substances 0.000 title abstract description 5
- 229920005989 resin Polymers 0.000 title abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 229920001721 polyimide Polymers 0.000 abstract description 6
- 238000000206 photolithography Methods 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract description 2
- 238000000059 patterning Methods 0.000 abstract description 2
- 230000002093 peripheral effect Effects 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 238000007789 sealing Methods 0.000 abstract 1
- 239000009719 polyimide resin Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は樹脂封止型半導体装置に関し、特にチップ製造
における表面保護膜に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a resin-sealed semiconductor device, and more particularly to a surface protective film used in chip manufacturing.
従来の樹脂封止型半導体装置の表面保護は、第2図に示
すように、半導体基板1上に形成された酸化シリコン等
からなる絶縁膜2を介して形成されたボンディングパッ
ド3の周辺を含む全面に、グラシベーション膜4を形成
し、ボンディングワイヤー6をボンディングパッド部に
接続したのち、全面に有機物からなるジャンクションコ
ート膜7を形成するか、または第3図に示すように、グ
ラシベーション膜4上にポリイミド樹脂膜8等を形成す
ることにより行なわれていた。そしてこれらジャンクシ
ョンコート膜7やポリイミド樹脂膜8上に封入用の樹脂
層が形成されていた。As shown in FIG. 2, surface protection of a conventional resin-sealed semiconductor device includes the area around a bonding pad 3 formed on a semiconductor substrate 1 via an insulating film 2 made of silicon oxide or the like. After forming the gravitation film 4 on the entire surface and connecting the bonding wire 6 to the bonding pad portion, a junction coat film 7 made of an organic substance is formed on the entire surface, or as shown in FIG. This was done by forming a polyimide resin film 8 or the like thereon. A resin layer for encapsulation was formed on the junction coat film 7 and the polyimide resin film 8.
半導体装置の多機能化にともないチップ面積が大きくな
っている。As semiconductor devices become more multifunctional, the chip area becomes larger.
しかるに樹脂封止型半導体装置に於ては、封止樹脂とチ
ップの熱膨張係数が異なるため、熱環境試験でチップ表
面に歪によるクラックが発生し、ひいては、チップ内配
線のオープン又はショートの発生原因となり、信頼度を
低下させるという問題があり、チップの大きいものほど
当該傾向が大きい。その為無機質のグラシベーション膜
4をはどこした半導体チップには、上述したようにジャ
ンクションコート膜やポリイミド樹脂膜等からなる歪緩
衝膜を形成し対応している。However, in resin-encapsulated semiconductor devices, because the thermal expansion coefficients of the encapsulating resin and the chip are different, cracks may occur on the chip surface due to strain during thermal environment tests, which can lead to open or short circuits in the wiring within the chip. There is a problem that this causes a decrease in reliability, and the larger the chip, the greater this tendency is. For this reason, a strain buffer film made of a junction coat film, a polyimide resin film, or the like is formed as described above on the semiconductor chip on which the inorganic gracivation film 4 is applied.
しかしながら、このような従来の歪緩衝膜を形成する方
法では、写真蝕刻工程が増えたりして製造工程が煩雑と
なり、製造原価が高くなるという問題点がある。However, such a conventional method for forming a strain buffer film has a problem in that the manufacturing process becomes complicated due to an increase in the number of photolithography steps, and the manufacturing cost increases.
本発明の目的は、製造原価の低減された歪緩衝膜を有す
るIBI脂封止型半導体装置を提供することにある。An object of the present invention is to provide an IBI fat-sealed semiconductor device having a strain buffer film with reduced manufacturing cost.
本発明の樹脂封止型半導体装置は、半導体基板上に絶縁
膜を介して形成されたボンディングパッドと、前記ボン
ディングパッドの周辺部を含む全面に形成されたグラシ
ベーション膜と、前記グラシベーション膜上に形成され
たホトレジストからなる歪緩衝膜とを含んで構成される
。The resin-sealed semiconductor device of the present invention includes a bonding pad formed on a semiconductor substrate with an insulating film interposed therebetween, a gracivation film formed on the entire surface including the periphery of the bonding pad, and a gracivation film formed on the gracivation film. and a strain buffer film made of photoresist formed on the substrate.
本発明によれば、グラシベーション膜に開口部茗形成す
るために使用するホトレジスト膜を歪綬mlとして用い
るため、歪緩衝膜を形成する為の材料や工程を特に必要
としない。According to the present invention, since the photoresist film used to form the openings in the gracivation film is used as the strain ribbon, there is no particular need for materials or processes for forming the strain buffer film.
次に、本発明の実施例について図面を用いて説明する。 Next, embodiments of the present invention will be described using the drawings.
第1図は本発明の一実施例の断面図である。FIG. 1 is a sectional view of an embodiment of the present invention.
第1図において、素子が形成された半導体基板1上には
酸1ヒシリコン膜等の絶縁膜2を介してボンディングパ
ッド3が形成されており、このボンディングパッド3の
ボンディングワイヤー6が接続される部分を除く全面に
は、グラシベーション115I4とホトレジスト膜5か
らなる歪緩衝膜が形成されている。そしてこの表面状態
で樹脂封入が行なわれる。In FIG. 1, a bonding pad 3 is formed on a semiconductor substrate 1 on which an element is formed through an insulating film 2 such as an acid-1-arsenic silicon film, and a portion of this bonding pad 3 to which a bonding wire 6 is connected is formed. A strain buffer film consisting of a glacivation layer 115I4 and a photoresist film 5 is formed on the entire surface except for the area. Then, resin encapsulation is performed in this surface state.
このホトレジスト膜5は、グラシベーション膜4を全面
に形成しボンディングパッド部上に開口部を形成する場
合に用いるマスクをそのまま利用することができ、ホト
レジス)・膜5は従来のポリイミド膜より厚くてもよい
。This photoresist film 5 can be used as is in the mask used when forming the gracivation film 4 on the entire surface and forming an opening on the bonding pad.The photoresist film 5 is thicker than the conventional polyimide film. Good too.
このように構成された本実施例においては、グラシベー
ション膜のパターニングに用いるホトレジスト膜を歪緩
衝膜として用いるため、写真蝕刻工程が少くなり、半導
体装置の製造原価は低減される。In this embodiment configured in this manner, the photoresist film used for patterning the glacivation film is used as a strain buffer film, so the number of photolithography steps is reduced and the manufacturing cost of the semiconductor device is reduced.
以上説明したように本発明は、ボンディングパッドの周
辺部を含む前面にグラシベーション膜とホトレジストか
らなる歪緩衝膜を形成することにより、樹脂封止型半導
体装置の製造原価を低減できる効果がある。As explained above, the present invention has the effect of reducing the manufacturing cost of a resin-sealed semiconductor device by forming a strain buffer film made of a gravitation film and a photoresist on the front surface including the peripheral portion of the bonding pad.
第1図は本発明の一実施例の断面図、第2図及び第3図
は従来の樹脂封止型半導体装置の断面図である。
1・・・半導体基板、2・・・絶縁膜、3・・・ボンデ
ィングパッド、4・・・グラシベーション膜、5・・・
ホトレジスI・膜、6・・・ボンディングワイヤー、7
・・・ジャンクションヨー1〜膜、8・・・ポリイミド
樹脂膜。FIG. 1 is a sectional view of an embodiment of the present invention, and FIGS. 2 and 3 are sectional views of a conventional resin-sealed semiconductor device. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Insulating film, 3... Bonding pad, 4... Gracivation film, 5...
Photoresist I/film, 6... bonding wire, 7
...Junction Yaw 1~membrane, 8...Polyimide resin film.
Claims (1)
グパッドと、前記ボンディングパッドの周辺部を含む全
面に形成されたグラシベーション膜と、前記グラシベー
ション膜上に形成されたホトレジストからなる歪緩衝膜
とを含むことを特徴とする樹脂封止型半導体装置。A bonding pad formed on a semiconductor substrate via an insulating film, a gracivation film formed on the entire surface including the periphery of the bonding pad, and a strain buffer film made of photoresist formed on the gracivation film. A resin-sealed semiconductor device comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9435887A JPS63260039A (en) | 1987-04-16 | 1987-04-16 | Resin sealed type semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9435887A JPS63260039A (en) | 1987-04-16 | 1987-04-16 | Resin sealed type semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63260039A true JPS63260039A (en) | 1988-10-27 |
Family
ID=14108072
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9435887A Pending JPS63260039A (en) | 1987-04-16 | 1987-04-16 | Resin sealed type semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63260039A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6239018A (en) * | 1985-08-14 | 1987-02-20 | Mitsubishi Electric Corp | Formation of passivation film |
-
1987
- 1987-04-16 JP JP9435887A patent/JPS63260039A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6239018A (en) * | 1985-08-14 | 1987-02-20 | Mitsubishi Electric Corp | Formation of passivation film |
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