JPS6216586B2 - - Google Patents

Info

Publication number
JPS6216586B2
JPS6216586B2 JP55002356A JP235680A JPS6216586B2 JP S6216586 B2 JPS6216586 B2 JP S6216586B2 JP 55002356 A JP55002356 A JP 55002356A JP 235680 A JP235680 A JP 235680A JP S6216586 B2 JPS6216586 B2 JP S6216586B2
Authority
JP
Japan
Prior art keywords
output
signal
transistor
circuit
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55002356A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5698952A (en
Inventor
Naotoshi Higashama
Kazuyuki Doi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP235680A priority Critical patent/JPS5698952A/ja
Publication of JPS5698952A publication Critical patent/JPS5698952A/ja
Publication of JPS6216586B2 publication Critical patent/JPS6216586B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H40/00—Arrangements specially adapted for receiving broadcast information
    • H04H40/18—Arrangements characterised by circuits or components specially adapted for receiving
    • H04H40/27—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95
    • H04H40/36—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving
    • H04H40/45—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving for FM stereophonic broadcast systems receiving
    • H04H40/63—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving for FM stereophonic broadcast systems receiving for separation improvements or adjustments
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D1/00—Demodulation of amplitude-modulated oscillations
    • H03D1/22—Homodyne or synchrodyne circuits
    • H03D1/2209—Decoders for simultaneous demodulation and decoding of signals composed of a sum-signal and a suppressed carrier, amplitude modulated by a difference signal, e.g. stereocoders
    • H03D1/2227—Decoders for simultaneous demodulation and decoding of signals composed of a sum-signal and a suppressed carrier, amplitude modulated by a difference signal, e.g. stereocoders using switches for the decoding

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Stereo-Broadcasting Methods (AREA)
JP235680A 1980-01-11 1980-01-11 Demodulation circuit for stereo signal Granted JPS5698952A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP235680A JPS5698952A (en) 1980-01-11 1980-01-11 Demodulation circuit for stereo signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP235680A JPS5698952A (en) 1980-01-11 1980-01-11 Demodulation circuit for stereo signal

Publications (2)

Publication Number Publication Date
JPS5698952A JPS5698952A (en) 1981-08-08
JPS6216586B2 true JPS6216586B2 (enrdf_load_stackoverflow) 1987-04-13

Family

ID=11526985

Family Applications (1)

Application Number Title Priority Date Filing Date
JP235680A Granted JPS5698952A (en) 1980-01-11 1980-01-11 Demodulation circuit for stereo signal

Country Status (1)

Country Link
JP (1) JPS5698952A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006001173A1 (ja) * 2004-06-25 2006-01-05 Niigata Seimitsu Co., Ltd. ステレオセパレーション調整回路及びそのｍｏｓ集積回路

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3714595A (en) * 1971-03-25 1973-01-30 Warwick Electronics Inc Demodulator using a phase locked loop
JPS53147611U (enrdf_load_stackoverflow) * 1977-04-26 1978-11-20

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006001173A1 (ja) * 2004-06-25 2006-01-05 Niigata Seimitsu Co., Ltd. ステレオセパレーション調整回路及びそのｍｏｓ集積回路

Also Published As

Publication number Publication date
JPS5698952A (en) 1981-08-08

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