JPS6216552A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6216552A JPS6216552A JP60061804A JP6180485A JPS6216552A JP S6216552 A JPS6216552 A JP S6216552A JP 60061804 A JP60061804 A JP 60061804A JP 6180485 A JP6180485 A JP 6180485A JP S6216552 A JPS6216552 A JP S6216552A
- Authority
- JP
- Japan
- Prior art keywords
- package
- leads
- semiconductor device
- lead
- upper package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は半導体装置に係り、特に複数のパッケージを積
み重ねて構成される半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and particularly to a semiconductor device configured by stacking a plurality of packages.
（従来の技術）
従来、半導体装置の機能を容易に向上させる方法として
、複数個の半導体装置を重ね合わせることにより、１つ
の半導体装置を構成する所謂ビギーバンク（ＰＩＧＧＹ
ＢＡＩＪ）法が提案され実用化されてきている。(Prior Art) Conventionally, as a method for easily improving the functions of a semiconductor device, a so-called PIGGY bank, in which a single semiconductor device is constructed by stacking a plurality of semiconductor devices, has been proposed.
BAIJ) method has been proposed and put into practical use.
第４図及び第５図は、例えば、実公昭５５−１２４４０
号公報に示される上記したピギーバック法によって構成
される半導体装置の説明図である。Figures 4 and 5 are, for example,
FIG. 2 is an explanatory diagram of a semiconductor device constructed by the above-mentioned piggyback method shown in the above publication.
まず、第４図に示される従来の積み重ね型半導体装置の
について説明すると、半導体素子１．２をそれぞれパッ
ケージした半導体装置３．４を上下方向に重ね合わせた
上で、各々のリードフレーム５．６の相対するリードを
それぞれ半田或いはスポット溶接によって接続し、これ
を１つの半導体装置として構成するようにしている。し
かしながら、この方法によると、パッケージ内に収容さ
れる半導体素子が熱による悪影響を受は易い素子である
場合には接続の際に受ける熱により素子の特性が不良に
なることがある。このため、第５図（ａ）、（ｂ）に示
されるように下部パッケージ７のリード８に長ｉ＄１９
を設け、上部パッケージ１０のリード１１の先端部をこ
の長溝９に挿入した後リードの側面からかしめ止めを行
う方法や、第５図（ｃ）、（ｄ）に示されるように下部
パンケージ７のリード８に孔１２を設け、上部パッケー
ジ１０のリード１１の先端部をこの孔１２に挿入してリ
ード８とリード１１とをリードの板厚の方向からかしめ
を行う方法が採用されている。First, to explain the conventional stacked type semiconductor device shown in FIG. The opposing leads of the semiconductor device are connected by soldering or spot welding to form one semiconductor device. However, according to this method, if the semiconductor element housed in the package is an element that is easily affected by heat, the characteristics of the element may deteriorate due to the heat received during connection. Therefore, as shown in FIGS. 5(a) and 5(b), the leads 8 of the lower package 7 have a length of 19
5(c) and 5(d), the tips of the leads 11 of the upper package 10 are inserted into the long grooves 9 and then caulked from the sides of the leads. A method is adopted in which a hole 12 is provided in the lead 8, the tip of the lead 11 of the upper package 10 is inserted into the hole 12, and the lead 8 and the lead 11 are caulked from the direction of the plate thickness of the lead.
（発明が解決しようとする問題点）
しかしながら、上記の従来のものは上下パッケージにデ
ュアルライン型（ＤＩＰ）を使用し、パッケージ本体も
厚く、挿入実装方式なので従来技術が適用できるとして
も、半導体装置のピンの数が増加し、多ピン化してくる
ともはや従来のようにリードを１つ１つかしめることは
困難であるという問題があった。(Problems to be Solved by the Invention) However, the above conventional method uses a dual line type (DIP) for the upper and lower packages, has a thick package body, and is an insertion mounting method, so even if the conventional technology can be applied, the semiconductor device As the number of pins increases and the number of pins increases, there is a problem in that it is no longer possible to tighten the leads one by one as in the past.
このような状況から、従来のものではパッケージも厚く
、挿入実装方式である場合に適用されるにすぎず、この
ような半導体装置の実装密度は著しく低く、リードフレ
ームの構造も複雑にならざるを得ないものであった。Under these circumstances, conventional semiconductor devices have thick packages and are only applicable to insertion mounting methods, and the packaging density of such semiconductor devices is extremely low and the structure of the lead frame is complicated. It was something I couldn't get.
本発明は、上記の問題点を除去し、構造が簡単であり多
ピン化した場合においてもその組み立てが容易で実装密
度の向上を図り得る半導体装置を提供することを目的と
する。SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device which eliminates the above-mentioned problems, has a simple structure, is easy to assemble even when the number of pins is increased, and can improve packaging density.
（問題点を解決するための手段）
本発明は、上記の問題点を解決するために、複数のパッ
ケージを積み重ねて構成される半導体装置において、下
部パッケージのリードを折曲し、下方の基板に接触させ
る部分を形成すると共に上方には上部パッケージを挟持
し得る立ち上がり部分を形成するように構成する。(Means for Solving the Problems) In order to solve the above problems, the present invention, in a semiconductor device configured by stacking a plurality of packages, bends the leads of the lower package and connects them to the substrate below. It is configured to form a contacting portion and also to form a rising portion above which can hold the upper package.
（作用）
下部パッケージ１３のリード１５の立ち上がり部１５−
１，１５−１間に上部パッケージを上方より押し込み、
その立ち上がり部１５・−１，１５−１に上部パッケー
ジ１６のリードの１８を圧接するように実装する。つま
り、リード１５の立ち上がり部１５−１．１５−１間に
上部パッケージ１６は挟持され積み重ねられる。(Function) Rising portion 15- of lead 15 of lower package 13
1, Push the upper package from above between 15-1,
Leads 18 of the upper package 16 are mounted so as to be in pressure contact with the rising portions 15.-1 and 15-1. That is, the upper package 16 is sandwiched between the rising portions 15-1 and 15-1 of the leads 15 and stacked.
（実施例）
以下、本発明の実施例を図面を参照しながら詳細に説明
する。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図は、本発明に係る積み重ね型半導体装置の説明図
であり、第１図（ａ、）は半導体装置の下部パッケージ
の断面図、第１図（ｂ）は半導体装置の上部、下部パッ
ケージが組み合わせられた積み重ね型の半導体装置の断
面図である。FIG. 1 is an explanatory diagram of a stacked semiconductor device according to the present invention, FIG. 1(a) is a sectional view of a lower package of the semiconductor device, and FIG. 1(b) is a cross-sectional view of the upper and lower packages of the semiconductor device. FIG. 2 is a cross-sectional view of a stacked semiconductor device in which two types of semiconductor devices are combined.
これらの図において、まず、１３は半導体装置の下部パ
ッケージであり、例えば、フラット型集積回路（ＩＣ）
装置、１４はこの下部パッケージ１３にモールドされる
半導体素子、１５はこのパッケージ１３のリード、１５
−１はリードの立ち上がり部、１５−２はこの立ち上が
り部１５−１に連設される湾曲部、１５−３はこの湾曲
部に連設される立ち下がり部である。一方、１６は半導
体装置の上部パッケージであり、例えば、チップキャリ
ア型ＩＣｖ装置、１７はこの上部パッケージ１６にモー
ルドされる半導体素子、１８はこのパッケージ１６のリ
ード、１９は基板である。In these figures, 13 is a lower package of a semiconductor device, for example, a flat integrated circuit (IC).
14 is a semiconductor element molded into this lower package 13; 15 is a lead of this package 13; 15
-1 is a rising part of the lead, 15-2 is a curved part connected to this rising part 15-1, and 15-3 is a falling part connected to this curved part. On the other hand, 16 is an upper package of a semiconductor device, for example, a chip carrier type ICv device, 17 is a semiconductor element molded into this upper package 16, 18 is a lead of this package 16, and 19 is a substrate.
第１図（ａ）に示されるように、下部パッケージ１３の
リード１５は、立ち上がり部１５−１、湾曲部１５−２
、立ち下がり部１５−３から成る。As shown in FIG. 1(a), the leads 15 of the lower package 13 include a rising portion 15-1 and a curved portion 15-2.
, and a falling portion 15-3.
一方、第１図（ｂ）に示されるように、上部パッケージ
１６はリード１８を有している。そこで、基板１７上に
前記下部パッケージ１３のリードの立ち下がり部１５−
３の先端部を取り付けて基板１７に下部パッケージ１３
を表面実装し、対向するり一ド１５−１．１５−１間に
上部パッケージ１６のリード１８を挟持させるように装
着する。On the other hand, as shown in FIG. 1(b), the upper package 16 has leads 18. Therefore, the falling portions 15- of the leads of the lower package 13 are placed on the substrate 17.
3 and attach the lower package 13 to the substrate 17.
are surface-mounted and mounted so that the leads 18 of the upper package 16 are sandwiched between the opposing leads 15-1 and 15-1.
つまり、下部パッケージのり一ド１５の立ち上がり部１
５−１によって囲まれた空間に上部パッケージ１６を互
いのリードが圧接されるように上方より押し込むことに
より実装する。In other words, the rising portion 1 of the lower package glue 15
The upper package 16 is mounted by pushing it into the space surrounded by 5-1 from above so that the leads are pressed against each other.
第２図は多端子対応積み重ね型半導体装置の斜視図であ
り、下部パッケージ２０のリード２１には立ち上がり部
が形成され、上部パッケージ２２が下部パッケージのリ
ード２１によって囲まれた空間に上方より装着され、実
装される。この場合にはり一ド２１が下部パッケージ２
０の４つの側面に位置するために、上部パッケージ２２
の位置決めが容易であり確実な接続を行うことができる
。FIG. 2 is a perspective view of a multi-terminal stacked semiconductor device, in which the leads 21 of the lower package 20 are formed with rising parts, and the upper package 22 is mounted from above into a space surrounded by the leads 21 of the lower package. , implemented. In this case, the beam 21 is the lower package 2.
0 to be located on the four sides of the upper package 22
Positioning is easy and reliable connections can be made.
第３図は本発明の第３の実施例を示す積み重ね型半導体
装置の説明図であり゛、上記の下部パンケージのリード
の形状を更に変形したものである。FIG. 3 is an explanatory view of a stacked semiconductor device showing a third embodiment of the present invention, in which the shape of the leads of the lower pancage described above is further modified.
つまり、下部パッケージのリードの立ち上がり部２５−
１の所望の位置に段部２５−４を設けてこの段部２５−
４で上部パッケージのリード２６を受けるようにしたも
のである。このように構成すると上部パッケージを押し
込み、上部パッケージのリード２６が段部２５−４に係
合して下方へのストッパの役目をし、上部パッケージの
Ｘ、Ｙ、θ方向の位置決めを確実にすると共に実装を容
易にし、しかもリード２５とリード２６間の接触面積を
増大させて、接続を良好にすることができる。In other words, the rising portion 25- of the leads of the lower package
A step portion 25-4 is provided at a desired position of the step portion 25-4.
4 to receive the leads 26 of the upper package. With this configuration, when the upper package is pushed in, the leads 26 of the upper package engage with the stepped portion 25-4 and act as a downward stopper, ensuring the positioning of the upper package in the X, Y, and θ directions. At the same time, it is possible to facilitate mounting, increase the contact area between the leads 25 and 26, and improve the connection.
次に第６図は本発明の第４の実施例を示す積み重ね型半
導体装置の断面図であり、２７は半導体素子２８をパッ
ケージした下部パッケージ、２９は下部パッケージ２７
のリードであり、このリード２９は予めリード毎に分岐
部２２より２分割できるような構造にしておき、その２
分割した一方を上方へ、もう一方を下方にそれぞれ折曲
させ、上方リード２９−２、下方リード２９−３を形成
する。３０は半導体装置３１をパッケージした上部パッ
ケージ、３２は上部パッケージ３０のリードである。こ
こで、下部パッケージは下方２９−３を使用して基板１
９に表面実装する。また、上方リード２９−３により囲
まれた空間に上方パッケージ３０を上方より押し込み、
上部パッケージのり一ド３２と下部パッケージのリード
２９が互いに圧接するように実装する。Next, FIG. 6 is a sectional view of a stacked semiconductor device showing a fourth embodiment of the present invention, in which 27 is a lower package in which a semiconductor element 28 is packaged, and 29 is a lower package 27.
This lead 29 is structured in advance so that it can be divided into two from the branch part 22 for each lead, and the two
One of the divided parts is bent upward and the other part is bent downward to form an upper lead 29-2 and a lower lead 29-3. 30 is an upper package in which the semiconductor device 31 is packaged, and 32 is a lead of the upper package 30. Here, the lower package uses the lower part 29-3 to
Surface mounting on 9. Further, the upper package 30 is pushed into the space surrounded by the upper leads 29-3 from above,
The upper package glue 32 and the leads 29 of the lower package are mounted in pressure contact with each other.
次に第７図は本発明の第５の実施例を示す積み重ね型半
導体装置の断面図である０図中、３３は下部パッケージ
であり、その内部には半導体装置３４が収容されている
。３５は下部パッケージ３３のリードであり、このリー
ド３５は立ち下がり部３５−１、この立ち下がり部３５
−１に続（湾曲部３５−２、この湾曲部３５−２に続く
立ち上がり部３５−３から成る。３６は上部パッケージ
であり、その内部には半導体装置３７が収容されている
。３８はこの上部パッケージ３６のリードである。この
図から明らかなように、下部パンケージのリード３５に
設けられた下方に位置する湾曲部３５−２を用いて基板
１９に実装する。更に、上部パッケージ３６を下部パッ
ケージのリードの立ち上がり部３５−３で囲まれる空間
に押し込み、上部パッケージ３６のリード３Ｂと下部パ
ッケージのリードの立ち上がり部３５−３が圧接するよ
うに実装する。Next, FIG. 7 is a sectional view of a stacked semiconductor device according to a fifth embodiment of the present invention. In FIG. 35 is a lead of the lower package 33, and this lead 35 has a falling portion 35-1 and a falling portion 35-1.
36 is an upper package in which a semiconductor device 37 is housed. 38 is an upper package. These are the leads of the upper package 36. As is clear from this figure, the lower pancage leads 35 are mounted on the board 19 using the downwardly positioned curved portions 35-2. The package is pushed into a space surrounded by the rising parts 35-3 of the leads of the package, and mounted so that the leads 3B of the upper package 36 and the rising parts 35-3 of the leads of the lower package come into pressure contact.
第８図は本発明の第６の実施例を示す積み重ね型半導体
装置の断面図であり、第７図に示される下部パッケージ
のリードを更に変形したものである。つまり、リードの
立ち上がり部の途中に段部３９−４を設けて、この段部
３９−４で上部パッケージのリードを受けるようにする
０機能としては、第３図に示されたものと同様である。FIG. 8 is a sectional view of a stacked semiconductor device showing a sixth embodiment of the present invention, in which the leads of the lower package shown in FIG. 7 are further modified. In other words, the function of providing a step 39-4 in the middle of the rising part of the lead and receiving the lead of the upper package at this step 39-4 is similar to that shown in FIG. be.
なお、上部パッケージの脱落が懸念される場合には、上
部パッケージを接着剤等を用いて下部パ。If there is a concern that the upper package may fall off, use adhesive or the like to attach the upper package to the lower part.
ソケージに固定しても良い、また、上部パッケージであ
るチップキャリア型半導体装置はチンプキャリア型であ
れば、パッケージの材質は問わない。It may be fixed to a socket, and the material of the package does not matter as long as the chip carrier type semiconductor device that is the upper package is a chip carrier type.
更に、リード間の接続を十分にするためには上下パッケ
ージのリードの接触部には導電接着剤を塗布するように
しても良い。Furthermore, in order to ensure sufficient connection between the leads, a conductive adhesive may be applied to the contact portions of the leads of the upper and lower packages.
なお、本発明は上記実施例に限定されるものではなく、
本発明の趣旨に従い種々の変形が可能であり、それらを
本発明の範囲から排除するものではない。Note that the present invention is not limited to the above embodiments,
Various modifications are possible according to the spirit of the present invention, and these are not excluded from the scope of the present invention.
（発明の効果）
以上、詳細に説明したように、本発明によれば、複数の
パッケージを積み重ねて構成される半導体装置において
、下部パッケージのリードを折曲し、下方の基板に接触
させる部分を形成すると共に上方には上部パッケージを
挟持し得る立ち上がり部分を形成するようにしたので、
半導体装置を容易にしかも正確に積み重ねることができ
、半導体装置の機能の向上を迅速、かつ的確に行うこと
ができる。また、上部パッケージを取り外して機能の再
編成を行うことも簡単である。また、リード形状も、バ
ラエティに冨んでおり、それらの形状のうち適宜選択す
ることができる。更に下部パッケージのリードの立ち上
がり部分の途中に段部を設けることにより、上部パッケ
ージのＸ、Ｙ、θ方向の位置決めを正確に行うことがで
きると共に上部パッケージと下部パッケージのリード間
の接続を良好ならしめることができる。(Effects of the Invention) As described in detail above, according to the present invention, in a semiconductor device configured by stacking a plurality of packages, the leads of the lower package are bent and the portion that contacts the lower substrate is bent. At the same time, a rising portion is formed above which can hold the upper package.
Semiconductor devices can be stacked easily and accurately, and the functions of semiconductor devices can be quickly and accurately improved. It is also easy to remove the upper package and reorganize functions. Further, there is a wide variety of lead shapes, and an appropriate one can be selected from among these shapes. Furthermore, by providing a step part in the middle of the rising part of the leads of the lower package, it is possible to accurately position the upper package in the X, Y, and θ directions, and to ensure a good connection between the leads of the upper and lower packages. It can be tightened.
このように本発明は種々の利点を有し、その効果は顕著
である。As described above, the present invention has various advantages, and its effects are remarkable.
第１図は本発明に係る積み重ね型半導体装置の説明図、
第２図は多端子対応積み重ね型半導体装置の説明図、第
３図は本発明の第３の実施例を示す積み重ね型半導体装
置の説明図、第４図は従来の積み重ね型半導体装置の断
面図、第５図は従来の他の積み重ね型半導体装置の説明
図、第６図は本発明の第４の実施例を示す積み重ね型半
導体装置の断面図、第７図は本発明の第５の実施例を示
す積み重ね型半導体装置の説明図１、第８図は本発明の
第６の実施例を示す積み重ね型半導体装置の断面図であ
る。
１３．２０．２７．３３・・・下部パッケージ、１５．
２１．２５．２９．３５．３９・・・下部パッケージの
リード、１５−１．２５−１．２９−２．３５−３．３
９−３・・・下部パンケージのリード立ち上がり部、２
５−４．３９−４・・・同リードの立ち上がり部の段部
、１６．２２．３０．３６・・・上部パッケージ、１８
．２４．２６．３２．３８・・・上部パッケージのリー
ド。FIG. 1 is an explanatory diagram of a stacked semiconductor device according to the present invention;
FIG. 2 is an explanatory diagram of a multi-terminal stacked semiconductor device, FIG. 3 is an explanatory diagram of a stacked semiconductor device showing a third embodiment of the present invention, and FIG. 4 is a sectional view of a conventional stacked semiconductor device. , FIG. 5 is an explanatory diagram of another conventional stacked semiconductor device, FIG. 6 is a sectional view of a stacked semiconductor device showing a fourth embodiment of the present invention, and FIG. 7 is a fifth embodiment of the present invention. Explanation of a stacked semiconductor device showing an example FIGS. 1 and 8 are cross-sectional views of a stacked semiconductor device showing a sixth embodiment of the present invention. 13.20.27.33...lower package, 15.
21.25.29.35.39... Lower package lead, 15-1.25-1.29-2.35-3.3
9-3... Lower pancage lead rising part, 2
5-4.39-4...Step part of the rising part of the same lead, 16.22.30.36...Upper package, 18
．． 24.26.32.38...Leads of upper package.
Claims (3)
装置において、下部パッケージのリードを折曲し、下方
の基板に接触させる部分を形成すると共に上方には上部
パッケージを挟持し得る立ち上がり部分を形成するよう
にしたことを特徴とする半導体装置。(1) In a semiconductor device configured by stacking a plurality of packages, the leads of the lower package are bent to form a portion that contacts the lower substrate and a rising portion that can hold the upper package at the top. A semiconductor device characterized by:
止する段部を形成したことを特徴とする特許請求の範囲
第１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein a step portion for locking the upper package is formed in the rising portion.
記上部パッケージはチップキャリア型半導体装置から成
るようにしたことを特徴とする特許請求の範囲第１項記
載の半導体装置。(3) The semiconductor device according to claim 1, wherein the lower package is a flat type semiconductor device, and the upper package is a chip carrier type semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60061804A JPS6216552A (en) | 1985-03-28 | 1985-03-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60061804A JPS6216552A (en) | 1985-03-28 | 1985-03-28 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6216552A true JPS6216552A (en) | 1987-01-24 |
Family
ID=13181642
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60061804A Pending JPS6216552A (en) | 1985-03-28 | 1985-03-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6216552A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5055912A (en) * | 1990-05-18 | 1991-10-08 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| US5508563A (en) * | 1991-03-13 | 1996-04-16 | Kabushiki Kaisha Toshiba | Semiconductor assembly having laminated semiconductor devices |
| KR100462993B1 (en) * | 2002-03-11 | 2004-12-23 | 최영인 | Manufacturing method and device of stacking IC package |
| CN109699191A (en) * | 2017-07-14 | 2019-04-30 | 新电元工业株式会社 | Electronic module |
-
1985
- 1985-03-28 JP JP60061804A patent/JPS6216552A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5055912A (en) * | 1990-05-18 | 1991-10-08 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| JPH0423460A (en) * | 1990-05-18 | 1992-01-27 | Mitsubishi Electric Corp | Semiconductor device |
| US5508563A (en) * | 1991-03-13 | 1996-04-16 | Kabushiki Kaisha Toshiba | Semiconductor assembly having laminated semiconductor devices |
| KR100462993B1 (en) * | 2002-03-11 | 2004-12-23 | 최영인 | Manufacturing method and device of stacking IC package |
| CN109699191A (en) * | 2017-07-14 | 2019-04-30 | 新电元工业株式会社 | Electronic module |
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