JPS62163945U - - Google Patents

Info

Publication number
JPS62163945U
JPS62163945U JP1986052711U JP5271186U JPS62163945U JP S62163945 U JPS62163945 U JP S62163945U JP 1986052711 U JP1986052711 U JP 1986052711U JP 5271186 U JP5271186 U JP 5271186U JP S62163945 U JPS62163945 U JP S62163945U
Authority
JP
Japan
Prior art keywords
substrate
metal layer
protruding electrode
bonded
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1986052711U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986052711U priority Critical patent/JPS62163945U/ja
Publication of JPS62163945U publication Critical patent/JPS62163945U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81193Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図は本考案の一実施例の実装工程
を順次示す側断面図、第3図、第4図は従来の実
装工程を順次示す側面図である。 1:半導体素子、2:基板、4:金属層、6:
突起状電極、7:くぼみ。
1 and 2 are side sectional views sequentially showing the mounting process of an embodiment of the present invention, and FIGS. 3 and 4 are side views sequentially showing the conventional mounting process. 1: semiconductor element, 2: substrate, 4: metal layer, 6:
Protruding electrode, 7: recess.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体素子の突起状電極が基板の一面に設けら
れたくぼみ内面に被着された金属層に圧着された
ことを特徴とする半導体装置。
A semiconductor device characterized in that a protruding electrode of a semiconductor element is pressure-bonded to a metal layer coated on the inner surface of a recess provided on one surface of a substrate.
JP1986052711U 1986-04-08 1986-04-08 Pending JPS62163945U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986052711U JPS62163945U (en) 1986-04-08 1986-04-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986052711U JPS62163945U (en) 1986-04-08 1986-04-08

Publications (1)

Publication Number Publication Date
JPS62163945U true JPS62163945U (en) 1987-10-17

Family

ID=30878118

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986052711U Pending JPS62163945U (en) 1986-04-08 1986-04-08

Country Status (1)

Country Link
JP (1) JPS62163945U (en)

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