JPS62162762U - - Google Patents
Info
- Publication number
- JPS62162762U JPS62162762U JP5091586U JP5091586U JPS62162762U JP S62162762 U JPS62162762 U JP S62162762U JP 5091586 U JP5091586 U JP 5091586U JP 5091586 U JP5091586 U JP 5091586U JP S62162762 U JPS62162762 U JP S62162762U
- Authority
- JP
- Japan
- Prior art keywords
- coloring
- circuit
- memory
- line buffer
- display pixel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004040 coloring Methods 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 4
- 238000001514 detection method Methods 0.000 description 1
Landscapes
- Image Generation (AREA)
Description
第１図は本考案の実施例を示すブロツク図、第
２図は本考案実施例のタイミング図、第３図は映
像表示例を示す図、第４図は従来例を示すブロツ
ク図。
７，７′：ラインバツフアメモリ、８：ライト
アドレスカウンタ、９：リードアドレスカウンタ
、１０：アドレスセレクタ、１１：ライトメモリ
アドレスセレクタ、１２：エツジデータメモリ、
１３：ライトマークメモリ、１４：ライトマーク
検出回路。
FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing diagram of the embodiment of the present invention, FIG. 3 is a diagram showing an example of video display, and FIG. 4 is a block diagram showing a conventional example. 7, 7': Line buffer memory, 8: Write address counter, 9: Read address counter, 10: Address selector, 11: Write memory address selector, 12: Edge data memory,
13: Light mark memory, 14: Light mark detection circuit.
Claims (1)
表示画素クロツクに同期したタイミングでぬりつ
ぶし回路へ出力するラインバツフアメモリ回路と
、ラインバツフアメモリの出力データをもとにぬ
りつぶし処理を行なうぬりつぶし回路において、
独立したエツジデータメモリとライトマークメモ
リを有し、表示画素クロツクへの同期とぬりつぶ
し処理を同時に行なうことを特徴とする映像発生
装置。 In the line buffer memory circuit that outputs edge data sorted in the horizontal direction to the coloring circuit in synchronization with the display pixel clock, and in the coloring circuit that performs coloring processing based on the output data of the line buffer memory,
1. A video generating device characterized in that it has independent edge data memory and write mark memory, and performs synchronization with a display pixel clock and fill-in processing at the same time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5091586U JPS62162762U (en) | 1986-04-07 | 1986-04-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5091586U JPS62162762U (en) | 1986-04-07 | 1986-04-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62162762U true JPS62162762U (en) | 1987-10-16 |
Family
ID=30874709
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5091586U Pending JPS62162762U (en) | 1986-04-07 | 1986-04-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62162762U (en) |
-
1986
- 1986-04-07 JP JP5091586U patent/JPS62162762U/ja active Pending
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