JPS6216036Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a muting circuit for an FM stereo receiver.

The muting circuit of the FM stereo receiver is
This is to cut out unpleasant noise (random noise) when selecting a channel on an FM stereo receiver. Also, the muting signal from the FMIF IC is detected from the detection curve (S curve). In other words, the S curve is at the perfect tuning point (fo) as shown in Figure 2.
A direct current (DC) voltage is generated that is proportional to the deviation (Δ) of the local oscillation frequency from the local oscillation frequency. It detects that DC voltage and issues a muting signal. Conventionally, the IF and detection IC and
Muting is applied to the demodulated signal (MPXout) of the FM stereo demodulation circuit. However, with this method, muting is suddenly applied when the peak voltage of the S curve is reached, so there is a risk that large noise will occur in the output of the FM stereo demodulation circuit.

Therefore, in the circuit of the present invention, the timing at which muting is applied to the detection output signal from the FM detection circuit and the demodulated signal from the stereo demodulation circuit is delayed from the time at which the muting signal is output. An embodiment of the present invention will be described below with reference to FIGS. 1 to 4.

(IC ₁ ) is an FMIF amplification and detection IC, and the detection method is quadrature. As such an FMIF amplification and detection IC, for example, HA11225 manufactured by Hitachi, Ltd. is known.

IC ₂ is an FM stereo demodulation IC. The muting signal of IC ₁ is detected from the detection curve (S curve) in Figure 2, and as shown in Figure 3, it is detected at the time of tuning.
0V, 5V when detuned. Also, the tuning bandwidth is approximately ±
It is 70kHz. S ₁ is a manual switch for FM muting, and when S ₁ is turned on, the muting signal from output terminal 4 of the muting signal generation circuit built in IC ₁ is sent to IC ₁ via R ₁ .
Detection output is applied to STOP terminal 1. When approximately 1.2V is applied to the detection output STOP terminal 1 of IC ₁ , muting is applied to the detection output signal. _R2 is a resistor for discharging _C1 and for dividing the muting voltage. On the other hand, the muting signal from IC ₁ passes through S ₁ and is also connected to the base of Q ₁ via R _{3 .}
When the base of Q ₁ becomes high level and turns on, the base of Q ₂ is biased by the voltage division ratio of R ₅ and R ₄ , and Q ₂ turns on. When Q ₂ turns ON, the collector of Q ₂ becomes high level, and the voltage VA at point A is 1.2V lower than the voltage divided by R ₆ and R ₇ by the forward voltage of D ₁ (varistor). Get out. Due to this voltage VA, the bases of Q ₃ and Q ₄ go to high level through R ₈ and R ₉ , respectively, and Q ₃
and Q ₄ is in the ON state. The stereo demodulated signal from IC ₂ is connected to the collectors of Q ₃ and Q ₄ , and when Q ₃ and Q ₄ are turned on, it is grounded and the output is cut off.

By the way, the voltage VA at point A is determined by the time constants of R ₆ and C ₂ and the voltage shift of D ₁ that constitute the first delay circuit 2 when the muting signal of IC ₁ is generated as shown in FIG. 5 (FIG. 5 a). (see Fig. 5b) becomes high level after a time delay of _T1 (see Fig. 5b).

In other words, when the voltage of the S curve passes the peak point and before random noise RN appears, VA becomes high level, and the bases of Q ₃ and Q ₄ are brought to high level via R ₈ and R ₉ , and Q ₃ , Turn on each Q ₄ and apply muting to the demodulated signal from the FM stereo demodulation circuit IC ₂ . On the other hand, at the STOP terminal 1 of IC ₁ , the muting signal of IC ₁ becomes high level with a delay from the time when the muting signal of IC ₁ is output due to the time constant of R ₁ and C ₁ .

The timing to apply mutating is
First, it is applied to the demodulated signal from IC ₂ , and then it is applied to the IF IC.
(IC ₁ ) is applied to the AC component (stereo composite signal) of the detection output. Therefore, the DC voltage at the detection output when muting is applied is shown in Figure 2 V _B
As shown in , it is very small and can suppress noise when detuning.

In the circuit shown in Figure 1, a resistor is also connected to the STOP terminal 1 of the IF IC (IC ₁ ) from the time the muting signal is generated.
A STOP signal is applied after a delay time by the second delay circuit 3 composed of _R1 and capacitor _C1 , and the IF
Since the detection output signal (stereo composite signal) from the IC (IC ₁ ) is muted,
Noise can be further reduced.

That is, the mutating signal from IC ₁ delayed by the time T ₁ in the first delay circuit 2 outputs Q ₃ and Q ₄ .
When turned on and mutating the demodulated signal from IC ₂ , the noise can be reduced by about 60 dB due to the characteristics of Q ₃ and Q ₄ , but since it is not completely muted, noise still exists in the demodulated signal line. . In addition, when the tuning operation progresses in this state and the state becomes detuned, the FM detection circuit outputs a detection output with random noise superimposed on it, so this random noise may appear on the demodulation signal line and cause audible problems. There is.

Therefore, after mutating the demodulated signal as in the present application, the detection output itself is transmitted by the second delay circuit 3 using the muting signal from IC ₁ (see FIG. 5c) delayed by a time T ₂ longer than the time T ₁ . By mutating, it is possible to suppress the noise superimposed on the detection output, thereby reliably removing the noise on the demodulation signal line, and for example, it is possible to reduce the noise by about 80 dB. Therefore, the circuit of FIG. 1 is particularly effective for use in high-output receivers.

As described above, according to the muting circuit of the FM stereo receiver according to the present invention, the DC voltage generated by the FM detection circuit is detected in proportion to the deviation from the perfect tuning point, and this DC voltage is the maximum peak voltage. In an FM stereo receiver equipped with a muting signal generating circuit that generates a muting signal when the mutating signal reaches the vicinity, a first delay circuit that delays the mutating signal for a first predetermined time; a second delay circuit that delays the muting signal by a second predetermined time that is larger than the first predetermined time; operating a demodulated signal muting switching element for muting the demodulated signal from the FM stereo demodulation circuit, and at the output of the second delay circuit, which is generated after a second predetermined time delay after the muting signal is generated; Since the detection output signal from the FM detection circuit is muted, it is possible not only to prevent noise from occurring at the start of the muting operation, but also to achieve muting with a large noise reduction level, and to use the automatic tuning function. Suitable for use in FM stereo receivers equipped with

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing the muting circuit of the FM stereo receiver according to the present invention, Fig. 2 is a characteristic diagram of the FM detection output, Fig. 3 is a diagram showing the relationship between the muting signal and the detuning frequency, and Fig. 4 is a diagram showing the relationship between the muting signal and the detuning frequency. 5 is a diagram showing the relationship between the driving voltage of the switching transistor for mutating and the detuning frequency, FIG. 5 is a diagram used to explain the muting operation according to the present invention, and FIG. FIG. 5B is a diagram showing an output signal from the first delay circuit, and FIG. 1C is a diagram showing an output signal from the second delay circuit. 2...first delay circuit, 3...second delay circuit,
IC ₁ ...IC for IF and detection, IC ₂ ...IC for FM stereo demodulation.

Claims (1)

[Scope of utility model registration request] FM stereo equipped with a muting signal generation circuit that detects the DC voltage generated by the FM detection circuit in proportion to the deviation from the perfect tuning point, and generates a muting signal when this DC voltage reaches near the maximum peak voltage. In the receiver, a first
and a second delay circuit for delaying the mutating signal for a second predetermined time that is larger than the first predetermined time, the mutating signal is generated a first predetermined time later than the first predetermined time. operating a demodulated signal muting switching element for muting the demodulated signal from the FM stereo demodulation circuit at the output of the first delay circuit, and generates a second predetermined time delay after the muting signal is generated. Said second
A muting circuit for an FM stereo receiver, characterized in that the detection output signal from the FM detection circuit is muted at the output of the delay circuit.