JPS6216037Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a muting circuit for an FM receiver.

The FM receiver's muting circuit cuts out unpleasant noise (random noise) when the FM receiver selects a channel. Also, the muting signal from the FMIF IC is detected from the detection curve (S curve). In other words, the S curve produces a direct current (DC) voltage proportional to the deviation (Δ) of the local oscillation frequency from the perfect tuning point f ₀ as shown in FIG. It detects that DC voltage and issues a muting signal. Conventionally, the moment the muting signal is output, muting is applied to the output signal (MPXout) of the IF IC and FM stereo demodulation circuit.
However, with this method, muting is suddenly applied when the peak voltage of the S curve is reached, so there is a risk that large noise will occur in the output of the FM stereo demodulation circuit.

Therefore, in the circuit of the present invention, the timing at which muting is applied to the low frequency signal is delayed from the point at which the muting signal is output. An embodiment of the present invention will be described below with reference to FIGS. 1 to 4.

IC ₁ is an FMIF amplification and detection IC, and the detection method is quadrature. Such FMIF amplification and detection ICs include, for example, those manufactured by Hitachi, Ltd.
HA11225 is known. IC ₂ is an FM stereo demodulation IC. The muting signal of IC ₁ is detected from the detection curve (S curve) in Figure 2, and
As shown in the figure, the voltage is 0V when tuned and 5V when detuned.
Also, the tuning bandwidth is approximately ±70kHz. S ₁ is a manual switch for FM muting, and S ₁ is ON.
Then, one of the muting signals from the output terminal 4 of the muting signal generation circuit built in IC ₁ is applied to the IFSTOP terminal 1 of IC ₁ via R ₁ . When approximately 1.2V is applied to IFSTOP terminal 1 of IC ₁ , muting is applied to IC ₁ . _R2 is a resistor for discharging _C1 and for dividing the muting voltage. On the other hand, the muting signal from IC ₁ is also connected to the base of Q ₁ via R ₃ after passing through S ₁ .
When the base of Q ₁ becomes high level and Q ₁ turns ON, the base of Q ₂ is biased by the voltage division ratio of R ₅ and R ₄ , and Q ₂ turns ON. When Q ₂ turns ON, the collector of Q ₂ becomes high level, and
At point A, there is a voltage divided by R ₆ and R ₇ .
A voltage VA that is 1.2V lower by the forward voltage of _D1 varistor is output. This voltage VA causes the bases of the muting switching transistors Q ₃ and Q ₄ to go high through R ₈ and R ₉ , respectively, and _the
Q4 is in ON state. The low frequency signal from IC ₂ is Q ₃
It is connected to the collector of Q 3 and Q ₄ , and when Q ₃ and Q ₄ are turned on, it falls to ground and the output is cut off.

By the way, due to the time constants of R ₆ and C ₂ and the voltage shift of D ₁ that constitute the first delay circuit 2, the voltage VA at point A is shorter than when the muting signal of IC ₁ is generated by a time T, as shown in FIG. It will reach a high level later. In other words, when the voltage of the S curve passes the peak point and before the random noise RN appears, VA becomes high level, and the bases of Q ₃ and Q ₄ are brought to high level via R ₈ and R ₉ , and Q ₃ and Q ₄ are turned on, respectively, and muting is applied to the low frequency signal from the FM stereo demodulation circuit IC ₂ . On the other hand, IFSTOP pin 1 of IC ₁ has
Similarly, the muting signal of IC ₁ becomes high level with a delay from the time when the muting signal of IC ₁ is output due to the time constants of R ₁ and C ₁ .

The timing to apply mutating is
First, it is applied to the low frequency signal from IC ₂ , and then it is applied to the IF IC.
(IC ₁ ). Therefore, the DC voltage at the detection output when muting is applied is very small, as shown by V _B in FIG. 2, and noise at detuning can be suppressed.

By the way, if you apply muting at the timing as proposed in this application, the FM
There is a risk that noise due to changes in the DC voltage output from the detector circuit may occur in the low-frequency signal line, but the range of change in DC voltage caused by such tuning operations is minute and does not cause any audible problem. .

In the circuit shown in Figure 1, a resistor is also connected to the STOP terminal 1 of the IF IC (IC ₁ ) from the time the muting signal is generated.
A STOP signal is applied after a delay time by the second delay circuit 3 composed of _R1 and capacitor _C1 , and the IF
Since the IC (IC ₁ ) is disabled, noise can be further reduced. For example, if muting is applied only to the low frequency signal from IC ₂ , the noise can only be reduced by 60 dB, whereas if muting is applied to the IF IC (IC ₁ ) as well, the noise can be reduced by 80 dB. You can. Therefore, the circuit of FIG. 1 is particularly effective for use in high-output receivers.

Although Fig. 1 shows an example of use in an FM stereo receiver, the present invention is not limited to such an embodiment.
It goes without saying that it may be used in a monaural receiver.

As described above, according to the muting circuit of the FM receiver according to the present invention, the DC voltage output from the FM detection circuit is detected in proportion to the deviation from the perfect tuning point, and this DC voltage is near the maximum peak voltage. In an FM receiver equipped with a muting signal generation circuit that generates a muting signal when the
A delay circuit for delaying the muting signal for a predetermined period of time, and a low frequency signal muting switching element connected to the low frequency signal line and for mutating the low frequency signal during operation are provided, and the muting signal is generated. Since the switching element for low frequency signal muting is driven by the output of the delay circuit which is generated after a predetermined time delay from This can be prevented from occurring and is suitable for use in FM receivers equipped with an automatic tuning function.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing the muting circuit of the FM receiver according to the present invention, Figure 2 is a characteristic diagram of the FM detection output, Figure 3 is a diagram showing the relationship between the muting signal and the detuning frequency, and Figure 4. 2 is a diagram showing the relationship between the driving voltage of the muting switching transistor and the detuning frequency. FIG. 4... Output terminal of the muting signal generation circuit, 2... Delay circuit.

Claims (1)

[Scope of utility model registration request] An FM receiver equipped with a muting signal generation circuit that detects the DC voltage output from the FM detection circuit in proportion to the deviation from the perfect tuning point and generates a muting signal when this DC voltage reaches near the maximum peak voltage. A delay circuit for delaying the mutating signal for a predetermined period of time, and a low frequency signal muting switching element connected to the low frequency signal line and for mutating the low frequency signal during operation are provided, and the muting signal is A muting circuit for an FM receiver, characterized in that the switching element for low frequency signal muting is driven by the output of the delay circuit which is generated after a predetermined time delay after the occurrence of the low frequency signal.