JPS6138271Y2 - - Google Patents
Info
- Publication number
- JPS6138271Y2 JPS6138271Y2 JP11573179U JP11573179U JPS6138271Y2 JP S6138271 Y2 JPS6138271 Y2 JP S6138271Y2 JP 11573179 U JP11573179 U JP 11573179U JP 11573179 U JP11573179 U JP 11573179U JP S6138271 Y2 JPS6138271 Y2 JP S6138271Y2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- gain control
- automatic gain
- tuner
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000003321 amplification Effects 0.000 claims description 12
- 238000001514 detection method Methods 0.000 claims description 12
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 12
- 238000009499 grossing Methods 0.000 claims description 10
- 239000003990 capacitor Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
Landscapes
- Amplifiers (AREA)
- Control Of Amplification And Gain Control (AREA)
Description
【考案の詳細な説明】
本考案は、アンテナ入力の大きさに応じて高周
波増幅段の利得を制御するチユーナの自動利得制
御回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic gain control circuit for a tuner that controls the gain of a high frequency amplification stage according to the magnitude of an antenna input.
チユーナの自動利得制御回路は検波出力の交流
信号の一部を取り出して平滑化して自動利得制御
電圧として得て高周波増幅段の利得を制御してい
る。しかしこの平滑回路の時定数による自動利得
制御電圧の遅延時間のためにポツプノイズが発生
する。そこでポツプノイズを防止するために第１
図に示す如く構成したチユーナの自動利得制御回
路がある。この回路はチユーナ１の検波出力の一
部を取り出して平滑して得られた直流電圧を高周
波増幅段の制御端子１ｂにその利得を制御するた
めの自動利得制御電圧として供給する平滑回路２
と、上記検波出力のレベルが所定値以上になつた
とき導通して上記制御端子１ｂに信号を供給して
上記高周波増幅段の利得を低下させるように上記
平滑回路２の両端間にダイオード３を接続したも
のである。なお第１図において１はチユーナで、
高周波増幅段、周波数変換回路、中間周波増幅段
および検波回路を含んでおり、検波出力はチユー
ナの出力端子１ａから取り出されて抵抗R1とコ
ンデンサC1とからなるフイルタを通して低周波
増幅回路に供給される。 The automatic gain control circuit of the tuner takes out a part of the AC signal of the detection output, smoothes it, obtains it as an automatic gain control voltage, and controls the gain of the high frequency amplification stage. However, pop noise occurs due to the delay time of the automatic gain control voltage due to the time constant of this smoothing circuit. Therefore, in order to prevent pop noise,
There is an automatic gain control circuit for a tuner constructed as shown in the figure. This circuit takes out a part of the detected output of the tuner 1, smoothes it, and supplies the obtained DC voltage to the control terminal 1b of the high frequency amplification stage as an automatic gain control voltage for controlling the gain of the smoothing circuit 2.
A diode 3 is connected between both ends of the smoothing circuit 2 so that when the level of the detection output exceeds a predetermined value, it becomes conductive and supplies a signal to the control terminal 1b to reduce the gain of the high frequency amplification stage. It is connected. In Figure 1, 1 is Chuyuna,
It includes a high frequency amplification stage, a frequency conversion circuit, an intermediate frequency amplification stage and a detection circuit, and the detection output is taken out from the output terminal 1a of the tuner and supplied to the low frequency amplification circuit through a filter consisting of a resistor R1 and a capacitor C1 . be done.
しかし上記の如きダイオード３を接続したチユ
ーナの自動利得制御回路においては、ダイオード
３によりコンデンサOC3を瞬時に充電するために
出力が一定値となるまでの時間は短かくなるが、
まだ第２図に示す如くポツプノイズが残る欠点が
あつた。第２図において直線Ａはダイオード３の
順方向電圧を、実線Ｂは自動利得制御電圧を、実
線Ｃは出力交流電圧を示している。 However, in the automatic gain control circuit of the tuner connected to the diode 3 as described above, since the diode 3 instantly charges the capacitor OC 3 , the time it takes for the output to reach a constant value is shortened.
There was still a drawback that pop noise remained as shown in Figure 2. In FIG. 2, straight line A shows the forward voltage of the diode 3, solid line B shows the automatic gain control voltage, and solid line C shows the output AC voltage.
そこで本考案は上記にかんがみなされたもの
で、上記の欠点を解消したチユーナの自動利得制
御回路を提供することを目的とするものであつ
て、以下本考案を実施例により説明する。 The present invention has been made in view of the above, and aims to provide an automatic gain control circuit for a tuner that eliminates the above-mentioned drawbacks.The present invention will be described below with reference to embodiments.
第３図は本考案の一実施例の回路図である。 FIG. 3 is a circuit diagram of an embodiment of the present invention.
第３図において１はチユーナであり、高周波増
幅段、周波数変換回路、中間周波増幅段および検
波回路を含んでおり、１ａはチユーナの検波出力
端子であり、１ｂは高周波増幅段の自動利得制御
電圧の入力端子である。検波回路の出力は出力端
子１ａから取り出され抵抗R1とコンデンサC1か
らなるフイルタを通つて低周波増幅段に供給され
る。 In Fig. 3, 1 is a tuner, which includes a high frequency amplification stage, a frequency conversion circuit, an intermediate frequency amplification stage, and a detection circuit, 1a is a detection output terminal of the tuner, and 1b is an automatic gain control voltage of the high frequency amplification stage. This is the input terminal of The output of the detection circuit is taken out from the output terminal 1a and is supplied to the low frequency amplification stage through a filter consisting of a resistor R1 and a capacitor C1 .
また、検波回路の出力端子１ａから抵抗R2，
R3、コンデンサC2，C3より成る平滑回路２を通
して検波回路の出力電圧の一部を平滑化して自動
利得制御電圧として端子１ｂに供給するととも
に、抵抗R1を通して検波出力となる点より端子
１ｂに向けて流れる電流に対して順方向となるよ
うに、抵抗R1の出力端１ｃと端子１ｂとの間に
ダイオード４を接続する。 Also, from the output terminal 1a of the detection circuit, a resistor R 2 ,
A part of the output voltage of the detection circuit is smoothed through a smoothing circuit 2 consisting of R 3 , capacitors C 2 and C 3 and supplied to the terminal 1b as an automatic gain control voltage. A diode 4 is connected between the output terminal 1c of the resistor R1 and the terminal 1b so that the current flows in the forward direction toward the terminal 1b.
そこで、平常動作時は検波出力電圧値はダイオ
ード４を導通状態にする電圧より低く設定されて
いるため、出力端子１ａの電圧は平滑回路２によ
り平滑されて自動利得制御電圧となり、通常に自
動利得制御回路として動作している。 Therefore, during normal operation, the detection output voltage value is set lower than the voltage that makes the diode 4 conductive, so the voltage at the output terminal 1a is smoothed by the smoothing circuit 2 to become an automatic gain control voltage, and the automatic gain control voltage is normally set to It operates as a control circuit.
いまたとえば同調操作時、同調点に近ずくに従
つて出力端１ｃの電圧は増大し、平滑回路２の時
定数により定まる遅延時間をもつて出力電圧を一
定にしようとする自動利得制御作用が働く。いま
出力端１ｃの電圧がダイオード４の順方向電圧を
超えるとダイオード４は導通状態となり、抵抗
R1とダイオード４とコンデンサC3によるクリツ
プ回路が動作し出力端１ｃの電圧がクリツプされ
る。同時にコンデンサC3を瞬時に充電し、自動
利得制御動作を早める。 For example, during a tuning operation, the voltage at the output terminal 1c increases as it approaches the tuning point, and an automatic gain control action is activated to keep the output voltage constant with a delay time determined by the time constant of the smoothing circuit 2. . Now, when the voltage at the output terminal 1c exceeds the forward voltage of the diode 4, the diode 4 becomes conductive, and the resistance
A clip circuit consisting of R1 , diode 4, and capacitor C3 operates, and the voltage at output terminal 1c is clipped. At the same time, it instantly charges capacitor C3 and speeds up automatic gain control operation.
この様子は第４図に示す如くで、第４図におい
て直線Ａはダイオード４の順方向電圧を示してお
り、出力端１ｃの出力交流電圧Ｂは直線Ａに示し
たダイオード４の順方向電圧でクリツプされ、こ
のクリツプ効果により出力電圧の一定化が行われ
る。なお第４図において実線Ｃは出力直流電圧を
示している。 This situation is as shown in Fig. 4. In Fig. 4, the straight line A shows the forward voltage of the diode 4, and the output AC voltage B at the output terminal 1c is the forward voltage of the diode 4 shown in the straight line A. This clipping effect stabilizes the output voltage. In addition, in FIG. 4, the solid line C indicates the output DC voltage.
以上説明した如く本考案によれば、チユーナの
同調、離調時のポツプノイズが従来より更に少な
くなり、特に離調時にミユーテング動作をさせな
い形のチユーナに最適である。 As explained above, according to the present invention, the pop noise when the tuner is tuned or detuned is further reduced than the conventional one, and it is particularly suitable for a tuner that does not perform a muting operation when the tuner is detuned.
第１図および第２図は従来のチユーナの自動利
得制御回路の回路図および出力電圧波形図。第３
図および第４図は本考案の一実施例の回路図およ
び出力電圧波形図。
１……チユーナ、２……平滑回路、４……ダイ
オード。
1 and 2 are a circuit diagram and an output voltage waveform diagram of an automatic gain control circuit of a conventional tuner. Third
FIG. 4 is a circuit diagram and an output voltage waveform diagram of an embodiment of the present invention. 1... Tuner, 2... Smoothing circuit, 4... Diode.
Claims (1)
接続してこのインピーダンス回路の出力端から出
力を得るようにし、前記チユーナの検波出力の一
部を取り出して平滑しこの平滑して得た直流電圧
を高周波増幅段の自動利得制御電圧入力端子に印
加する平滑回路と、前記インピーダンス回路の出
力端と前記自動利得制御電圧入力端子との間に前
記インピーダンス回路の出力端から前記自動利得
制御電圧入力端子の方向を順方向として接続した
ダイオードとを備えたことを特徴とするチユーナ
の自動利得制御回路。 An impedance circuit is connected to the detection output terminal of the tuner so that the output is obtained from the output terminal of the impedance circuit, a part of the detection output of the tuner is taken out and smoothed, and the DC voltage obtained by this smoothing is sent to the high frequency amplification stage. a smoothing circuit applied to the automatic gain control voltage input terminal of the impedance circuit, and a smoothing circuit applied to the automatic gain control voltage input terminal between the output terminal of the impedance circuit and the automatic gain control voltage input terminal. An automatic gain control circuit for a tuner, comprising a diode connected as a direction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11573179U JPS6138271Y2 (en) | 1979-08-24 | 1979-08-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11573179U JPS6138271Y2 (en) | 1979-08-24 | 1979-08-24 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5633815U JPS5633815U (en) | 1981-04-02 |
| JPS6138271Y2 true JPS6138271Y2 (en) | 1986-11-05 |
Family
ID=29347964
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11573179U Expired JPS6138271Y2 (en) | 1979-08-24 | 1979-08-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6138271Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6363208A (en) * | 1986-09-03 | 1988-03-19 | Fujitsu Ten Ltd | Am receiver |
-
1979
- 1979-08-24 JP JP11573179U patent/JPS6138271Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5633815U (en) | 1981-04-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6221453B2 (en) | ||
| JPH0117855Y2 (en) | ||
| JPH0152930B2 (en) | ||
| CA1278053C (en) | Filter adjustment apparatus and method | |
| US6333765B1 (en) | Television receiver having an AGC circuit to control the gain on a tuner | |
| JPS6138271Y2 (en) | ||
| JPH09181632A (en) | Delayed automatic gain control circuit | |
| JPH054334Y2 (en) | ||
| JPS6127714B2 (en) | ||
| US4806876A (en) | High frequency amplifier circuit | |
| US4289981A (en) | Pulsive component detecting apparatus | |
| JP3213495B2 (en) | Noise removal circuit | |
| JPS632364B2 (en) | ||
| JPS6327479Y2 (en) | ||
| JPS6143301Y2 (en) | ||
| KR800001064Y1 (en) | Automatic gain control circuit | |
| JPH0510419Y2 (en) | ||
| JPS6228094Y2 (en) | ||
| JPS5837135Y2 (en) | Muting signal generation circuit | |
| KR960003837B1 (en) | Receiver | |
| JPS6230351Y2 (en) | ||
| JPH0314814Y2 (en) | ||
| JPS6348978Y2 (en) | ||
| JPS6143300Y2 (en) | ||
| JPH0215414Y2 (en) |