JP2943165B2 - Clamp circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a clamp circuit used for video signal processing and the like.

2. Description of the Related Art In recent years, satellite broadcasting has been started in each home to receive radio waves directly from satellites. The power concentrated on the pedestal level and the synchronization signal level by superimposing a triangular energy spread signal synchronized with the frame period on the video signal so that the radio wave of this broadcasting satellite does not interfere with the terrestrial radio wave Spreading spectrum.

In the satellite broadcast receiver, this energy spread signal is superimposed on the video signal after FM demodulation and after de-emphasis. To eliminate this, a clamp circuit is used.

FIG. 2 is a circuit diagram showing an example of a conventional clamp circuit. In FIG. 2, 1 is a signal input terminal for inputting a signal, 2 is a capacitor having one end connected to the signal input terminal 1, 3 is a signal output terminal, 4 is a DC power supply, and 5 is a base connected to the DC power supply 4. A transistor whose emitter is connected to the other end of the capacitor 2 and the signal output terminal 3, and 6 is a power supply terminal.

The operation of the clamp circuit configured as described above will be described below.

FIG. 2 shows a generally well-known clamp circuit in which a DC component of an input signal input to a signal input terminal 1 is cut by a capacitor 2. When the difference between the voltage on the side connected to the signal output terminal 3 of the capacitor 2 and the DC power supply 4, that is, the base-emitter voltage of the transistor 5 becomes larger than 0.6 V due to a change in the amplitude of the input signal, the transistor 5 is turned on. , The capacitor 2 is charged, and the DC potential of the negative peak value of the input signal at the signal output terminal 3 is clamped to a voltage lower than the DC power supply 4 by about 0.6 V.

However, in the above configuration, the amplitude of the input signal is directly applied to the emitter of the transistor 5. Therefore, in the case of an excessive input signal such as a signal to which a noise component is added, an excessive reverse voltage is applied between the base and the emitter of the transistor 5, and the transistor 5 is broken or deteriorated, so that a normal clamping operation is not performed. In particular, it has a problem that it is disadvantageous for an IC circuit using a transistor element having a low reverse breakdown voltage as compared with a discrete transistor.

The present invention has been made in view of the above problems, and provides a clamp circuit suitable for an IC circuit.

Means for Solving the Problems In order to solve the above problems, a clamp circuit of the present invention comprises:
A capacitor having one end connected to the signal input terminal and the other end connected to the signal output terminal for cutting a DC component of the input signal;
A fixed bias was supplied to the base from the midpoint of the first and second resistors connected in series between the power supply and the ground, the emitter was connected to the signal output terminal side of the capacitor, and the collector was connected to the power supply. A switching element including a first transistor; and a voltage detector including a second transistor having an emitter, a collector, and a base connected to the base, the collector, and the emitter of the first transistor, respectively. Things.

According to the present invention, the DC voltage of the signal input to the input terminal is cut by the capacitor, and the signal between the fixed bias voltage and the base-emitter voltage of the first transistor is output from the output terminal of the capacitor. The DC voltage having a negative peak value is clamped and output to the difference voltage, and the maximum value of the reverse voltage applied between the base and the emitter of the first transistor is equal to the base-emitter of the second transistor. The voltage difference between the reference voltage and the signal output terminal can be reduced by suppressing the voltage below the intermediate voltage, so that the reverse voltage applied to the switch element in the clamp circuit is reduced, and a normal clamp operation is obtained. Can be

Embodiment Hereinafter, a clamp circuit according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a clamp circuit according to one embodiment of the present invention.

In FIG. 1, the same parts as those in FIG. 2 are denoted by the same reference numerals. FIG. 5 is a first transistor, 7 is a second transistor whose base is connected to the emitter of the first transistor 5 and whose emitter is connected to the base of the first transistor 5, and 8 is one end of the first transistor 5. And the emitter of the second transistor 7
The other end of the resistor is connected to the ground, and 9 is a resistor having one end connected to the resistor 8 and the other end connected to the power supply terminal 6.

The operation of the clamp circuit configured as described above will be described below.

The input signal input to the signal input terminal 1 is a capacitor 2
As a result, the DC component of the input signal is cut. Due to the change in the amplitude of the input signal, the difference between the voltage at the signal output terminal 3 connected to one end of the capacitor 2 and the potential at the connection point of the resistors 8 and 9, that is, the base-emitter voltage of the first transistor 5 becomes When the voltage exceeds 0.6 V, the first transistor 5 is turned on, the capacitor 2 is charged, and the DC potential of the negative peak value of the input signal is changed from the potential at the connection point of the resistors 8 and 9 at the output signal terminal 3. Clamped to a voltage of about 0.6V. Here, when the amplitude of the clamped output signal increases and the value obtained by subtracting the base voltage of the first transistor 5 from the positive peak value exceeds about 0.6 V, the second transistor 7 is turned on. Become. Therefore, in this state, the base voltage of the first transistor 5 fluctuates in conjunction with the peak value of the signal, and the reverse voltage applied between the base and the emitter of the first transistor 5 is reduced by the second transistor 7.
Is fixed at the base-emitter voltage (about 0.6 V).

As described above, according to the present embodiment, the capacitor 2 that cuts the DC component of the signal, the voltage source 6, and the peak value of the input signal are connected to the output terminal 3 side of the capacitor 2 to be in a conductive state. A switching element 5 for applying the potential of the voltage source 6 to the output terminal 3 side, a voltage detector 7 for detecting a voltage at the output terminal 3 side, and the voltage detector 7 based on the detection voltage of the voltage detector. With the provision of the voltage control circuit for controlling the voltage of the source, the reverse voltage applied to the switch element 5 can be fixed to a maximum of about 0.6 V, and a normal clamping operation can be obtained even when the input is excessive. .

Effects of the Invention As described above, according to the present invention, a capacitor that cuts a DC component of a signal, a voltage source, and a peak value of an input signal are connected to an output terminal side of the capacitor to be in a conductive state, A switching element for applying the potential of the voltage source to the output terminal side, a voltage detector for detecting the voltage on the output terminal side, and a voltage for controlling the voltage of the voltage source based on the detection voltage of the voltage detector By including the control circuit, the reverse voltage applied to the switch element can be reduced, and the excessive input signal can be normally clamped by the switch element having a low reverse withstand voltage even at the time of excessive input.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a clamp circuit in one embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional clamp circuit. 2. Capacitor, 5,7 Transistor, 8,9 Resistor.

Claims (1)

(57) [Claims] 1. A capacitor having one end connected to a signal input terminal and the other end connected to a signal output terminal for cutting a DC component of an input signal, and first and second resistors connected in series between a power supply and a ground. A first transistor having a fixed bias supplied to the base from the midpoint, an emitter connected to the signal output terminal of the capacitor, and a collector connected to the power supply; a base, a collector and an emitter of the first transistor A second transistor having an emitter, a collector, and a base connected to each other, wherein a DC component of the signal input to the input terminal is cut by the capacitor and the fixed bias voltage is output from the output terminal of the capacitor. DC voltage having a negative peak value is clamped to the voltage of the difference between the first transistor and the base-emitter voltage of the first transistor. Wherein the maximum value of the reverse voltage applied between the base and the emitter of the first transistor is suppressed to be less than or equal to the voltage between the base and the emitter of the second transistor. .