JPS62158989U - - Google Patents

Description

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of the digital convergence circuit according to this invention, and FIG. 2 is a timing diagram for explaining the operation of the embodiment.
FIG. 3 is a circuit diagram showing the configuration of a conventional digital convergence circuit, and FIG. 4 is a timing diagram for explaining the operation of the conventional circuit. 1...Operation unit, 2...Adjustment point H address generation unit, 3
...H comparator, 4...H address counter, 5...adjustment point V address generator, 6...V comparator, 7...V address counter, 8...timing generator, 9...AND gate, 10...inverter, 11...digital・
Memory, 12... Adder, 13... Latch circuit, 14
...3-state battle.

Claims (1)

[Claims for Utility Model Registration] (1) A digital memory that stores CRT convergence correction data, and an addition or subtraction of the same amount to each of a plurality of correction data when rewriting the correction data stored in this digital memory. and a correction data generation circuit for writing these correction data into the digital memory as new correction data. (2) The utility model registration request is characterized in that the plurality of correction data written in the digital memory is correction data for one line in the horizontal direction, correction data for one line in the vertical direction, or correction data for the entire screen. A digital convergence circuit according to scope 1.