JPS62158564U - - Google Patents

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Publication number
JPS62158564U
JPS62158564U JP1986044820U JP4482086U JPS62158564U JP S62158564 U JPS62158564 U JP S62158564U JP 1986044820 U JP1986044820 U JP 1986044820U JP 4482086 U JP4482086 U JP 4482086U JP S62158564 U JPS62158564 U JP S62158564U
Authority
JP
Japan
Prior art keywords
memory
write
data
written
set number
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1986044820U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986044820U priority Critical patent/JPS62158564U/ja
Publication of JPS62158564U publication Critical patent/JPS62158564U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案のメモリ書き込み禁止回路の一
実施例を示したブロツク図、第2図は第1図に示
した回路の動作波形図である。 1……メモリ、2……CPU、3……カウンタ
、4……リセツト回路、5,6,7……ゲート。
FIG. 1 is a block diagram showing an embodiment of the memory write inhibit circuit of the present invention, and FIG. 2 is an operational waveform diagram of the circuit shown in FIG. 1. 1...Memory, 2...CPU, 3...Counter, 4...Reset circuit, 5, 6, 7...Gate.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] メモリへのデータ書き込み回数を設定する書き
込み回数設定手段と、CPUによるメモリへのデ
ータ書き込み回数をカウントして前記設定回数に
達したことを検出する書き込み回数検出手段と、
メモリへの前記設定回数のデータ書き込みが行な
われるとこれ以上のメモリへのデータ書き込みを
ハード的に不可能とする書き込み禁止手段とを具
備したことを特徴とするメモリ書き込み禁止回路
write count setting means for setting the number of times data is written to the memory; write count detection means for counting the number of times data is written to the memory by the CPU and detecting when the set number of times has been reached;
1. A memory write inhibiting circuit comprising: a write inhibiting means for hardware-wise disabling further data writing to the memory after the set number of data writes to the memory have been performed.
JP1986044820U 1986-03-28 1986-03-28 Pending JPS62158564U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986044820U JPS62158564U (en) 1986-03-28 1986-03-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986044820U JPS62158564U (en) 1986-03-28 1986-03-28

Publications (1)

Publication Number Publication Date
JPS62158564U true JPS62158564U (en) 1987-10-08

Family

ID=30862989

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986044820U Pending JPS62158564U (en) 1986-03-28 1986-03-28

Country Status (1)

Country Link
JP (1) JPS62158564U (en)

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