JPS6215833B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display device for an electronic timepiece that optically displays hands.

When an analog electronic watch is configured by radially arranging the liquid crystal display section that displays the shape of the hands and lighting up the display sections corresponding to the hour and minute hands, etc., there are generally many electrode wirings, and the display surface In this case, the display section is formed over almost the entire surface.

Therefore, it is difficult to add other function displays to the display screen, such as the abbreviated English letters AM and PM indicating morning and afternoon, or a display indicating battery voltage drop.

Therefore, in the present invention, display parts that are lit up in segments in the length direction are arranged radially, and a part of at least one of the display parts corresponding to the hour hand, minute hand, and second hand is used as notification information. The present invention provides a display device for an electronic timepiece that turns on or off depending on the time.

Hereinafter, one embodiment of the present invention will be described based on the drawings.

In FIG. 1, 1 is a crystal oscillator, 2 is a frequency divider, and these constitute a reference pulse generation circuit. 3 and 4 are decimal and hexadecimal counters that measure the seconds digit, respectively, 5 and 6 are decimal and hex counters that measure the minute digit, respectively, and 7 and 8 are the hour digits, respectively. to time
They are a decimal counter and a hexadecimal counter. Each of the above counters produces a binary coded decimal code output. 9
is a hexadecimal counter. The above counter constitutes a timekeeping circuit. Reference numeral 10 denotes a timing pulse generation circuit, which sequentially generates pulses at terminals P ₁ to _{P 3} in response to generation of output pulses from the frequency divider. Reference numerals 11 to 16 constitute a selection circuit, which is a gate circuit having an AND function, and is controlled by pulses sequentially generated at terminals _P1 to _P3 . 17 and 18 are gate circuits having an OR function. Decoders 19 and 20 convert the output codes of the gate circuits 17 and 18, respectively. 21 is an output order switching circuit, and the output order of the decoder 19 is switched according to the state of one output of the gate circuit 18. 22 is a segment potential setting circuit that selects the potential to be applied to the segment electrodes, which will be described in detail later, and 23 is a common potential setting circuit that selects the potential to be applied to the common electrode. The circuits from the gate circuits 17 and 18 to the common potential setting circuit 23 constitute a voltage supply circuit. 24 is a flip-flop circuit, 25 is a potential setting circuit, and terminals S ₀ , S ₁ , C ₀ , C ₁ are set to potentials 0, V ₀ , 2V ₀ and 3V ₀
A predetermined potential is periodically generated. The flip-flop circuit 24 and the potential setting circuit 25 constitute a pulse setting circuit. 26 is an inverter, and 27 is a gate circuit. Reference numeral 28 denotes a flip-flop circuit whose outputs are set to "0" and "1" during the morning and afternoon hours, respectively. Gate circuit 27 and flip-flop circuit 28 constitute a display erasing circuit.

FIGS. 2 and 3 show electrode patterns of a liquid crystal display device that displays hands.

In FIG. 2, numeral 29 indicates an arrangement pattern of segment electrodes having 60 electrodes, and segment electrodes 29a and 29a having 12 electrodes are connected to terminals e ₁ to e ₁₀ of the segment potential setting circuit 22 as shown in the figure. There is. The other segment electrodes have the connection relationships shown below. Note that the order of the segment electrodes is counted clockwise, with the segment electrode 29a connected to the terminal _e1 being the first. 12th
The th segment electrode 29a is the 13th segment electrode 29a, the 11th segment electrode 29a is the 14th segment electrode, and so on.
The 1st is connected to the 24th, the 24th is connected to the 25th, the 23rd is connected to the 26th, and the 13th is connected to the 36th.

Thereafter, segment electrodes up to the 60th are connected in the same relationship as above.

FIG. 3 shows a common electrode arrangement pattern 30 , in which common electrodes 30a and 3 are divided into five parts on the outside and inside.
0a is configured.

Note that each dividing groove 30 of the common electrodes 30a, 30b
c...30c is between the 12th and 13th segment electrodes, between the 24th and 25th segment electrodes, between the 36th and 37th segment electrodes, and between the 48th and 49th segment electrodes in the clockwise direction. It is configured so that it can be located between the 60th and 1st segment electrodes and between the 60th and 1st segment electrodes.

Note that a liquid crystal display device is constituted by an assembly of display parts with liquid crystal interposed between segment electrodes and a common electrode, but the configuration can be easily implemented by a person skilled in the art, and The present invention is not characterized by such a configuration itself, so a description thereof will be omitted.

FIG. 4 is a detailed circuit diagram of the output priority switching circuit 21 and the segment potential setting circuit 22.
45 are gate circuits, 46 to 55 are the same switching circuits as shown in the first diagram, and 56 to 60 are inverters.

FIG. 5 is a detailed circuit diagram of the potential setting circuit 25, in which 61 to 68 are switching circuits and 69 is an inverter.

FIG. 6 is a detailed circuit diagram of the common potential setting circuit 23, in which 70-75 are gate circuits, 76-85 are the same switching circuits as shown in the first diagram, 86-90 are inverters, 91-93 are gate circuits, 94 is an inverter.

In the above configuration, the states of the potential to be applied to the segment electrodes generated at the terminals S ₀ and S ₁ and the potential to be applied to the common electrode generated at the terminals C ₀ and C ₁ in FIG. The voltage between the electrodes will be explained. The set potentials are 0, V ₁ , 2V ₀ and
3V ₀ , and the liquid crystal display device in this example is assumed to be off when the periodic voltage is below |V ₀ |, and to be lit when the voltage is above 3|V ₀ |.

Now, in the fifth illustration, 0 is applied to terminals l ₁ and l ₄ , V _{0 is} applied to terminals l ₂ and l ₇ , 2V ₀ is applied to terminals l ₃ and l ₆ , and 3V ₀ is applied to terminals l ₀ and l ₅ .
A potential of is applied. When "1" is periodically generated at the terminal P1 of the timing pulse generating circuit 10 shown in FIG. ₁ , "1" and "0" are alternately generated at the output Q of the flip-flop circuit 24. As a result, the potentials 3V ₀ and 0 are applied to the terminal S ₀ shown in Figure 5, the potentials V0 and 2V ₀ are applied to the terminal S ₁ , the potentials 0 and 3V ₀ are applied to the terminal C ₀ , and the potentials 2V ₀ and V ₀ are applied to the terminal C ₁ alternately. arise. Figure 7 summarizes this relationship. In the diagram, the potential Vs indicates the potential that terminals S ₀ and S ₁ can take, and the potential Vc indicates the potential that terminals C ₀ and C ₁ can take. Of the two potentials, the left one is the flip-flop circuit 2.
The right side shows the potentials generated at each terminal when the output Q of 4 is a logical value "1" (hereinafter simply referred to as "1"), and the right side shows the potentials generated at each terminal when the output Q is "0". Further, the voltage Vs-c indicates the potential difference between the terminals S ₀ and S ₁ and between the terminals C ₀ and C ₁ . As is clear from this, when a potential is applied to the terminals S ₀ and C ₀ , the corresponding display section is lit.

As an example, if the counters 3 to 8 shown in the first figure are
The pointer display when the time is 10:05 will be explained. In this timekeeping state, counter 3 is "5", counter 4 is "0", counter 5 is "0",
The counter 6 counts "0", the counter 7 counts "0", and the counter 8 counts "5". Therefore, as pulses are periodically generated at the terminal P ₁ of the timing pulse generation circuit 10, the second digit gate circuit 1
1 and 14 are opened, and the second data of counter 3 is input to the gate circuit 17, and the second data of counter 4 is input to the gate circuit 18. Therefore, "1" is generated at the 2 ⁰ and 2 ² terminals of the gate circuit 17,
“01” is generated at terminals ²⁰ to ²² of the gate circuit 18. As a result, "1" is produced at the terminal, "0" is produced at the terminal h, and "1" is produced at the terminal _X5 of the decoder 19. Therefore, referring to FIG. 4, gate circuit 3
Since the outputs of the terminals 5 and 43 become "1", the potential generated at the terminal _S0 is generated at the terminal _e6 . Other terminals e ₁ ~
For e ₅ and e ₇ to e ₁₀ , switching circuit 4
Since 7...49, 53...55 are turned on, a potential is generated at the terminal _S1 .

Next, regarding the decoder 20, "1" is generated at the terminal _y0 . On the other hand, since the time zone is morning, the output is "0", and the output of the gate circuit 93 remains "1". Therefore, the potential generated at the terminal _C0 is generated at the terminal _k1 shown in FIG. Further, since the terminal _P3 of the timing pulse generation circuit 10 is "0", the output of the inverter 94 is "1", and the gate circuits 70 to 75 are opened. Therefore, the switching circuit 76 is turned on and the terminal
The potential occurring at C ₀ is generated at terminal g ₁ . The potential occurring at the terminal _C1 is generated at the other terminals _k2 to _k6 and _g2 to _g6 . As a result, when a potential is applied to the terminal e ₆ and the terminals g ₁ and k ₁ , the display section will be lit.

Next, terminal P ₂ of the timing pulse generation circuit 10
When a pulse is generated periodically, gate circuits 12 and 15 are opened, and each data "0" of counters 5 and 6 passes through them. Therefore, "1" is generated at the terminal X ₀ of the decoder 19 and "1" is generated at the terminal y ₀ of the decoder 20, or "1" and h are held at "0".

Therefore, the output of the gate circuit 41 in FIG. 4 becomes "1", the switching circuit 46 is turned on, and the potential which is present at the terminal _S0 is generated at the terminal _e1 . The potential occurring at the terminal _S1 is generated at the other terminals _e2 to _e10 .

Also, from FIG. 6, the potential occurring at the terminal _C0 is generated at the terminals _g1 , _k1 , and the potential at the other terminals _g2 to _g6 and _k2
A potential occurs at terminal C ₁ at ~k ₆ . Accordingly, according to the chart shown in FIG. 7, the display portions corresponding to the terminal e ₁ and the terminals g ₁ and k ₁ are lit.

Furthermore, the terminal of the timing pulse generation circuit 10
When the gate circuits 13 and 16 are opened by the pulses generated periodically at P ₃ , the outputs of the counters 7 and 8 pass through them. As a result, the potential generated at the terminal _S0 is generated at the terminal _e10 of the segment potential setting circuit 22. Terminal of common potential setting circuit 23
The potential that occurs at terminal c ₀ occurs at k ₆ , and the other terminals
The potential generated at the terminal _c1 is generated between _k1 and _k5 . Note that when a pulse occurs at the terminal _P3 , the outputs of the gate circuits ₇₀ to ₇₅ shown in _FIG . Occur.

Therefore, the display portions corresponding to terminal _e10 and terminal _k6 are lit. FIG. 8 shows the pointer display of this embodiment.

Next, when the time slot is in the afternoon, the output Q of the flip-flop circuit 28 shown in the first diagram becomes "1". Therefore, when a pulse is generated at the terminal _P1 of the timing pulse generating circuit 10 shown in the first diagram, the output of the gate circuit 93 becomes "0", so that the gate circuits 91 and 92 are closed. Therefore, terminal k ₁
...The potential applied to terminal _c1 is generated at _k6 . As is clear from the previous explanation, the terminal shown in the third diagram
The display portions corresponding to the common electrodes 50a...30a connected to _k1 to _k6 are not lit. An example of such a display state is shown in FIG. 9, where the display section D is shown in which a part of the second hand displayed in the morning time zone is missing. By looking at the display on the second hand, you can know the morning and afternoon time zones.

In this embodiment, the notification content is morning and afternoon identification, but the present invention is not limited to this, and for example, a decrease in the battery power supply voltage may be detected. In other words, the output logic value is set to be "0" when the battery voltage is steady, and the output logic value "1" is generated when the battery voltage falls below the steady value.
Detection can be performed by supplying the signal to the terminal input of the gate circuit 93 shown in the figure instead of the same input. Therefore, when the second hand display becomes display D shown in FIG. 9, it is possible to know when it is time to replace the battery.

As detailed above, the present invention allows the notification content to be identified by changing the lighting form of the optical pointer display, so that the content can be intuitively followed just by glancing at the pointer display. . Furthermore, there are no problems in terms of space or wiring, and other excellent effects are achieved.

[Brief explanation of the drawing]

The drawings show an embodiment of the present invention; FIG. 1 is a block diagram of an electric circuit, FIG. 2 is a plan view showing the arrangement pattern of segment electrodes of a display device, and FIG. 3 is a common electrode arrangement pattern. 4 to 6 are detailed circuit diagrams of the main parts of the block diagram shown in Fig. 1. Fig. 7 is a diagram showing the states of potentials and voltages applied to the main parts of Fig. 1. and 9 are explanatory diagrams showing the display state of the pointer. 3-9... Counter, 10... Timing pulse generation circuit, 11-16... Gate circuit, 19-20...
Decoder, 22...Segment potential setting circuit, 23
...Common potential setting circuit.

Claims (1)

[Claims] 1. A plurality of segment electrodes arranged radially are divided into a plurality of groups each having a predetermined number of segment electrodes, and corresponding ones of the segment electrodes constituting each group are electrically connected, and a liquid crystal is connected to the segment electrodes of the above group. Common electrodes facing each other are provided in each group to constitute a plurality of display elements to constitute a liquid crystal display device that displays a second hand, a minute hand, and an hour hand, and a reference pulse generation circuit that generates a reference pulse is provided. A timing pulse generation circuit is provided that receives the output of the reference pulse and generates a timing pulse, and receives the output of the timing pulse generation circuit and measures the digit output of the timing pulse. A selection circuit is provided for time-divisionally selecting a pulse voltage, a pulse setting circuit is provided for setting a predetermined number of pulse voltages, and voltages for display and non-display are selected from the pulse setting circuit in accordance with the output of the selection circuit. and a voltage supply circuit for supplying the liquid crystal display to the liquid crystal display device, and when the selection circuit selects seconds digit output, the voltage setting circuit supplies a non-display voltage to the voltage supply circuit to display seconds. An electronic watch display device equipped with a display erasing circuit that turns off some of the display elements.