JPS62154651A - Integrated circuit substrate - Google Patents
Integrated circuit substrateInfo
- Publication number
- JPS62154651A JPS62154651A JP29581485A JP29581485A JPS62154651A JP S62154651 A JPS62154651 A JP S62154651A JP 29581485 A JP29581485 A JP 29581485A JP 29581485 A JP29581485 A JP 29581485A JP S62154651 A JPS62154651 A JP S62154651A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- holes
- integrated circuit
- plate
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 26
- 239000010432 diamond Substances 0.000 claims abstract description 25
- 229910003460 diamond Inorganic materials 0.000 claims abstract description 25
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 9
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 9
- 239000000919 ceramic Substances 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 3
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 claims description 12
- 239000007789 gas Substances 0.000 claims description 7
- 239000001257 hydrogen Substances 0.000 claims description 4
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- FRWYFWZENXDZMU-UHFFFAOYSA-N 2-iodoquinoline Chemical compound C1=CC=CC2=NC(I)=CC=C21 FRWYFWZENXDZMU-UHFFFAOYSA-N 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- LTPBRCUWZOMYOC-UHFFFAOYSA-N beryllium oxide Inorganic materials O=[Be] LTPBRCUWZOMYOC-UHFFFAOYSA-N 0.000 claims description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 12
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 4
- 229910000040 hydrogen fluoride Inorganic materials 0.000 abstract description 4
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 4
- 239000000377 silicon dioxide Substances 0.000 abstract description 4
- 238000001312 dry etching Methods 0.000 abstract description 2
- 239000003513 alkali Substances 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 238000006243 chemical reaction Methods 0.000 description 7
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 4
- 238000010292 electrical insulation Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000010453 quartz Substances 0.000 description 3
- 239000002994 raw material Substances 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000010802 sludge Substances 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- YZCKVEUIGOORGS-IGMARMGPSA-N Protium Chemical compound [1H] YZCKVEUIGOORGS-IGMARMGPSA-N 0.000 description 1
- 241000220304 Prunus dulcis Species 0.000 description 1
- 229910018540 Si C Inorganic materials 0.000 description 1
- 235000020224 almond Nutrition 0.000 description 1
- -1 and in this example Chemical compound 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
- H01L21/481—Insulating layers on insulating parts, with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3732—Diamonds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 ［産業上の利用分野１ 本発明は集積回路基板に関し、特にその構造に関する。[Detailed description of the invention] [Industrial application field 1 TECHNICAL FIELD This invention relates to integrated circuit boards, and more particularly to their structures.
［従来の技術］
集積回路基板としては、従来、電気絶縁性に優れ、かつ
焼成や研磨か容易であるアルミナ（△４Ｑ２０３）セラ
ミックスが多用されている。[Prior Art] Conventionally, alumina (Δ4Q203) ceramics, which have excellent electrical insulation properties and are easily fired and polished, have been widely used for integrated circuit boards.
［発明が解決しようとする問題点１
ところで近年、集積回路はその集積疫か飛躍的に向上し
ており、例えばウェハ規模の１．−３Ｉてｔ、１その発
熱量は１Ｋｗ程にｂなる。[Problem to be Solved by the Invention 1]In recent years, the integration rate of integrated circuits has improved dramatically.For example, 1. -3It, 1The calorific value is about 1Kw.
ここにおいて、上記従来のアルミナ基板ではその熱伝導
性が比較的悪いため、現状以上の回路集積度の向」二は
困難である。Here, since the conventional alumina substrate described above has relatively poor thermal conductivity, it is difficult to increase the degree of circuit integration beyond the current level.
本発明はかかる問題点に鑑み、電気絶縁性および熱伝導
性共に優れる集積回路基板を提供することを目的とする
。SUMMARY OF THE INVENTION In view of these problems, an object of the present invention is to provide an integrated circuit board having excellent electrical insulation and thermal conductivity.
［問題点を解決するための手段］
本発明の構成を第１図、第２図で説明すると、金属ない
しセラミックスよりなる板状基板１には多数の貫通孔１
ａが設けてあり、上記基体１にはダイヤモンド層２が形
成しである。ダイヤモンド層２は上記各貫通孔１ａを埋
めるとともに基体１表面を覆っている。[Means for Solving the Problems] The configuration of the present invention will be explained with reference to FIGS. 1 and 2. A plate-shaped substrate 1 made of metal or ceramics has a large number of through holes 1.
A is provided, and a diamond layer 2 is formed on the base 1. The diamond layer 2 fills each of the through holes 1a and covers the surface of the base 1.
［作用、効果］
上記構造の集積回路基板は、熱伝導率が従来のアルミナ
基板の約５０倍にも達し、しかも電気絶縁性も充分であ
る。[Operations and Effects] The integrated circuit board having the above structure has a thermal conductivity approximately 50 times that of a conventional alumina board, and also has sufficient electrical insulation.
すなわち、板状基体に多数の貫通孔を設けてこれらをダ
イヤモンド層で埋めたから、集積回路を形成する一方の
面より他方の面へ大量の熱伝達が可能となったのである
。That is, by providing a large number of through holes in the plate-shaped substrate and filling them with a diamond layer, a large amount of heat could be transferred from one surface of the integrated circuit to the other surface.
かかる回路基板を使用することにより、回路集積度を更
に飛躍的に向上せしめることができる。By using such a circuit board, the degree of circuit integration can be further dramatically improved.
［実施例］
第１図には本発明になる回路基板の断面図を示し、第２
図にはその平面図を示す。図中、１は炭化ケイ素（Ｓｉ
Ｃ）よりなる板状基体であり、該基体１には板面を貫通
する多数の貫通孔１ａが設けである。図は理解を容易に
するために各部の寸法比を実際と異ならしめてあり、基
体１は約１０ｍｍ角、貫通孔１ａは直径約１０μでおる
。開口率は基体１の機械的強度を損なわない程度に大き
くする。[Example] FIG. 1 shows a cross-sectional view of a circuit board according to the present invention, and FIG.
The figure shows the plan view. In the figure, 1 is silicon carbide (Si
C), and the substrate 1 is provided with a large number of through holes 1a that penetrate through the plate surface. In the figure, the dimensional ratio of each part is made different from the actual size to facilitate understanding, and the base body 1 is approximately 10 mm square, and the through hole 1a is approximately 10 μm in diameter. The aperture ratio is made large enough not to impair the mechanical strength of the base 1.
そして、上記基体１は全体をダイヤモンド層２で覆って
おり、ダイヤモンド層２は各貫通孔１ａ内を埋めている
。ダイヤモンド層２の厚さは約１０μである。The base body 1 is entirely covered with a diamond layer 2, and the diamond layer 2 fills each through hole 1a. The thickness of the diamond layer 2 is approximately 10μ.
かかる回路基板は以下の手順で製作する。第３図には基
体１の製作工程を示す。図において、ＳｉＣ板１′には
スパッタ等によりシリカ（Ｓ１０２）膜３を形成する（
第３図（１））。続いて上記５ｉｎ２膜３上にレジスト
４を塗布し、上記貫通孔１ａのパターンを露光し現象す
る（第３図（２））。これにより、レジスト４には貫通
孔１ａを形成すべき位置に扱き穴４ａが形成される（第
３図（３））。続いて、フッ化水素系溶液で上記抜き穴
４ａ内に露出したＳｉＯ２膜３をエツチングしく第３図
（４））、その後レジスト４をはく離除去する（第３図
（５））。この状態で、水酸化ナトリウム（ＮａＯＨ＞
溶液等を使用したアルカリエツチング、あるいはドライ
エツチングによりＳｉＣ板１−に貫通孔１ａを形成しく
第３図（６））、再びフッ化水素系溶液で５ｉ０２膜３
を除去して基体１とする（第３図（７））。Such a circuit board is manufactured by the following procedure. FIG. 3 shows the manufacturing process of the base body 1. In the figure, a silica (S102) film 3 is formed on a SiC plate 1' by sputtering or the like (
Figure 3 (1)). Subsequently, a resist 4 is applied on the 5in2 film 3, and the pattern of the through holes 1a is exposed to light (FIG. 3(2)). As a result, a handling hole 4a is formed in the resist 4 at the position where the through hole 1a should be formed (FIG. 3(3)). Subsequently, the SiO2 film 3 exposed in the hole 4a is etched using a hydrogen fluoride solution (FIG. 3 (4)), and then the resist 4 is peeled off (FIG. 3 (5)). In this state, sodium hydroxide (NaOH>
The through-holes 1a are formed in the SiC plate 1- by alkaline etching using a solution or dry etching (Fig. 3 (6)), and the 5i02 film 3 is again etched with a hydrogen fluoride solution.
is removed to obtain a base 1 (FIG. 3 (7)).
このようにして製作した基体１にダイヤモンド層２を形
成するには、例えばマイクロ波プラズマＣＶＤ装置によ
る。装置構成を第４図に示す。図において、石英反応管
５１内にはホルダ５２が設けてあり、該ホルダ５２上に
上記基体１が支持せしめである。反応管５１内は図略の
真空排気装置により約５０Ｔｏｒｒの真空に保たれてい
る。上記基体１付近にはマイクロ波電源５６に接続され
た導波管５３により２４５０ＭＨｚのマイクロ波が供給
されている。なお、図中、５４．５５はそれぞれ整合器
およびアイソレータである。To form the diamond layer 2 on the substrate 1 manufactured in this manner, for example, a microwave plasma CVD apparatus is used. The device configuration is shown in FIG. 4. In the figure, a holder 52 is provided inside a quartz reaction tube 51, and the base 1 is supported on the holder 52. The inside of the reaction tube 51 is maintained at a vacuum of about 50 Torr by an unillustrated vacuum evacuation device. A microwave of 2450 MHz is supplied to the vicinity of the base 1 by a waveguide 53 connected to a microwave power source 56. In addition, in the figure, 54 and 55 are a matching box and an isolator, respectively.
この状態で上記反応管５１内にガス供給管５７を介して
原料カスを供給する。原料ガスはメタンと水素の混合ガ
スであり、本実施例ではメタン／水索＝０．８ （体積
％）とした。かがる原料ガスは基体１付近でマイクロ波
電力を受けてプラズマＢとなり、基体１上にダイヤモン
ドが析出する。In this state, raw material waste is supplied into the reaction tube 51 via the gas supply pipe 57. The raw material gas is a mixed gas of methane and hydrogen, and in this example, methane/water line=0.8 (volume %). The raw material gas for darning receives microwave power near the base 1 and becomes plasma B, and diamond is deposited on the base 1.
発明者らの実験では、マイクロ波電力５００Ｗ、メタン
流ｆＮ０．８ｃｃ ／ｍｉｎ 、水素流ｆｆ１９９．
２ｃｃ ／ｍｉｎの条件で、ダイヤンド層２の成長速
度は０．６μ／ｈであった。In the experiments conducted by the inventors, microwave power was 500 W, methane flow was fN0.8 cc/min, and hydrogen flow was f199.
Under the condition of 2 cc/min, the growth rate of the diamond layer 2 was 0.6 μ/h.
上記構造の集積回路基板は、レーザフラッシュ法による
測定で熱伝導率が約１２００ｗ／ｍｋと大きな値を示し
、これは従来のアルミナ基板の約５０倍であり、銅と比
較しても約３倍である。また、電気絶縁性についても比
抵抗が１ｏ１３ Ω・ｃｍと充分大きな値を示す。The integrated circuit board with the above structure exhibits a large thermal conductivity of approximately 1200 W/mK when measured using the laser flash method, which is approximately 50 times that of conventional alumina boards and approximately three times that of copper. It is. Furthermore, regarding electrical insulation, the specific resistance shows a sufficiently large value of 1013 Ω·cm.
しかして、本発明の回路基板を使用することにより、回
路集積度を更に飛躍的に向上せしめることか可能でおる
。Therefore, by using the circuit board of the present invention, it is possible to further dramatically improve the degree of circuit integration.
本発明の回路基板においては、その表面をダイヤモンド
層２て覆うとともに上下面を４通する多数の通孔１ａを
設りて該通孔１ａ内をダイヤモンド層で満たしたから、
集積回路を形成する基板上面より下面へ向けて大量の熱
を効率的に伝熱せしめることができるのでおる。In the circuit board of the present invention, its surface is covered with a diamond layer 2, and a large number of through holes 1a are provided in the upper and lower surfaces, and the insides of the through holes 1a are filled with the diamond layer.
A large amount of heat can be efficiently transferred from the upper surface to the lower surface of the substrate forming the integrated circuit.
また、発明者らの実験によると、基体１へのダイヤモン
ド析出は、貫通孔１ａ開口のエツジ部にダイヤモンドの
核か効果的に生じることにより促進されることか確認さ
れた。Further, according to experiments conducted by the inventors, it was confirmed that diamond precipitation on the substrate 1 is promoted by the effective formation of diamond nuclei at the edge portion of the opening of the through hole 1a.
基体１へのダイヤモンド層２の形成は、高周波プラズマ
ＣＶＤ装置、必るいは熱フィラメントＣ＼／Ｄ装置によ
っても行ない得る。これをそれぞれ第５図、第６図に示
す。The formation of the diamond layer 2 on the substrate 1 can be carried out by means of a high frequency plasma CVD apparatus, or alternatively also by a hot filament C\/D apparatus. This is shown in FIGS. 5 and 6, respectively.
第５図に示す高周波プラズマＣＶＤ装置において、５８
は水冷されたワークコイルであり、該コイル５８には図
略の高周波電源より例えば１３゜５６Ｍ１ｉＺの高周波
電力が供給される。この状態で石英反応管５１内を約３
０〜１００Ｔｏｒｒの真空に保ら、カス供給管５７より
メタン／水素−１（体積％）の混合カスを供給する。混
合カスは高周波電力を受けてプラズマＢとなり、ダイヤ
モンドか基体１上に析出する。In the high frequency plasma CVD apparatus shown in FIG.
is a water-cooled work coil, and a high frequency power of, for example, 13°56M1iZ is supplied to the coil 58 from a high frequency power source (not shown). In this state, the inside of the quartz reaction tube 51 is
A vacuum of 0 to 100 Torr is maintained, and a mixed sludge of methane/hydrogen-1 (volume %) is supplied from the sludge supply pipe 57. The mixed scum becomes plasma B by receiving high-frequency power, and is deposited on the diamond substrate 1.
第６図に示す“熱フイラメントＣＶＤ装置において、６
英反応管５１内にホルダ５２で支持された基体１の近傍
にはＱ、３ｍｍ 径のタングスデンフィラメント５９が
位置せしめてあり、識フィラメン１〜５９は図略の電源
より通電されて２０００’Ｃ以上に赤熱せしめられてい
る。基体１が位置号る石英反応管５１の外周には環状炉
６０が設けられ、吊体１同囲の雰囲気を７００〜９００
°Ｃに保っている。また、上記反応管５１内は約３０Ｔ
ｏ ｒ ｒの真空に保持されている。この状態でガス供
給管５７よりメタン／水素＝１（体積％〉の混合）ｊス
を供給すると、これは上記フィラメント５９により分解
励起され、基体１上にダイへアモンドが析出する。In the "thermal filament CVD apparatus" shown in FIG.
A tungsten filament 59 with a diameter of 3 mm is placed near the substrate 1 supported by a holder 52 in the reaction tube 51, and the filaments 1 to 59 are energized from an unillustrated power source to a temperature of 2000°C. It's even more red-hot. An annular furnace 60 is provided around the outer periphery of the quartz reaction tube 51 in which the base 1 is located, and the atmosphere around the hanging body 1 is heated to 700 to 900 ℃.
It is kept at °C. Moreover, the inside of the reaction tube 51 is about 30T.
It is kept in a vacuum of o r r. In this state, when methane/hydrogen=1 (volume % mixture) gas is supplied from the gas supply pipe 57, it is decomposed and excited by the filament 59, and almonds are deposited on the die on the substrate 1.
なお、上記基体１としては、上記ＳｉＣ板以外に、窒化
アルミニウム、酸化ベリリウム等のセラミックス、ある
いは銅、アルミ、タングステン等の金属が使用できる。In addition to the SiC plate, ceramics such as aluminum nitride and beryllium oxide, or metals such as copper, aluminum, and tungsten can be used as the substrate 1.
これらセラミックスおよび金属はできる限り熱伝導率が
大きく、かつ熱膨張率がダイヤモンドと近いものが望ま
しい。そして、上記ダイヤモンド形成用の各装置は、基
体１として使用する材料の耐熱性に応じて選択される。It is desirable that these ceramics and metals have as high a thermal conductivity as possible and a coefficient of thermal expansion close to that of diamond. Each of the above diamond forming devices is selected depending on the heat resistance of the material used as the substrate 1.
また、貴通孔１ａの形状は円形に限らず、四角おるいは
三角等でも良い。Further, the shape of the through hole 1a is not limited to a circular shape, but may be square, triangular, or the like.
ざらに、金属基体への１通孔の形成はレーザ７ＪＤ工に
よっても良い。In general, the formation of one hole in the metal substrate may be performed by laser 7JD machining.
第１図は集積回路基板の断面図、第２図はその平面図、
第３図は基体の製造工稈を示す断面図、第４図ないし第
６図はそれぞれダイヤモンド層形成用の各装置の概略構
成図でおる。
１・・・・・・板状基体 １′・・・・・・炭化
ケイ素板２・・・・・・ダイヤモンド層 ３・・・・・
・シリカ膜４・・・・・・レジスト
’；Ｎ；１＠
“３暮
ニ１，５ 図
・６二Figure 1 is a cross-sectional view of the integrated circuit board, Figure 2 is its plan view,
FIG. 3 is a cross-sectional view showing the process for manufacturing the substrate, and FIGS. 4 to 6 are schematic diagrams of each apparatus for forming a diamond layer. 1...Plate-shaped substrate 1'...Silicon carbide plate 2...Diamond layer 3...
・Silica film 4...Resist';N;1@"3 1, 5 Figure 62
Claims (6)
の貫通孔を設け、かつ該貫通孔を埋めるとともに基体表
面を覆うダイヤモンド層を形成したことを特徴とする集
積回路基板。(1) An integrated circuit board characterized in that a plate-shaped base made of metal or ceramics is provided with a large number of through holes, and a diamond layer is formed to fill the through holes and cover the surface of the base.
ずれかの金属板で構成した特許請求の範囲第１項記載の
集積回路基板。(2) The integrated circuit board according to claim 1, wherein the base is made of a metal plate of copper, aluminum, or tungsten.
び酸化ベリリウムのいずれかのセラミックス板で構成し
た特許請求の範囲第１項記載の集積回路基板。(3) The integrated circuit board according to claim 1, wherein the base is made of a ceramic plate of silicon carbide, aluminum nitride, or beryllium oxide.
を約１０μで形成してなる特許請求の範囲第１項記載の
集積回路基板。(4) The integrated circuit board according to claim 1, wherein the through hole has a diameter of about 10 microns and the diamond layer has a diameter of about 10 microns.
成した特許請求の範囲第１項記載の集積回路基板。(5) The integrated circuit board according to claim 1, wherein the through hole is formed by etching a silicon carbide plate.
び水素の混合ガスプラズマを析出せしめて形成した特許
請求の範囲第１項記載の集積回路基板。(6) The integrated circuit board according to claim 1, wherein the diamond layer is formed on the substrate by depositing a mixed gas plasma of methane and hydrogen.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29581485A JPS62154651A (en) | 1985-12-26 | 1985-12-26 | Integrated circuit substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29581485A JPS62154651A (en) | 1985-12-26 | 1985-12-26 | Integrated circuit substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62154651A true JPS62154651A (en) | 1987-07-09 |
Family
ID=17825508
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29581485A Pending JPS62154651A (en) | 1985-12-26 | 1985-12-26 | Integrated circuit substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62154651A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0707741A1 (en) * | 1994-05-05 | 1996-04-24 | Siliconix Incorporated | Surface mount and flip chip technology |
| US5757081A (en) * | 1994-05-05 | 1998-05-26 | Siliconix Incorporated | Surface mount and flip chip technology for total integrated circuit isolation |
| US5767578A (en) * | 1994-10-12 | 1998-06-16 | Siliconix Incorporated | Surface mount and flip chip technology with diamond film passivation for total integated circuit isolation |
| JP2006111500A (en) * | 2004-10-15 | 2006-04-27 | Sumitomo Electric Ind Ltd | Diamond substrate and its manufacturing method |
-
1985
- 1985-12-26 JP JP29581485A patent/JPS62154651A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0707741A1 (en) * | 1994-05-05 | 1996-04-24 | Siliconix Incorporated | Surface mount and flip chip technology |
| EP0707741A4 (en) * | 1994-05-05 | 1997-07-02 | Siliconix Inc | Surface mount and flip chip technology |
| US5757081A (en) * | 1994-05-05 | 1998-05-26 | Siliconix Incorporated | Surface mount and flip chip technology for total integrated circuit isolation |
| US5767578A (en) * | 1994-10-12 | 1998-06-16 | Siliconix Incorporated | Surface mount and flip chip technology with diamond film passivation for total integated circuit isolation |
| JP2006111500A (en) * | 2004-10-15 | 2006-04-27 | Sumitomo Electric Ind Ltd | Diamond substrate and its manufacturing method |
| JP4691952B2 (en) * | 2004-10-15 | 2011-06-01 | 住友電気工業株式会社 | Diamond substrate and manufacturing method thereof |
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