JPS62153199A - Gaseous-phase etching device for iii-v compound semiconductor - Google Patents

Gaseous-phase etching device for iii-v compound semiconductor

Info

Publication number
JPS62153199A
JPS62153199A JP29257585A JP29257585A JPS62153199A JP S62153199 A JPS62153199 A JP S62153199A JP 29257585 A JP29257585 A JP 29257585A JP 29257585 A JP29257585 A JP 29257585A JP S62153199 A JPS62153199 A JP S62153199A
Authority
JP
Japan
Prior art keywords
reaction tube
substrate crystal
crystal
substrate
iii
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP29257585A
Other languages
Japanese (ja)
Other versions
JPH0355439B2 (en
Inventor
Akira Usui
彰 碓井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP29257585A priority Critical patent/JPS62153199A/en
Publication of JPS62153199A publication Critical patent/JPS62153199A/en
Publication of JPH0355439B2 publication Critical patent/JPH0355439B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE:The titled device capable of precisely controlling etching depth in a monomo lecular layer unit, wherein a halogen gas or a hydrogen halide gas is adsorbed on surface of substrate crystal in a low-temperature zone and an element of group III is vaporized as a halide of the element of group III of III-V compound semiconductor in a high-temperature zone. CONSTITUTION:In a gaseous-phase etching device for III-V compound semiconductor such as GaAs, etc., a substrate holder 2 capable of transporting a reaction tube 1 in the longer direction in the interior of a reaction chamber of the reaction tube and a resistant heating means 4 to heat the interior of the reaction tube is set at the outside. Firstly, the substrate holder 2 is transferred, substrate crystal 3 is placed at a low-temperature zone 6 at the upper stream of the reaction tube, the temperature of the crystal is raised to desired temperature (600 deg.C) and HCl is fed to the zone and sufficiently adsorbed on the surface of the substrate crystal (first process). Then, the substrate crystal is transferred to a high-temperature zone 7 (600 deg.C) at the down stream and Ga is removed as GaCl from the surface of crystal (second process). The substrate crystal 3 is retransferred to the low-temperature zone 6 at the upper stream of the reaction tube. The above-mentioned processes are repeated by using this device so that the titled extremely precisely controlled etching can be carried out.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、■−V族化合物半導体の非常に精密に制御さ
れた気相エツチング装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a highly precisely controlled vapor phase etching apparatus for ■-V group compound semiconductors.

〔従来技術とその問題点〕[Prior art and its problems]

GaAs、InP等のようなm−v族化合物半導体の気
相エピタキシャル成長結晶は、発光ダイオード、レーザ
ダイオードのような光デバイスや、FETのようなマイ
クロ波デバイスに広く応用されている。ところで、基板
結晶上に気を目成長によりエピタキシャル成長を行なう
場合、基板結晶のエツチングを行なうのが普通である。
Vapor phase epitaxially grown crystals of m-v group compound semiconductors such as GaAs and InP are widely applied to optical devices such as light emitting diodes and laser diodes, and microwave devices such as FETs. By the way, when epitaxial growth is performed on a substrate crystal by optical growth, the substrate crystal is usually etched.

・このエツチングには、基板結晶を反応管にセットする
前に行なう溶液によるタミカルエッチングと、反応管に
セット後成長直前に行なう気相エツチングとがある。前
者は主として基板結晶表面に残っている鏡面研廖の際に
発生した破壊層を取り除くのが目的であり、後者は主と
してケミカルエツチング後から反応管にセットするまで
の間に表面に形成された酸化膜や、ゴミなどの付着した
不純物を除去したり、昇温の間に形成された変成層を除
去するのが目的である。この気相エツチングが十分でな
いと、表面上に残った酸化膜や微小なゴミ等が核となり
、ヒルロック等の表面欠陥の非常に多い成長面となる。
- This etching includes chemical etching using a solution, which is performed before setting the substrate crystal in the reaction tube, and vapor phase etching, which is performed after setting the substrate crystal in the reaction tube and immediately before growth. The purpose of the former is to remove the destructive layer that remains on the surface of the substrate crystal during mirror polishing, and the purpose of the latter is to remove the oxidized layer that is formed on the surface between the time of chemical etching and the time of setting it in the reaction tube. The purpose is to remove attached impurities such as films and dust, and to remove metamorphic layers formed during temperature rise. If this vapor phase etching is not sufficient, the oxide film, minute dust, etc. remaining on the surface become nuclei, resulting in a growth surface with many surface defects such as hillocks.

また、エピタキシアル層と基板結晶の界面にディップ層
と呼ばれるキャリア濃度の非常に低下した部分が生じた
りする。これらは何れもデバイス作製上、有害なもので
ある。従って、この気本目エツチングは結晶成長上欠か
せないプロセスである。
Further, a portion called a dip layer where the carrier concentration is extremely reduced may occur at the interface between the epitaxial layer and the substrate crystal. All of these are harmful to device fabrication. Therefore, this serious etching is an essential process for crystal growth.

ところで、従来の気相エツチング装置を、第3図に示し
たハイドライド気を目成長装置に於いて説明する。Ga
Asの成長を例に取ると、反応管1の上流にGaソース
ポート10を置き、その上流からH2キャリヤガスと共
にHClガスを供給する。
By the way, a conventional vapor phase etching apparatus will be explained using a hydride eye growth apparatus shown in FIG. Ga
Taking the growth of As as an example, a Ga source port 10 is placed upstream of the reaction tube 1, and HCl gas is supplied together with H2 carrier gas from the upstream side.

この結果、GaCβが生成され下流に運ばれる。As a result, GaCβ is generated and transported downstream.

また、Gaソースポート10をバイパスするパイプ5か
らAsの水素化物であるA s H3をH2キャリヤガ
スと共に供給する。この両者のガスが基板結晶3の領域
で混合し成長が起こる。気相エツチングは、バイパスパ
イプ5からHClガスを供給する二とによって行ない、
Ga輸送用のHClガスとの比を調整することによって
そのエツチング速度を制御していた。しかしながら、こ
の従来装置では、基板結晶温度、Ga輸送用のHClガ
ス流量、あるいはΔsH3流遣等成長条件にエツチング
速度が大きく影響され、デバイス作製上要求される精度
を持ってエツチング深さを制御することは不可能であっ
た。
Further, As H3, which is a hydride of As, is supplied from the pipe 5 bypassing the Ga source port 10 together with the H2 carrier gas. These two gases mix in the region of the substrate crystal 3 and growth occurs. Gas phase etching is carried out by supplying HCl gas from the bypass pipe 5,
The etching rate was controlled by adjusting the ratio to HCl gas for Ga transport. However, in this conventional apparatus, the etching rate is greatly affected by growth conditions such as substrate crystal temperature, HCl gas flow rate for Ga transport, or ΔsH3 flow, and it is difficult to control the etching depth with the precision required for device fabrication. That was impossible.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、■−V族化合物半導体の気相エツチン
グにおいて、従来のかかる欠点を除去し、エツチング深
さの精密な制御が可能な気相エツチング装置を提供しよ
うとするものである。
An object of the present invention is to provide a vapor phase etching apparatus which eliminates the conventional drawbacks in vapor phase etching of group 1-V compound semiconductors and allows precise control of the etching depth.

〔発明の構成〕[Structure of the invention]

本発明によれば、I−V族化合物半導体の気相エツチン
グ装置において、反応管と、この反応管の内部に設けら
れ、基板結晶を保持する移動可能な基板ホルダと、前記
反応管の外部に設けられ、反応管内部を温度傾斜を保っ
て加熱する加熱手段とを備え、低温領域でハロゲンない
しハロゲン化水素ガスを基板結晶表面に吸着させ、高温
領域で、■−V族化合物半導体の■族元素のハロゲン化
物として基板結晶表面から■族元素を揮発させることを
特徴とするI−V族化合物半導体の気相エツチング装置
が得られる。
According to the present invention, in a vapor phase etching apparatus for a group IV compound semiconductor, there is provided a reaction tube, a movable substrate holder provided inside the reaction tube and holding a substrate crystal, and a movable substrate holder provided inside the reaction tube to hold a substrate crystal; The device is equipped with a heating means for heating the inside of the reaction tube while maintaining a temperature gradient, and adsorbs halogen or hydrogen halide gas onto the substrate crystal surface in the low temperature region, and adsorbs the halogen or hydrogen halide gas on the substrate crystal surface in the high temperature region. A vapor phase etching apparatus for IV group compound semiconductors is obtained, which is characterized by volatilizing group (I) elements from the substrate crystal surface as elemental halides.

〔作用〕[Effect]

本発明の装置では2つの工程が実施される。先ず最初に
基板結晶上にハロゲンないしハロゲン化水素ガスを吸着
させる第一の工程である。例えばGaAsとHCj’ガ
スの場合、基板結晶温度が比較的高い場合にはHClガ
スの供給によりすぐにエツチングが生じるが、以下の実
施例でも述べるように、400℃程度になると、基板結
晶上にHClガスを供給してもエツチングを生じること
は一;<HClの吸着のみが起こる。このようにHCl
が吸着した後、HClガスの供給を止め、次に、この基
板結晶を高温度領域に移動し、GaCβとして結晶表面
からGaを取り去る。これが第二の工程である。Gaと
の結合ボンドを切るれたAs原子は自分自身で気相中に
飛び出すと考えられる。この第一の工程と第二の工程に
より、基板結晶表面の一分子層がエツチングされること
になる。従って、本発明による気相エツチング装置を用
いると、エツチングの深さは第一の工程と第二の工程の
繰り返しの数にのみ依存し、しかも、一分子層の単位(
約3人)で制御できるようになる。
Two steps are carried out in the device of the invention. This is the first step in which halogen or hydrogen halide gas is first adsorbed onto the substrate crystal. For example, in the case of GaAs and HCj' gas, if the substrate crystal temperature is relatively high, etching will occur immediately upon supply of HCl gas, but as will be described in the examples below, when the temperature reaches about 400°C, etching will occur on the substrate crystal. Even if HCl gas is supplied, no etching occurs; only adsorption of HCl occurs. In this way HCl
After adsorption, the supply of HCl gas is stopped, and then this substrate crystal is moved to a high temperature region to remove Ga from the crystal surface as GaCβ. This is the second step. It is thought that the As atoms, whose bond with Ga is broken, fly out into the gas phase by themselves. Through these first and second steps, one molecular layer of the substrate crystal surface is etched. Therefore, when using the gas phase etching apparatus according to the invention, the etching depth depends only on the number of repetitions of the first and second steps, and moreover, in units of monolayers (
It can be controlled by approximately 3 people.

次に、本発明を実施例に基づき具体的に説明する。Next, the present invention will be specifically explained based on examples.

〔実施例〕〔Example〕

実施例 1 本実施例ではGaAs基板結晶を前面に亘って気相エツ
チングする場合に本発明を適用した場合について述べる
。本実施例の気相エツチング装置の概略を第1図に示し
た。
Embodiment 1 In this embodiment, a case will be described in which the present invention is applied to vapor phase etching the entire front surface of a GaAs substrate crystal. FIG. 1 shows an outline of the vapor phase etching apparatus of this embodiment.

反応管1は1つの反応室を有し、内部には反応管の長手
方向に移動し1尋る基板ホルダ2が設けられている。反
応管1の外部には、反応管内部を加熱する抵抗加熱半没
4が設けられている。
The reaction tube 1 has one reaction chamber, and is provided with a substrate holder 2 that moves one step in the longitudinal direction of the reaction tube. On the outside of the reaction tube 1, there is provided a resistance heating semi-immersion 4 for heating the inside of the reaction tube.

この装置に於いて反応管lが上流からH2キマリャガス
と共にHClガスを供給する。また、反応管に挿入した
バイパスパイプ5からA Sの水素化物であるASH3
をH2キャリヤガスと共に供給する。基板結晶3として
は(100)面方位のG a 、A sを用いた。反応
管の温度は抵抗加熱手段4により制御し、上流部は40
0℃、下流部は600℃に保った。
In this apparatus, a reaction tube 1 supplies HCl gas together with H2 chimal gas from upstream. In addition, ASH3, which is a hydride of AS, is released from the bypass pipe 5 inserted into the reaction tube.
is supplied together with H2 carrier gas. As the substrate crystal 3, Ga and As having (100) plane orientation were used. The temperature of the reaction tube is controlled by resistance heating means 4.
The temperature was kept at 0°C and the downstream part was kept at 600°C.

ガス流量条件は次の通りである。The gas flow conditions are as follows.

HCl1     5  cc/m1nASH35CC
/m1n 82     2.000 c c/rn i nエツ
チングの手順としては、先ず、基板ホルダ2を移動して
基板結晶3を反応管上流の低温領域6に置き、所定温度
(400℃)まで昇温した。その温度に達した所でHC
Iを供給し、そこで10秒間HCIを十分に吸着させ(
第一工程)、基板結晶3を下流の高温領域7 (600
℃)に移動しく第二の工程)、10秒後再び基板結晶3
を反応管上流の低温領域6に移動した。これを−サイク
ルとして、ここでは300サイクル行なった。この後、
基板結晶3を取り出し、エツチング深さの評価を行なっ
たところ、GaAsは約850人の厚さエツチングされ
ていることがわかった。これは、−サイクルに一分子層
がエツチングされていることを示している。
HCl1 5 cc/m1nASH35CC
/m1n 82 2.000 c c c/rn i In the etching procedure, first, the substrate holder 2 is moved, the substrate crystal 3 is placed in the low temperature region 6 upstream of the reaction tube, and the temperature is raised to a predetermined temperature (400° C.). did. When that temperature is reached, HC
I was supplied, and HCI was sufficiently adsorbed there for 10 seconds (
(first step), the substrate crystal 3 is placed in the downstream high temperature region 7 (600
℃), then move the substrate crystal 3 again after 10 seconds (second step).
was moved to the low temperature area 6 upstream of the reaction tube. This was defined as a -cycle, and 300 cycles were performed here. After this,
When the substrate crystal 3 was taken out and the etching depth was evaluated, it was found that the GaAs was etched to a thickness of approximately 850 mm. This indicates that a monolayer was etched in the − cycle.

次に反応管上流部の温度を200〜400℃、反応管下
流部の温度を600〜750℃の間で変化させたり、H
CI流−量を変化させてエツチング深さの変化を調べた
が、−サイクルにほぼ一分子層がエツチングされている
結果は変わらなかった。これらの結果は、エンチングの
深さは第一の工程と第二の工程の繰り返しの数にのみ依
存し、しかも、一分子層の単位(約3人)で精密に制御
できる本発明の効果を良く現わしている。更に、エツチ
ング面は、表面欠陥や、特別なモフォロジーがなく、鏡
面性に優れたものが得られた。
Next, the temperature at the upstream part of the reaction tube was varied between 200 and 400°C, and the temperature at the downstream part of the reaction tube was varied between 600 and 750°C.
Changes in the etching depth were investigated by changing the CI flow rate, but the result remained unchanged: approximately one molecular layer was etched in each cycle. These results demonstrate that the depth of etching depends only on the number of repetitions of the first and second steps, and that the effect of the present invention is that it can be precisely controlled in units of one molecular layer (approximately 3 people). It shows itself well. Furthermore, the etched surface had no surface defects or special morphology, and had excellent specularity.

実施例 2 本実施例ではGaAs基板結晶を用いてエツチング−成
長の連続プロセスにおいて本発明を適用した場合につい
て述べる。用いた装置の概略を第2図に示した。反応管
1は上段反応室8と下段反応室9との2つの反応室を有
し、反応管1の内部にはこれら反応室間を上下方向に、
および反応室8.9内を長手方向に移動し得る基板ホル
ダ2が設けられている。反応管1の外部には、反応管内
部を加熱する抵抗加熱手段4が設けられている。
Example 2 In this example, a case will be described in which the present invention is applied to a continuous process of etching and growth using a GaAs substrate crystal. Figure 2 shows an outline of the apparatus used. The reaction tube 1 has two reaction chambers, an upper reaction chamber 8 and a lower reaction chamber 9, and inside the reaction tube 1 there is a space between these reaction chambers in the vertical direction.
and a substrate holder 2 which can be moved longitudinally within the reaction chamber 8.9. A resistance heating means 4 is provided outside the reaction tube 1 to heat the inside of the reaction tube.

この装置では、上段反応室8の上流からH2キャリヤガ
スと共にHCj2ガス、Asの水素化物であるA s 
H3を供給する。下役反応室9の上流にはGaソースポ
ート10置き、その上流からH2キャリヤガスと共にH
Clガスを供給する。また、Gaソースポート10をバ
イパスするパイプ5からはAsの水素化物であるASH
3をH2キャリヤガスと共に供給する。基板結晶3とし
ては、G a A s (100)ウェファ−を用いた
。反応管1の温度は抵抗加熱手段4により制御し、Ga
ソース部は800℃、上段反応室8の高温領域11およ
び下段反応室9の成長領域12は600℃、上段反応室
8の低温領域13は400℃に保った。ガス流量条件は
次の通りである。
In this apparatus, HCj2 gas and As hydride A s
Supply H3. A Ga source port 10 is placed upstream of the subordinate reaction chamber 9, and H2 carrier gas and H2 are supplied from the upstream of the Ga source port 10.
Supply Cl gas. In addition, from the pipe 5 bypassing the Ga source port 10, ASH, which is a hydride of As, is
3 with H2 carrier gas. As the substrate crystal 3, a GaAs (100) wafer was used. The temperature of the reaction tube 1 is controlled by resistance heating means 4, and the temperature of the reaction tube 1 is controlled by a resistance heating means 4.
The source part was kept at 800°C, the high temperature region 11 of the upper reaction chamber 8 and the growth region 12 of the lower reaction chamber 9 were kept at 600°C, and the low temperature region 13 of the upper reaction chamber 8 was kept at 400°C. The gas flow conditions are as follows.

上段反応室 HCff      5  CC/m1n82    
 2.000 c c/m i n下段反応室 HCI (Ga)  5  cc/m1nAS83  
   5  CC/m1n82     2.000 
c c/rn i n先ず、エツチングの手順を示す。
Upper reaction chamber HCff 5 CC/m1n82
2.000 cc/m i lower reaction chamber HCI (Ga) 5 cc/m1n AS83
5 CC/m1n82 2.000
First, the etching procedure will be described.

基板結晶3を基板ホルダ2にセットし、上段反応室8の
低温領域13で所定温度(400℃)まで昇温した。そ
の温度に達したところでHCIを供給し、10秒間HC
Iを十分に吸着させたく第一の工程)。次に、HCIの
供給を止め、基板結晶3を高温領域11に移動しく第二
の工程)、10秒後再び基板結晶3を反応管下流の低温
領域13に移動した。これを−サイクルとして、ここで
は700サイクル行なった。一方、下段反応室9のGa
ソースに対しHCIを供給し、バイパスパイプ5からは
A s H3ガスと1×1018cm−3程度ドーピン
グするためのドーパントガスH2Sを供給した。上段反
応室8でのプロセスが終了したところで基板結晶3を下
役反応室9の成長領域12に移動し、GaAsを約20
00人の厚さに成長させた。成長結晶を調べた結果、最
初エツチングが行なわれ、その場所に高濃度ドーピング
層が再成長していることが判明した。出ころで、エツチ
ング深さの評価を行なったところ、GaAsは約200
0Aの厚さエツチングされて!J)ることがわかった。
The substrate crystal 3 was set in the substrate holder 2, and the temperature was raised to a predetermined temperature (400° C.) in the low temperature region 13 of the upper reaction chamber 8. When that temperature is reached, supply HCI and HC1 for 10 seconds.
The first step is to ensure sufficient adsorption of I). Next, the supply of HCI was stopped, and the substrate crystal 3 was moved to the high temperature region 11 (second step), and after 10 seconds, the substrate crystal 3 was again moved to the low temperature region 13 downstream of the reaction tube. This was defined as a -cycle, and 700 cycles were performed here. On the other hand, Ga in the lower reaction chamber 9
HCI was supplied to the source, and A s H3 gas and a dopant gas H2S for doping about 1×10 18 cm −3 were supplied from the bypass pipe 5 . When the process in the upper reaction chamber 8 is completed, the substrate crystal 3 is moved to the growth region 12 of the lower reaction chamber 9, and about 20% of GaAs is grown.
It grew to a thickness of 00 people. Examination of the grown crystal revealed that it had first been etched and a highly doped layer had regrown in its place. When we evaluated the etching depth at the exit point, it was found that GaAs was approximately 200
Etched to a thickness of 0A! J) It was found that

これは、−サイクルにほぼ一分子層がエツチングされて
いることを示している。
This indicates that approximately one monolayer was etched in the − cycle.

また、エピタキシャル層はヒルロック等の表面欠陥の非
常に少なく、鏡面性に優れたものであった。
Further, the epitaxial layer had very few surface defects such as hillocks and had excellent specularity.

更に、成長方向にキャリア濃度プロファイルを調べた結
果、エピタキシャル層と基板結晶の界面にキャリア濃度
の低下したディップ層も無かった。
Furthermore, as a result of examining the carrier concentration profile in the growth direction, there was no dip layer with a reduced carrier concentration at the interface between the epitaxial layer and the substrate crystal.

〔発明の効果〕〔Effect of the invention〕

以上述べたように、本発明によるI−V族化合物半導体
の気相エツチング装置を用いると、エツチング深さの一
分子層単位での精密な制御が可能となり、また、基板結
晶とエピタキシャル層界面を非常に急峻なものとするこ
とが出来る。
As described above, by using the vapor phase etching apparatus for IV group compound semiconductors according to the present invention, it is possible to precisely control the etching depth in units of one monolayer, and the interface between the substrate crystal and the epitaxial layer can be controlled precisely. It can be made very steep.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による実施例1を説明するための図で、
GaAs基板結晶表面を気相エツチングする場合に本発
明を適用した場合の気相エツチング装置の概略図である
。 第2図は本発明による実施例2を説明するための図で、
GaAS基板結晶を用いてエツチング−成長の連続プロ
セスを行なうための装置の概略図である。 第3図は従来のハイドライド法による気相エツチング装
置を説明するための図である。
FIG. 1 is a diagram for explaining Embodiment 1 according to the present invention,
1 is a schematic diagram of a vapor phase etching apparatus to which the present invention is applied when performing vapor phase etching on the crystal surface of a GaAs substrate. FIG. 2 is a diagram for explaining Embodiment 2 according to the present invention,
1 is a schematic diagram of an apparatus for performing a continuous etching-growth process using a GaAS substrate crystal; FIG. FIG. 3 is a diagram for explaining a conventional vapor phase etching apparatus using the hydride method.

Claims (1)

【特許請求の範囲】[Claims] (1)III−V族化合物半導体の気相エッチング装置に
おいて、反応管と、この反応管の内部に設けられ、基板
結晶を保持する移動可能な基板ホルダと、前記反応管の
外部に設けられ、反応管内部を温度傾斜を保って加熱す
る加熱手段とを備え、低温領域でハロゲンないしハロゲ
ン化水素ガスを基板結晶表面に吸着させ、高温領域でI
II−V族化合物半導体のIII族元素のハロゲン化物とし
て基板結晶表面からIII族元素を揮発させることを特徴
とするIII−V族化合物半導体の気相エッチング装置。
(1) In a vapor phase etching apparatus for III-V compound semiconductors, a reaction tube, a movable substrate holder provided inside the reaction tube and holding a substrate crystal, and provided outside the reaction tube, It is equipped with a heating means that heats the inside of the reaction tube while maintaining a temperature gradient, and adsorbs halogen or hydrogen halide gas to the substrate crystal surface in the low temperature region, and adsorbs I in the high temperature region.
A vapor phase etching apparatus for a III-V compound semiconductor, characterized in that a group III element is volatilized from a substrate crystal surface as a halide of a group III element of a group II-V compound semiconductor.
JP29257585A 1985-12-27 1985-12-27 Gaseous-phase etching device for iii-v compound semiconductor Granted JPS62153199A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29257585A JPS62153199A (en) 1985-12-27 1985-12-27 Gaseous-phase etching device for iii-v compound semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29257585A JPS62153199A (en) 1985-12-27 1985-12-27 Gaseous-phase etching device for iii-v compound semiconductor

Publications (2)

Publication Number Publication Date
JPS62153199A true JPS62153199A (en) 1987-07-08
JPH0355439B2 JPH0355439B2 (en) 1991-08-23

Family

ID=17783546

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29257585A Granted JPS62153199A (en) 1985-12-27 1985-12-27 Gaseous-phase etching device for iii-v compound semiconductor

Country Status (1)

Country Link
JP (1) JPS62153199A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02283018A (en) * 1989-01-31 1990-11-20 Matsushita Electric Ind Co Ltd Processing method of semiconductor base body and manufacture of semiconductor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02283018A (en) * 1989-01-31 1990-11-20 Matsushita Electric Ind Co Ltd Processing method of semiconductor base body and manufacture of semiconductor

Also Published As

Publication number Publication date
JPH0355439B2 (en) 1991-08-23

Similar Documents

Publication Publication Date Title
JPS6134929A (en) Growing device of semiconductor device
US20070141814A1 (en) Process for producing a free-standing iii-n layer, and free-standing iii-n substrate
JPS62188309A (en) Vapor growth method and equipment therefor
JPS62153199A (en) Gaseous-phase etching device for iii-v compound semiconductor
JPS62153198A (en) Method for gaseous-phase etching of iii-v compound semiconductor
JPS62153200A (en) Gaseous-phase etching device for iii-v compound semiconductor
JPH04160100A (en) Method for epitaxial-growing iii-v compound semiconductor
JPH0289313A (en) Cleaning nethod for silicon substrate surface
JPH0618189B2 (en) Method for vapor phase etching of group III-V compound semiconductor
JPH02230720A (en) Vapor growth method and apparatus for compound semiconductor
JPH0431391A (en) Epitaxial growth
JPH0630339B2 (en) Method for producing GaAs single crystal
JPS63182299A (en) Vapor growth method for iii-v compound semiconductor
JPH0232532A (en) Gaseous phase growth device
JPS61260622A (en) Growth for gaas single crystal thin film
JPS6134932A (en) Vapor growing process
JPH0243720A (en) Molecular beam epitaxial growth method
JPS63174314A (en) Method for doping iii-v compound semiconductor crystal
JP2000082673A (en) Thin-film formation method and device
JP2660182B2 (en) Method for manufacturing GaAs semiconductor device
JPH03159994A (en) Vapor-phase growth process of group iii-v compound semiconductor
JPH0222199A (en) Epitaxial growth method in vapor phase
JPS6134926A (en) Growing device of semiconductor single crystal
JP2753832B2 (en) III-V Vapor Phase Growth of Group V Compound Semiconductor
JP2620546B2 (en) Method for producing compound semiconductor epitaxy layer