JPS62152202A - Detection and integration circuit - Google Patents
Detection and integration circuitInfo
- Publication number
- JPS62152202A JPS62152202A JP60293707A JP29370785A JPS62152202A JP S62152202 A JPS62152202 A JP S62152202A JP 60293707 A JP60293707 A JP 60293707A JP 29370785 A JP29370785 A JP 29370785A JP S62152202 A JPS62152202 A JP S62152202A
- Authority
- JP
- Japan
- Prior art keywords
- amplifier
- integration
- offset
- output
- amplifiers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明ぽ入力信号が零の時、積分出力が積分時間に関係
なく一定に保たれる検波・積分回路に関するものである
。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a detection/integration circuit in which when the input signal is zero, the integral output is kept constant regardless of the integration time.
従来の技術
従来の検波・積分回路では、第２図に示すようなブロッ
ク溝底で同期検波・積分をすることがよく行われる。2. Description of the Related Art In conventional detection/integration circuits, synchronous detection/integration is often performed at the bottom of a block groove as shown in FIG.
ここでは、アンプ２１の出力を同期検波のためのスイン
チング動作を行うアンプ４の反転入力とオフセット検出
用の抵抗５の一端とに接続し、その抵抗の他端をアンプ
４の非反転入力、積分用コンデンサ６およびバッファ１
０の入力を接続し、アンプ４の出力をアンプ２１の非反
転入力と検波回路ホールド用コンデンサ３とに接続して
、同期検波・積分を行っていた。Here, the output of the amplifier 21 is connected to the inverting input of the amplifier 4 that performs the switching operation for synchronous detection and one end of the resistor 5 for offset detection, and the other end of the resistor is connected to the non-inverting input of the amplifier 4, capacitor 6 and buffer 1
0 input was connected, and the output of the amplifier 4 was connected to the non-inverting input of the amplifier 21 and the detection circuit hold capacitor 3 to perform synchronous detection and integration.
発明が解決しようとする問題点
このような従来の回路では、第２図に示すアンプ４にオ
フセットがあると、同アンプ４がオンしている状態でも
、積分用コンデンサ６にアンプ４のオフセント電圧１ｖ
。Ｓ、オフセット検出用の抵抗の抵抗値をＲとすると、
ｖｏｓ／Ｒの電流が流れ込むため、精度金製する積分や
、長時間の積分を行わせることが困難であった。Problems to be Solved by the Invention In such a conventional circuit, if there is an offset in the amplifier 4 shown in FIG. 1v
. S, and let R be the resistance value of the resistor for offset detection,
Since a current of vos/R flows in, it is difficult to perform precision integration or long-time integration.
本発明はかかる点に鑑みてなされたもので、精度を要す
る積分や長時間の積分が可能な検波・積分回路を提供す
ることを目的としている。The present invention has been made in view of these points, and an object of the present invention is to provide a detection/integration circuit that is capable of performing integration that requires precision and integration over a long period of time.
問題点を解決するための手段
本発明は上記問題点を解決するために、入力信号を反転
入力とする第１のオペアンプの入・出力に抵抗を接続し
、該出力を同期検波用アンプおよび抵抗を介して第２の
オペアンプに反転入力接続し、該同期検波用アンプの出
力を第１のオペアンプの非反転入力接続とし、かつ検波
回路ホールド用コンデンサ接続とし、他方、第２のオペ
アンプの反転入力と出力側にコンデンサを接続し、該出
力側を反転入力と出力側に接続した出力段バッファに接
続し、且つ積分用アンプの反転入力接続とし、かつ該積
分用アンプの出力を第２のオペアンプの非反転入力およ
びホールド用コンデンサに接続し、且つ上記同期検波用
アンプおよび積分用アンプの非反転入力端子を基準電圧
設定接続とする構成の検波・積分回路である。Means for Solving the Problems In order to solve the above problems, the present invention connects a resistor to the input/output of a first operational amplifier whose input signal is an inverted input, and connects the output to a synchronous detection amplifier and a resistor. The inverting input of the synchronous detection amplifier is connected to the non-inverting input of the first operational amplifier, and the detection circuit holding capacitor is connected to the inverting input of the second operational amplifier. A capacitor is connected to the output side, and the output side is connected to the output stage buffer connected to the inverting input and output side, and the inverting input of the integrating amplifier is connected, and the output of the integrating amplifier is connected to the second operational amplifier. The detection/integration circuit is connected to the non-inverting input of the synchronous detection amplifier and the holding capacitor, and the non-inverting input terminals of the synchronous detection amplifier and the integrating amplifier are connected to the reference voltage setting.
作用
本発明によると入力信号が零のとき、回路を構成するア
ンプにオフセットがあっても、積分出力が積分時間に関
係なく一定に保たれる。According to the present invention, when the input signal is zero, the integral output is kept constant regardless of the integration time even if there is an offset in the amplifiers forming the circuit.
実施例
第１図は本発明の検波・積分回路の一実施例を示すブロ
ック図である。第１図乙において、１は入力信号源、２
は入力信号全増幅するためのオペアンプ、３は検波回路
ホールド用コンデンサ、４は同期検波用アンプ、５はオ
フセット検出用抵抗、６は積分用コンデンサ、７は積分
回路を構成するオペアンプ、８は積分回路ホールド用コ
ンデンサ、９は積分用アンプ、１ｏは出力段のバッファ
アンプであり、同図すにおいて、１１は入力信号、１２
は同期検波用アンプ４へのスイッチング信号で入力信号
１１と同期している。１３は積分用アンプ９へのスイッ
チング信号、１４は出力電圧である。Embodiment FIG. 1 is a block diagram showing an embodiment of the detection/integration circuit of the present invention. In Figure 1 B, 1 is the input signal source, 2
is an operational amplifier for amplifying the entire input signal, 3 is a capacitor for holding the detection circuit, 4 is an amplifier for synchronous detection, 5 is a resistor for offset detection, 6 is a capacitor for integration, 7 is an operational amplifier forming the integration circuit, 8 is an integration 9 is an integrating amplifier, 1o is an output stage buffer amplifier, 11 is an input signal, 12 is a circuit hold capacitor, and 1o is an output stage buffer amplifier.
is a switching signal to the synchronous detection amplifier 4 and is synchronized with the input signal 11. 13 is a switching signal to the integrating amplifier 9, and 14 is an output voltage.
次に、本発明の回路について動作説明する。Next, the operation of the circuit of the present invention will be explained.
即ち、第１図に示すようにして、アンプ４とアンプ９が
オンの状態では検波回路ホールド用コンデンサ３がアン
プ２とアンプ４のオフセノトヲ補償するように働き、積
分回路ホールド用コンデンサ８がアンズブのオフセノト
ヲ補償するように働き、結果的に出力段バッファ１ｏに
現れる積分出力に関係するのけアンプ９のオフセット電
圧だけにするものである。That is, as shown in FIG. 1, when the amplifiers 4 and 9 are on, the detection circuit hold capacitor 3 works to compensate for the offset of the amplifiers 2 and 4, and the integrating circuit hold capacitor 8 works to compensate for the offset of the amplifiers 2 and 4. It works to compensate for the offset, and as a result, only the offset voltage of the amplifier 9 is related to the integrated output appearing at the output stage buffer 1o.
なお、アンプ９のオフセット電圧は積分出力への影響に
対して積分時間とは無関係にあるので長時間の積分が精
度よく行われる。Note that since the offset voltage of the amplifier 9 has no relation to the integration time with respect to its influence on the integrated output, long-term integration is performed with high precision.
また、アンプ４とアンプ９が、オフの状態になったとき
にはそれぞれの出力に接続されているホールド用コンデ
ンサが電位を記憶し、この状態でもアンプ４とアンプ９
がオンのときと同じようにそれぞれのアンプのオフセク
トが補償されている。Furthermore, when the amplifier 4 and the amplifier 9 are turned off, the hold capacitors connected to their respective outputs memorize the potential, and even in this state, the amplifier 4 and the amplifier 9
The offset of each amplifier is compensated in the same way as when is on.
従って精度よく同期検波・積分が行われる。Therefore, synchronous detection and integration can be performed with high precision.
発明の効果
以上述べてきたように、本発明によれば、構成するアン
プのオフセットに関係なく精度のよい積分が行え、しか
も、半導体集積回路に適用しても容易に実現できて実用
的にきわめて有用である。Effects of the Invention As described above, according to the present invention, highly accurate integration can be performed regardless of the offset of the constituent amplifiers, and it is also easily realized even when applied to semiconductor integrated circuits, making it extremely practical. Useful.
分目路を示すブロック図である。
１・・・・・・入力信号源、２・・・・・・オペアンプ
、３・・・・・検波回路ホールド用コンデンサ、４・・
・・・同期検波用アンプ、５・・・・・オフセット検出
用抵抗、６・川・・積分用コンデンサ、７・・・・・・
オペアンプ、８・・・・・積分回路ホールド用コンデン
サ、９・・・・・積分用アンプ、１０・・・・・・出力
段のバッフ７．１１・・・・入力信号、１２・・・・・
・スイッチング信号、１３・甲・・スイッチング信号、
１４・・・・・・出力信号。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名１−
ｍ−人力１ｉ弊気
２−−一不１＠アンア
３−一一オ１５及回−シＪ１−ルド弔フンヂンヴ七−月
剪り東方用アン７゜
５−−７７巳、卜矛忙亡用考乏、硫
８−−−郭１定ＴｉＪ工（ムールト弔Ｊンテ′ンブｑ−
−−−１７し７゜
ｔｏ−−−）Ｂ乃↓ンめ八−７ファ
イＩ−−−７＼力（Ｔで１
＋２−４１’ｌス４．／ ＋ｎ’（詩
ＩＵ−−−９１／ｌ 、。
＋４−一−ｔカ電、ｔ
？ −−−、＞、刀１官１５ツ
ｍ ２ 図
３−−−：ｔ、−・乙し弔っンテンて４−−
″；ｌ英月鋤祖アン７゜
５−− Ｔ７り、ＬＺ峠と恵ン（コ杷
６−−−丁１９・弔几チー、−
（Ｄ−−一七乃よ’に／ｌｌバッフ
ァｆ−−−７ン７゛
９１−一−ス６ッナ５ｆ回！１It is a block diagram showing a branch path. 1... Input signal source, 2... Operational amplifier, 3... Capacitor for holding the detection circuit, 4...
... Amplifier for synchronous detection, 5 ... Resistor for offset detection, 6 ... Capacitor for integration, 7 ......
Operational amplifier, 8... Integrating circuit hold capacitor, 9... Integrating amplifier, 10... Output stage buffer 7.11... Input signal, 12...・
・Switching signal, 13・A...Switching signal,
14...Output signal. Name of agent: Patent attorney Toshio Nakao and 1 other person1-
m-human power 1i evil spirit 2--ichifu 1@an-a 3-11o 15 times-si J1-rudo condolence hunjinv July pruning for the east 7゜5--77 Sn, Bakugo busy death use Thoughtful, Sulfur 8 --- Guaranteed TiJ Engineering
---17 し7゜to----) Bno↓nme8-7phiI---7\force (1 in T +2-41'lsu4./+n' (poetry IU---91 /l,.+4-1-tkaden,t? ---,>, sword 1 official 15 m 2 figure
3---:t,--・I'm sorry for the inconvenience 4--
'';l Yinggetsu Souan 7゜5-- T7ri, LZ Pass and Een (Ko 6---Ding 19, condolence Qi, - (D--17noyo'/ll buffer f ---7n7゛91-1-s6nna5f times!1
Claims (1)
もに、同第１のオペアンプの反転入力端子−出力端子間
を抵抗接続し、前記第１のオペアンプの出力端子を第２
のオペアンプの反転入力端子に接続し、前記第２のオペ
アンプの出力端子を第１コンデンサと共に前記第１のオ
ペアンプの非反転入力端子に接続し、前記第１のオペア
ンプの出力端子を、抵抗を介して、第３のオペアンプの
反転入力端子に接続し、前記第３のオペアンプの出力端
子−反転入力端子間に第２コンデンサを介在し、前記第
３のオペアンプの出力端子を第４のオペアンプの反転入
力端子に接続し、前記第４のオペアンプの出力端子を第
３コンデンサと共に前記第３のオペアンプの非反転入力
端子に接続し、前記第３のオペアンプの出力をバッファ
増幅器を通して取り出す構成の検波・積分回路。A signal is input to the inverting input terminal of the first operational amplifier, and a resistor is connected between the inverting input terminal and the output terminal of the first operational amplifier, and the output terminal of the first operational amplifier is connected to the second operational amplifier.
The output terminal of the second operational amplifier is connected together with a first capacitor to the non-inverting input terminal of the first operational amplifier, and the output terminal of the first operational amplifier is connected to the non-inverting input terminal of the first operational amplifier through a resistor. A second capacitor is interposed between the output terminal and the inverting input terminal of the third operational amplifier, and the output terminal of the third operational amplifier is connected to the inverting input terminal of the fourth operational amplifier. the output terminal of the fourth operational amplifier is connected to the non-inverting input terminal of the third operational amplifier together with a third capacitor, and the output of the third operational amplifier is taken out through a buffer amplifier. circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60293707A JPS62152202A (en) | 1985-12-26 | 1985-12-26 | Detection and integration circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60293707A JPS62152202A (en) | 1985-12-26 | 1985-12-26 | Detection and integration circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62152202A true JPS62152202A (en) | 1987-07-07 |
Family
ID=17798190
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60293707A Pending JPS62152202A (en) | 1985-12-26 | 1985-12-26 | Detection and integration circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62152202A (en) |
-
1985
- 1985-12-26 JP JP60293707A patent/JPS62152202A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US3820033A (en) | Mos-fet sample and hold system for digitizing high frequency signals | |
| JPS61164338A (en) | Multiplex arithmetic type digital-analog converter | |
| US3586989A (en) | Time shared amplifiers | |
| KR830001935B1 (en) | Voltage comparator | |
| KR940003172A (en) | Transconductance cell | |
| KR930000820B1 (en) | Sample and hold circuit | |
| US3679989A (en) | Clamp circuit for preventing saturation of operational amplifier | |
| KR950005172B1 (en) | Three-terminal op amplifier | |
| JPS62152202A (en) | Detection and integration circuit | |
| US4634996A (en) | Operational amplifier | |
| GB1490257A (en) | Multi-stage differential amplifier circuit with means for compensating the temperature drift of a constant current source transistor | |
| JPS5566110A (en) | Amplifier circuit | |
| JPS57203296A (en) | Sample holding circuit | |
| JPS63311700A (en) | Sample-and-hold circuit | |
| GB1105184A (en) | Improvements in or relating to parametric amplifiers | |
| GB1333287A (en) | Pure nonlinear transfer circuit | |
| SU1019633A1 (en) | Electronic switching device for analog signals | |
| JPS57162185A (en) | Sample holding circuit | |
| SU1469544A1 (en) | Power amplifier | |
| GB675268A (en) | Improvements in d.c. amplifying systems | |
| SU1427306A1 (en) | Voltage calibrating resistance box | |
| SU738168A1 (en) | Mds-transistor- based multistage switching apparatus | |
| SU1171981A1 (en) | Linear voltage-to-current converter | |
| US6166578A (en) | Circuit arrangement to compensate non-linearities in a resistor, and method | |
| JPH0546090Y2 (en) |