JPS62152134A - Semiconductor device with internal matching circuit - Google Patents

Semiconductor device with internal matching circuit

Info

Publication number
JPS62152134A
JPS62152134A JP60296404A JP29640485A JPS62152134A JP S62152134 A JPS62152134 A JP S62152134A JP 60296404 A JP60296404 A JP 60296404A JP 29640485 A JP29640485 A JP 29640485A JP S62152134 A JPS62152134 A JP S62152134A
Authority
JP
Japan
Prior art keywords
matching circuit
semiconductor chip
bonded
electrode leads
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60296404A
Other languages
Japanese (ja)
Inventor
Takeshi Suzuki
武 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP60296404A priority Critical patent/JPS62152134A/en
Publication of JPS62152134A publication Critical patent/JPS62152134A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H01L2924/30111—Impedance matching

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To bond the electrode leads of the semiconductor chip mounted upside down at constant intervals without relying on the perception and experience of operators and to adjust the capacitance by splitting the bonding parts, whereon the electrode leads are bonded, into a number larger than the number of the bonding parts. CONSTITUTION:Dielectric substrates 2 for matching circuit, which performed a matching of the input/output impedance and external impedance of a semiconductor chip 1, are installed on a package 5, then the semiconductor chip 1 is bonded on the package 5. Then, the prescribed number of second electrode leads 7 are bonded on bonding patterns 3a splitted into the number more than that of the bonding parts 9 on the substrates 2. In case adjustment of the capacitance is necessary, the patterns 3a are trimmed the desired number before the second electrode leads 7 are bonded, then the second electrode leads 7 are bonded on the patterns 3a.

Description

【発明の詳細な説明】 〔虚業上の利用分野〕 装置に係り１、符に整合回路上の半導体チップ電極ボン
ディング部のポンディング形態の改良番こ関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Field of Application] The present invention relates to an apparatus, and the first aspect relates to an improvement in the bonding form of a semiconductor chip electrode bonding portion on a matching circuit.

〔従来の技術〕[Conventional technology]

高周波半導体装置において、牛４体チップのインピダン
スが低くなると外部回路との整合が難しくなるため、半
導体チップの近傍に整合回路を設けた内部整合回路付半
導体装置が連成採用されている。この半導体装置におい
て高周波での寄生要素、特にリードのインダクタンスを
極力小さくするために、半導体チップをアップサイヒダ
９ンでマウントする方法が用いられている。In high-frequency semiconductor devices, if the impedance of the four-body chip becomes low, it becomes difficult to match it with an external circuit, so a semiconductor device with an internal matching circuit in which a matching circuit is provided near the semiconductor chip is used in combination. In this semiconductor device, in order to minimize parasitic elements at high frequencies, particularly lead inductance, a method is used in which the semiconductor chip is mounted with an upside fold.

第２図は従来のアップサイトダウン半導体チップマウン
ト方式番こよる内部整合形半導体装［伍を示す平面図で
あり、図において、（１）はアップサイドダウンにマウ
ントされた半導体チップ、（２）は整合回路用誘電体基
板、（３）は半導体チップ（１）の電１愼リードボンデ
ィング部と容はとを兼ね屑えるように螢合回路基板（２
）上に設けられたボンデイングバタ−ン、（４）は容重
パターン、（５）は半導体チップ（１）と整合回路が構
成された整合回路基板（２）とを装着するパッケージ（
またはキャリヤ）、　（６）はＡｕリホン等からなる＄
１の電極リード、（７）は整合回路パターンとボンディ
ングされる第２の電極リード、（８）ハＡｕワイヤから
なリボンティングパター７　（３ａ）　（！：８　ｔ　
パターン（４）とを接続するインダクタンス、（９）（
・印で示す）はボンデづングパターン（３）と第２の電
極リード（７）とのボンディング部、α０はパッケージ
（またはキャリヤ）（５）のリートボンデ１フフ部であ
る。FIG. 2 is a plan view showing an internally matched semiconductor device according to the conventional up-side-down semiconductor chip mounting method. In the figure, (1) is a semiconductor chip mounted upside-down, (2) (3) is a dielectric substrate for a matching circuit, and (3) is an integrated circuit board (2) which also serves as the electrical lead bonding part of the semiconductor chip (1) and can be discarded.
), (4) is a weight pattern, and (5) is a package (5) on which a semiconductor chip (1) and a matching circuit board (2) on which a matching circuit is configured are attached.
or carrier), (6) is made of Au silicon, etc.
1 electrode lead, (7) a second electrode lead bonded to the matching circuit pattern, and (8) a rebonding pattern 7 made of Au wire. (3a) (!:8 t
Inductance connecting pattern (4), (9) (
. . ) is the bonding part between the bonding pattern (3) and the second electrode lead (7), and α0 is the bonding part of the package (or carrier) (5).

第２図を用いて半導体装置の組立方法について説明する
。半導体チップ゛（１）の人出力インピーダンスと外部
１ンビーダンスとのｍ　ｈをとった整合回路用誘電体基
板（２）をパンケージ（５）に装置し、その後半導体チ
ップ（１）をパンケージ（５）にダイボンドすると共に
、整合回路用誘電体基板（２）上のボンディングパター
ン（３）へ第２の電極リード（７）を所定数ボンディン
グする。A method for assembling a semiconductor device will be explained using FIG. A dielectric substrate (2) for a matching circuit, which has a m h difference between the human output impedance of the semiconductor chip (1) and the external impedance, is installed in the pan cage (5), and then the semiconductor chip (1) is placed in the pan cage (5). At the same time, a predetermined number of second electrode leads (7) are bonded to the bonding pattern (3) on the matching circuit dielectric substrate (2).

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の内部整合回路付半導体装置は以上の様に組立、構
成されているので、所定数のボンディングを実施する際
、ボンディング位置１量隔は作業者の勘と経験で行うこ
とが必要で、素子毎にばらつきを生じるのが問題点であ
った。Conventional semiconductor devices with internal matching circuits are assembled and configured as described above, so when performing a predetermined number of bondings, it is necessary to determine the bonding position at intervals of one amount based on the operator's intuition and experience. The problem was that there were variations from case to case.

この発明は上記のような問題点を解消するためになされ
たもので、ボンディング位置を作業者の勘と経験にたよ
ることなく一定の間隔でボンディングできるとともに、
容量調整もできる内部整合回路付半導体装置を得ること
を目的とする。This invention was made to solve the above-mentioned problems, and allows bonding to be performed at regular intervals without relying on the operator's intuition and experience in determining the bonding position.
The object of the present invention is to obtain a semiconductor device with an internal matching circuit that can also adjust the capacitance.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る内部整合付半導体装置は整合回路パター
ンにおいて、半導体チップ成極リードボンディング部ボ
ンディングパターンをボンディング数以上に分割したも
のである。A semiconductor device with internal matching according to the present invention has a matching circuit pattern in which a semiconductor chip polarization lead bonding part bonding pattern is divided into more than the number of bonds.

〔作　用〕[For production]

この発明では半導体チップ電極リードポンディング部ボ
ンディングパターンを当該ボンディング数以上に分割し
たので、その分割された各部の内、定められたものにつ
いて各１個所ずっ半導体チップの第２の成極リードとボ
ンディングすれば、作業者の個人差もなくなり、素子相
互間も均一になる。In this invention, the bonding pattern of the semiconductor chip electrode lead bonding part is divided into more than the number of bonding parts, so that one predetermined part of each divided part is connected to the second polarization lead of the semiconductor chip. This eliminates individual differences among workers and makes the elements uniform.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の一実施例を図について説明する。第１
図において、第２図の従来例と同一符号は同一、又は相
当部分を示しており、（３ａ）はボンディング数以上に
所定の面積に分割したボンディングパターンである。An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, the same reference numerals as in the conventional example in FIG. 2 indicate the same or corresponding parts, and (3a) is a bonding pattern divided into predetermined areas larger than the number of bondings.

半導体チップＣ１１の入出力インピーダンスと外部イン
ピーダンスとの整合をとった整合回路用誘電体基板（２
）をパッケージ（５）Ｉこ装着し、その後半導体チップ
（１）をパッケージ（５）にダイボンドし、その後整合
回路用誘電体基板（２）上のボンディング数以上に分別
されたボンディングパターン（３ａ）へ第２のＩ電極リ
ード（７）を所定数ボンディングする。容址調ヱか必要
な場合には第２の電極！Ｊ　−ト’（７）をボンディン
グする前に、ボンディングパターン（３ａ）ヲ所望数ト
リミングし、その後に第２の４極り一層（７）をボンデ
ィングパターン（３ａ）にボンディングスル。A matching circuit dielectric substrate (2) that matches the input/output impedance of the semiconductor chip C11 and the external impedance.
) is attached to the package (5), and then the semiconductor chip (1) is die-bonded to the package (5), and then the bonding pattern (3a) separated into more than the number of bonds on the matching circuit dielectric substrate (2) is attached. A predetermined number of second I electrode leads (7) are bonded to. A second electrode if necessary! Before bonding the J-to' (7), the bonding pattern (3a) is trimmed a desired number of times, and then the second quadrupole layer (7) is bonded to the bonding pattern (3a).

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば歪合回路パターン上の
ボンティングパターンを半導体チップの電極リードをボ
ンディング数以上に分割して構成したので、ボンディン
グ位置が常に一定になり、作業性の向上と品質の同上が
図れると共に容量調整も６エ能となり歩留も向上すると
いう効果がある。As described above, according to the present invention, the bonding pattern on the distortion circuit pattern is constructed by dividing the electrode leads of the semiconductor chip into more than the number of bondings, so the bonding positions are always constant, which improves workability. This has the effect of not only improving quality but also increasing capacity adjustment and improving yield.

【図面の簡単な説明】 第１図はこの発明の一実施例による人出力インピーダン
ス内部整合回路付半導体装置の平面図、第２図は従来の
入出力インピーダンス内部（合回路付半導体装置の平面
図である。 図において、（１）は半導体チップ、（２）は整合回路
用誘電体基板、（３ａ）はボンディング部（ボンデイン
クパターン）　、＋４）は容量パターン、（５）＋；ｔ
パンケージ、（７）は電極リード、（８）はインダクタ
ンスである０ なＳ、図中同一符号は同一、または相当部分を示す。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view of a semiconductor device with an internal matching circuit for human output impedance according to an embodiment of the present invention, and FIG. 2 is a plan view of a conventional semiconductor device with internal input/output impedance (combiner circuit) In the figure, (1) is a semiconductor chip, (2) is a dielectric substrate for matching circuit, (3a) is a bonding part (bond ink pattern), +4) is a capacitor pattern, (5) +;
A pan cage, (7) an electrode lead, (8) an inductance of 0 S, and the same reference numerals in the drawings indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] （１）金（Ａｕ）リボンからなる電極リードを有する半
導体チップと、 入出力インピーダンス内部整合回路を構成する容量及び
インダクタンスと、上記電極リードがボンディングされ
るボンディング部とが上に形成された整合回路用誘電体
基板と、 上記半導体チップと上記整合回路用誘電体基板とを装着
するパツケージ（またはキャリヤ）からなるものにおい
て、 アップサイドダウンにマウントされた上記半導体チップ
の電極リードがボンディングされる上記ボンディング部
が当該ボンディング数以上の数に分割されていることを
特徴とする内部整合回路付半導体装置。(1) A matching circuit formed on a semiconductor chip having electrode leads made of gold (Au) ribbons, capacitance and inductance forming an input/output impedance internal matching circuit, and a bonding portion to which the electrode leads are bonded. and a package (or carrier) for mounting the semiconductor chip and the matching circuit dielectric substrate, the bonding to which the electrode leads of the semiconductor chip mounted upside down are bonded. 1. A semiconductor device with an internal matching circuit, characterized in that the portion is divided into a number equal to or greater than the number of bondings.
JP60296404A 1985-12-25 1985-12-25 Semiconductor device with internal matching circuit Pending JPS62152134A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60296404A JPS62152134A (en) 1985-12-25 1985-12-25 Semiconductor device with internal matching circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60296404A JPS62152134A (en) 1985-12-25 1985-12-25 Semiconductor device with internal matching circuit

Publications (1)

Publication Number Publication Date
JPS62152134A true JPS62152134A (en) 1987-07-07

Family

ID=17833107

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60296404A Pending JPS62152134A (en) 1985-12-25 1985-12-25 Semiconductor device with internal matching circuit

Country Status (1)

Country Link
JP (1) JPS62152134A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0247673A (en) * 1988-08-09 1990-02-16 Mita Ind Co Ltd Shifting device for transfer paper in image forming device
JP2007232257A (en) * 2006-02-28 2007-09-13 Misawa Homes Co Ltd Building with ventilating tower
WO2011148819A1 (en) 2010-05-28 2011-12-01 日本碍子株式会社 Impedance matching element

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0247673A (en) * 1988-08-09 1990-02-16 Mita Ind Co Ltd Shifting device for transfer paper in image forming device
JP2007232257A (en) * 2006-02-28 2007-09-13 Misawa Homes Co Ltd Building with ventilating tower
WO2011148819A1 (en) 2010-05-28 2011-12-01 日本碍子株式会社 Impedance matching element
US8878625B2 (en) 2010-05-28 2014-11-04 Ngk Insulators, Ltd. Impedance matching device

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