JPS62151055A - Timing clock control system - Google Patents

Timing clock control system

Info

Publication number
JPS62151055A
JPS62151055A JP60290780A JP29078085A JPS62151055A JP S62151055 A JPS62151055 A JP S62151055A JP 60290780 A JP60290780 A JP 60290780A JP 29078085 A JP29078085 A JP 29078085A JP S62151055 A JPS62151055 A JP S62151055A
Authority
JP
Japan
Prior art keywords
output
multiplier
signal
frequency
oscillator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60290780A
Other languages
Japanese (ja)
Inventor
Atsushi Yoshida
厚 吉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60290780A priority Critical patent/JPS62151055A/en
Publication of JPS62151055A publication Critical patent/JPS62151055A/en
Pending legal-status Critical Current

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  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To facilitate the control of a timing clock even for a multipoint and low roll-off ratio QAM signal by using a carrier phase of the QAM signal estimated by deciding a QAM orthogonal amplitude modulation signal and a one-frequency pilot signal. CONSTITUTION:A multiplier 101 multiplies an input signal 10 with an output of an oscillator 102 of an oscillation frequency f1 to apply quasi-synchronization detection in a data MODEM receiver receiving the QAM signal of a carrier frequency f1 attended with a pilot signal of frequency f2. The output of the multiplier 101 is decided by a complex number decider 103 and a phase detector 104 extracts a carrier phase shift by the result of decision and a complex number signal before the decision. The pilot signal 20 uses the multiplier 105 and is multiplied with the output of the oscillator 106 whose oscillation frequency f2 to apply the quasi-synchronization detection. The multiplier 105 outputs the phase detector 104 are given to a phase detector 107, where the difference between phase shifts is detected and its output controls the frequency of the oscillator 108 to obtain a timing clock.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はQAM (quadrature ampli
tudemodulation :直交振幅変調)方式
のデータモデムのタイミングクロック制御方式に関する
[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to QAM (quadrature amplifier).
The present invention relates to a timing clock control method for a data modem using a quadrature amplitude modulation (tudemodulation) method.

〔従来の技術〕[Conventional technology]

従来、 QAM方式のデータモデムのタイミングクロッ
ク制御方式としては、復調出力に2乗或いは全波整流な
どの非線形演算を行ない、タイミングクロック周波数の
線スペクトラムを発生させた後。
Conventionally, the timing clock control method for a QAM data modem involves performing nonlinear calculations such as square or full-wave rectification on the demodulated output to generate a line spectrum of the timing clock frequency.

狭帯域フィルタにて、これを抽出する方式が用いられて
きた。
A method of extracting this using a narrowband filter has been used.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のタイミングクロック制御方式は。 The conventional timing clock control method mentioned above is as follows.

伝送速度の高速化に伴ない、データ点配置がより多点に
なり、更にロールオフ率が低下するに従って抽出が困難
になるという欠点がある。
As the transmission speed increases, the data point arrangement becomes more numerous, and as the roll-off rate decreases, extraction becomes difficult.

上述の欠点を除去するものとして、 QAM信号に2種
の周波数の/−PイPヮト信号を挿入し、これら2種の
ノぐイロット信号よりタイミングクロックを制御すると
いう方式がある。
In order to eliminate the above-mentioned drawbacks, there is a method in which /-PIP signals of two types of frequencies are inserted into the QAM signal, and the timing clock is controlled by these two types of pilot signals.

しかしながら、この方式は通常のデータを伝送するQA
M信号が占有する帯域の他に、2つのパイロット信号が
占有する帯域が必要となるために。
However, this method is not suitable for QA which transmits normal data.
This is because in addition to the band occupied by the M signal, a band occupied by the two pilot signals is required.

より広い周波数帯域幅が必要となり不利である。A wider frequency bandwidth is required, which is disadvantageous.

本発明の目的は、上述した欠点を除去し、多点。The purpose of the present invention is to eliminate the above-mentioned drawbacks and achieve multiple points.

低ロールオフ率のQAM信号でも、それに1種のパイロ
ット信号を付加するだけで、容易にタイミングクロック
の制御を行なうことができるタイミングクロック制御方
式を提供することにある。
It is an object of the present invention to provide a timing clock control system that can easily control the timing clock even for a QAM signal with a low roll-off rate by simply adding one type of pilot signal to it.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、−周波数のパイロット信号と、 QAM信号
を判定することにより推定されるQAM信号の搬送波位
相とを使用してタイミングクロックを制御する方式であ
る。
The present invention is a method of controlling a timing clock using a pilot signal of -frequency and a carrier wave phase of a QAM signal estimated by determining the QAM signal.

本発明によれば9周波数12のパイロット信号を伴なっ
て送信される。搬送波周波数11のQAM信号を受信す
るデータモデム受信機において2発振周波数がflであ
る第1の発振器と、該第1の発振器出力と受信QAM信
号を乗する第1の乗算器と、該第1の乗算器の出力を複
素平面上で領域判定を行なう複素判定器と、該複素判定
器の出力及び前記第1の乗算器の出力より複素平面上で
の位相を得る第1の位相検出器と1発振周波数が12で
ある第2の発振器と、該第2の発振器出力と受信パイロ
ット信号を乗する第2の乗算器と、該第2の乗算器の出
力位相及び前記第1の位相検出器の出力位相を比較する
第2の位相検出器と、該第2の位相検出器出力により発
振周波数が制御される第3の発掘器とを備え、前記第3
の発振器出力を系のタイミングクロックとすることを特
徴とするタイミングクロック制御方式が得られる。
According to the present invention, the signal is transmitted with pilot signals of 9 frequencies and 12. A data modem receiver that receives a QAM signal with a carrier frequency of 11 includes: a first oscillator whose oscillation frequency is fl; a first multiplier that multiplies the output of the first oscillator by the received QAM signal; a first phase detector that obtains a phase on the complex plane from the output of the complex decider and the output of the first multiplier; a second oscillator with an oscillation frequency of 12; a second multiplier that multiplies the second oscillator output by a received pilot signal; and an output phase of the second multiplier and the first phase detector. and a third excavator whose oscillation frequency is controlled by the output of the second phase detector,
A timing clock control method is obtained in which the output of the oscillator is used as the timing clock of the system.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の方式によるデータモデム受信機を示す
ブロック図である。本データモデム受信機は2周波数f
2の・ぐイロット信号を伴なって送信される。搬送波周
波数ftのωM倍信号受信するものである。本データモ
デム受信機は、第1の乗算器101は入力のQAM信号
10と1発振周波数がf+である第1の発振器102の
出力とを。
FIG. 1 is a block diagram illustrating a data modem receiver according to the present invention. This data modem receiver has two frequencies f
It is transmitted with the second pilot signal. It receives a signal with a carrier frequency ft multiplied by ωM. In this data modem receiver, a first multiplier 101 receives an input QAM signal 10 and an output from a first oscillator 102 whose oscillation frequency is f+.

乗算する事により、準同期検波を行なう。第1の乗算器
101の出力は、搬送波位相ずれを被ったベースバンド
信号であるが、搬送波成分を含んでいないので、このま
までは劣化量を抽出することはできない。第1の乗算器
101の出力は複素判定器103により判定され、この
判定結果及び判定前の複素信号、すなわち第1の乗算器
101の出力より、第1の位相検出器104により搬送
波位相ずれを抽出する。
By multiplying, quasi-synchronous detection is performed. The output of the first multiplier 101 is a baseband signal subjected to a carrier wave phase shift, but since it does not include a carrier wave component, the amount of deterioration cannot be extracted as is. The output of the first multiplier 101 is determined by the complex determiner 103, and based on this determination result and the complex signal before determination, that is, the output of the first multiplier 101, the carrier phase shift is determined by the first phase detector 104. Extract.

一方、パイロット信号20は、第2の乗算器105によ
り2発撮周波数が12である第2の発振器106の出力
と2乗算されて準同期検波を行なう。第2の乗算器10
5はノ4イロット信号の位相ずれを出力する。第2の乗
算器105の出力と。
On the other hand, the pilot signal 20 is multiplied by the output of the second oscillator 106 whose two-shot frequency is 12 by a second multiplier 105 to perform quasi-synchronous detection. second multiplier 10
5 outputs the phase shift of the No. 4 pilot signal. and the output of the second multiplier 105.

第1の位相検出器104の出力は、第2の位相検出器1
07によって、それぞれの位相ずれの差を検出し、その
位相差出力により第3の発振器108の周波数を制御し
、タイミングクロックとする。
The output of the first phase detector 104 is transmitted to the second phase detector 1
07, the difference between the respective phase shifts is detected, and the frequency of the third oscillator 108 is controlled by the output of the phase difference, which is used as a timing clock.

〔発明の効果〕〔Effect of the invention〕

以上説明したように2本発明は、従来の方式ではタイミ
ングクロックの制御が困難であった多点。
As explained above, the present invention provides multi-point timing clock control, which is difficult to control using conventional methods.

低ロールオフ率のQAM信号でも、それに一種のパイロ
ット信号を付加するだけで、容易にタイミングクロック
の制御ができるようになるという効果がある。
Even with a QAM signal having a low roll-off rate, the timing clock can be easily controlled simply by adding a type of pilot signal to it.

【図面の簡単な説明】 第1図は本発明の方式によるデータモデム受信機を示す
ブロック図である。 図において。 101・・・第1の乗算器、102・・・第1の発掘器
。 103・・・複素判定器、104・・・第1の位相検出
器。 105・・・第2の乗算器、106・・・第2の発振器
。 107・・・第2の位相検出器、108・・・第3の発
振器である。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram illustrating a data modem receiver according to the present invention. In fig. 101...first multiplier, 102...first excavator. 103... Complex determiner, 104... First phase detector. 105...Second multiplier, 106...Second oscillator. 107...Second phase detector, 108...Third oscillator.

Claims (1)

【特許請求の範囲】[Claims] 1、周波数f_2のパイロット信号を伴なって送信され
る、搬送波周波数f_1のQAM信号を受信するデータ
モデム受信機において、発振周波数がf_1である第1
の発振器と、該第1の発振器出力と受信QAM信号を乗
ずる第1の乗算器と、該第1の乗算器の出力を複素平面
上で領域判定を行なう複素判定器と、該複素判定器の出
力及び前記第1の乗算器の出力より複素平面上での位相
を得る第1の位相検出器と、発振周波数がf_2である
第2の発振器と、該第2の発振器出力と受信パイロット
信号を乗する第2の乗算器と、該第2の乗算器の出力位
相及び前記第1の位相検出器の出力位相を比較する第2
の位相検出器と、該第2の位相検出器出力により発振周
波数が制御される第3の発振器とを備え、前記第3の発
振器出力を系のタイミングクロックとすることを特徴と
するタイミングクロック制御方式。
1. In a data modem receiver that receives a QAM signal of carrier frequency f_1 transmitted with a pilot signal of frequency f_2, the first one whose oscillation frequency is f_1
an oscillator, a first multiplier that multiplies the output of the first oscillator by a received QAM signal, a complex determiner that performs area determination on a complex plane of the output of the first multiplier, and a first phase detector that obtains the phase on the complex plane from the output and the output of the first multiplier; a second oscillator whose oscillation frequency is f_2; a second multiplier that compares the output phase of the second multiplier and the output phase of the first phase detector;
and a third oscillator whose oscillation frequency is controlled by the output of the second phase detector, and the output of the third oscillator is used as a system timing clock. method.
JP60290780A 1985-12-25 1985-12-25 Timing clock control system Pending JPS62151055A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60290780A JPS62151055A (en) 1985-12-25 1985-12-25 Timing clock control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60290780A JPS62151055A (en) 1985-12-25 1985-12-25 Timing clock control system

Publications (1)

Publication Number Publication Date
JPS62151055A true JPS62151055A (en) 1987-07-06

Family

ID=17760413

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60290780A Pending JPS62151055A (en) 1985-12-25 1985-12-25 Timing clock control system

Country Status (1)

Country Link
JP (1) JPS62151055A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04123554A (en) * 1990-09-13 1992-04-23 Matsushita Electric Ind Co Ltd Data transmitter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04123554A (en) * 1990-09-13 1992-04-23 Matsushita Electric Ind Co Ltd Data transmitter

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