JPS62150485A - Image information converting circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for partial scanning conversion and to eliminate the need also for the control of split processing by storing parallel image information in a memory in the unit of dot. CONSTITUTION:The parallel image information stored in a shift register 1 synchronously with a clock from an oscillation circuit 3 is converted into serial image information and the result is written on a memory 2. A dot information address of the serial image information is generated by a counter 4 and a write address on the memory 2 is generated by a memory switching means 5 while being addressed in the unit of dot. At read instruction, the serial image information from the memory 2 is stored in the shift register 1 while being shifted. The dot address information is generated in the same way as the write.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a data conversion circuit for image information, and more particularly to a conversion process for converting horizontally scanned parallel image information into vertically scanned parallel image information.

(Prior Art) Conventionally, data conversion of image information in the serial dot printer head of this building was performed by an image data conversion circuit shown in FIG. In Figure 8,
301 is a counter, 3031 to 3034 are shift registers, 307i is a data trigger circuit, 408.4
13 are parallel image data buses.

In FIG. 3, several dots of shift register 303
1 to 3034 are loaded with parallel image information that is continuous in a direction perpendicular to the scanning direction via parallel image data 408. This information is shifted out one bit at a time while being synchronized with the synchronizing signal on the signal line 414, and stored in the data latch circuit 307. The second parallel image information, which differs in scanning direction by 90 degrees from the original image information, is transferred to the parallel image data bus 413.
created above. As a result, the shift registers 3031 to 303 are transferred via the parallel image data bus 408.
4 parallel image information is loaded. A synchronization signal for parallel image information on parallel image data bus 408 is sent to counter 301 via signal line 400. Thereby, load control signals generated by counting are transmitted from the counter 301 to the shift registers 3031 to 3034 via signal lines 403 to 406, respectively.

(Problems to be Solved by the Invention) The conventional image information conversion circuit described above requires a number of shift registers corresponding to the number of print heads of a serial dot printer. Therefore, in order to scan-convert a large image, the image must be divided and scan-converted in parts.

Therefore, there is a drawback that a memory area is required to store both the parallel image information before conversion and the parallel image information after conversion, and it is also necessary to control the division process of the image information.

The object of the invention is to convert parallel image information to serial image information, store the image information in dot units, count clocks in response to requests for writing or reading parallel image information, and perform write/successive operations. By switching and latching the address, the above drawback is eliminated, and partial scan conversion is not required.
An object of the present invention is to provide an image information conversion circuit configured so that control of division processing is not required.

(Means for Solving the Problems) An image information conversion circuit according to the present invention includes a shift register, a memory, an oscillation circuit, a counter, a memory address switching means, and a write/continuous address latch circuit. , parallel image information obtained by constant scanning can be converted into a format of parallel information addressed perpendicular to the scanning direction.

The shift register is for converting parallel image information into serial image information.

The memory is for storing serial image information successively received from the shift register in units of dots.

The oscillator circuit is activated in response to a request for inputting or outputting parallel image information, and is used to provide a clock on a monthly basis.

The counter is for counting clocks and giving dot addresses.

The memory address switching means is for switching addresses by writing or reading operations.

The loading/reading address latch circuit is for storing parallel image information or latching σ successive addresses.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an image information conversion circuit according to the present invention. In Figure 1, lFi
Shift register, 2 memory, 3 oscillation circuit, 4 counter, 5 memory address switching means, 6 write/*
output address latch circuit, 105 is a dot information address bus, 11G is a parallel image data bus, 112
H address bus 113 is an address bus for parallel image information.

In FIG. 1, when the parallel image information write/read control information on the signal -101 instructs writing, the parallel image information write/continue request signal sent on the signal line 102 Parallel image information on signal line 110 is stored in shift register l. Therefore, the oscillation circuit 3 activated by the convolution request signal
The parallel image information stored in the shift register I is converted into serial image information and sent out onto the signal return line 111 in synchronization with the clock sent out on the signal 1103 from the signal line 1103. The clock on signal line 103 is counter 4
The dot information address of the serial image information on the signal line 111 is generated by the output of the counter 4, and is sent onto the signal line 105.

In response to the write request signal on the signal line 102, the parallel image information is latched by the address latch circuit 6, and the write address of the parallel image information sent out on the address bus 113 and the address bus 108 are latched by the write request signal on the signal line 102.
Using the nine-dot information address sent above, the memory address switching means S generates a pledge address to the memory 2, which is addressed in units of dots. The serial image information on the signal line 111 is written into the memory 2 by this write address.

Signal line 111 corresponding to unit amount of parallel image information
When the writing of the above 7 real image information is completed, the signal of the upper digit of the dot alarm address bus 105 of the counter 4 becomes the parallel image information write/read operation end signal, clears the counter 4, and also starts the oscillation circuit 30. Stop the oscillation operation. Image information is written into the memory 2 by repeating this process.

On the other hand, if the parallel image information write/continue control information sent out on the signal line 101 instructs reading, the serial image information read out from the memory 2 onto the signal line 111 is read out by 7 feet. while storing it in shift register l. Generation of dot address information on the address bus IO5 is performed in the same manner as in the case of convolution. At this time, the address information on the address bus 112 is arranged in a direction 90 degrees different from the writing time so that adjacent dots are addressed in order.

The memory address switching means 5 switches addresses based on this address information.

The operation of the memory address switching means 5 will be explained with reference to FIG.

FIG. 2 is an explanatory diagram showing the byte allocation of the address bus 113 for parallel image information input to the memory address switching means 5 and the byte allocation of the address bus 112 output from the memory address switching means 5. In FIG. 2, 500 is dot address information of the parallel image information, 501 is horizontal address information of the address for parallel image information, S02 is vertical address information of the address for parallel image information, and 503 is dot address information. and horizontal address information.

At the time of loading, internal address information of the parallel image information is added to the lower bit position on the address bus 113 via the address bus 105, and is sent onto the address bus 112 as address information. When reading, the horizontal address on the address bus 113 (501 in FIG.
) and address information for parallel image information (
The vertical address (503 in FIG. 2) on the address bus 113 is the sum of the number of digits (503 in FIG.
If the number of digits is equal to the number of digits 502) in FIG. 2, the address information sent on the address bus 112 at the time of convolution has its upper byte and lower byte swapped. (See Figure 2 (a)) On the other hand, if the above sum (503 in Figure 2) is larger than the number of digits of the vertical address (502 in Figure 2), then the number of digits from the lower byte of the above sum is The number of digits is added to the upper byte side of the vertical address. (See Figure 2(b).) The above sum (
If the number of digits (503 in FIG. 2) is smaller than the number of digits of the vertical address (502 in FIG. 2), it is added to the lower byte side by the number of digits of the sum from the upper byte side of the vertical address. (Fig. 2 (C) @ Teru) If address information in memory 2 is generated as described above and sent onto the address bus 112, even if the same address information is sent onto the address bus 113, it will not be stored at the time of reading. Image information whose direction differs by 90 degrees from time can be obtained on the data bus 110 as parallel data.

(Effects of the Invention) As explained above, the present invention reduces the number of shift registers required by the number of print heads of a serial dot printer to 11 by storing parallel image information in the memory in units of dots. In addition, since the scanning direction of the parallel image information can be changed in the memory itself, it is possible to reduce the number of memories for the parallel image information by one before and after the change.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an image information changing circuit according to the present invention. FIG. 2 is an explanatory diagram showing the operation of the memory address switching means shown in FIG. 1. FIG. 8 is a block diagram illustrating an example of a eclipsing circuit according to the prior art. 1.3031~3034・Φ・Shift register 2...
Memory 3...Oscillation circuit 4.301...Color/ReS...Memory address switching means 6m+1/Write/read address latch circuit 3037
... Day latch circuit 10g, 11G, 112. l13.408゜413-・
...Pass

Claims (1)

[Claims] a shift register for converting parallel image information into serial image information; a memory for storing the serial image information read from the shift register in dot units; and a request for writing or reading the parallel image information. an oscillation circuit that is activated and supplies a clock to the memory; a counter that counts the clock and supplies a dot address; a memory address switching unit that switches addresses by the write or read operation; A write/read address latch circuit for latching a write or read address of parallel image information is provided, and the parallel image information obtained by a certain scan is processed into parallel information addressed perpendicularly to the direction of the scan. An image information conversion circuit characterized in that the image information conversion circuit is configured to be able to convert into an image format.