JPS62150414A - Protection equipment for common device - Google Patents

Abstract

PURPOSE:To prevent the destruction of a memory content or the like by inhibiting the access to a system bus of a processor module group at application of main power supply and permitting the access to the said bus after the initialization of all common devices is finished. CONSTITUTION:The system equipped with the common device protecting equipment consists of a processor module (PM) 11 and a common device (CM) 12 such as a common memory contained in a rack while connecting them by a system bus 10. In this case, a setup circuit 20 and a processor module lock (PML) circuit 30 are connected between the CM 12 and the system bus 10 to form the common device protecting equipment. The access to the system bus 10 of the PM 11 is inhibited as soon as power is applied and the bus access inhibition is released by the end of initialization of each CM 12 due to the system reset to effectively protect the CM 12.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a common VA, device protection circuit, and is particularly used in a multi-processing system having a group of processor modules sharing a system bus. be.

[Technical background of the invention and its problems]

A multi-processing module group consisting of a plurality of processor modules each connected to an external device is connected to each other by a system bus, and is also connected to a common memory device, input/output device, etc.
The system is widely used. In such a multi-processing system, the memory device 4, display device, etc. are shared as common equipment, making it possible to improve the system operating rate and efficiency.In particular, by using a microprocessor as the processor, performance versus price can be improved. It is possible to improve the ratio.

An example of a multi-processing system is shown in FIG.

According to the figure, a plurality of processor modules (PMl
)11~(PM,)1o and each unit of common equipment 1~
(CMl) 21 to (CMIll) 2IIl are stored in the rack 4. In addition, in the same figure, each common t equipment unit 1
-21~2. is shown in the form of a printed board, but in addition to those that take the form of a printed board such as a memory device, in the case of 110 equipment, the entire device is represented by a control printed board.

Each of these common equipment units 21-2. is located on the living surface of the rack 4 and is connected via a connector to a motherboard (not shown) that forms part of the system bus. A power switch 5 for the processor module and a power switch 6 for the common equipment unit are provided on the side surface of the rack 4, and a reset switch 7 for the processor module is provided on the top surface. In addition, a reset switch (
R8W1)31 to (R8Wo)3o are provided.

If a system reset is applied in such a multi-processing system, common equipment may be destroyed.

In other words, when each processor module is reset by a system reset, the processor modules that have already completed the reset routine may start accessing common devices such as memory devices through the system bus that are being initialized by the system reset. There is,
As a result, the memory contents will be destroyed.

In order to prevent such a situation from occurring, the multi-processing system is started up as follows.

First, turn on the power switch 3 for the common device, and then turn on the reset switch 31 to 3o for each unit of each common device.
Manually operate each in sequence to apply a local reset,
Complete initialization for each unit. Next, pu [1t?
The power switch 2 for the Tsusa module is turned on and a dedicated reset for the processor module is applied.

However, in order to start up such a system, a power switch for the common equipment and a power switch for the processor module must be installed separately, a reset I switch must be provided for each unit of the common equipment, and the order in which these are turned on must be set separately. Care must be taken not to make a mistake. Further, as a result of performing such an operation, the local reset operation within each processor module is forced to wait until the initialization in the common area is completed, resulting in a problem that the startup of the entire system is delayed.

To solve this problem, a circuit is provided for each unit of the common equipment to generate a local reset signal based on the system reset signal, and each unit in the common equipment is initialized during system reset. There is a way.

FIG. 5 shows a timing chart showing an example of this method. If the system reset (SR) is started at time to, then based on this system reset signal, at time t11, which is close to to, ...Zm is configured to initialize and start programming of each common equipment unit. For example, the reset of the substrate module (CMl) 21 starts at time t11.
performed at a common equipment reset time CRT1 ending at 21;
After that, programming time PT1 occurs, and the same applies to each unit. Therefore, a circuit for generating a local reset is provided for each unit.

In this case, the system reset time S takes into account the reset time and programming time of all units to finish the initialization of each unit during system reset.
If the initialization time of the C common equipment unit in which the RT is determined is long, the processor module group will be forced to wait in a reset state, causing the problem that the entire system will start up soon.

[Purpose of the invention]

The present invention was made to solve such problems, and provides a common equipment protection device that does not require a special operation section or complicated operations for each common equipment unit, and can reliably protect each common equipment unit. The purpose is to provide

[Summary of the invention]

The common device protection circuit according to the present invention receives an initialization completion signal from a plurality of common devices connected to a system bus that is reset by a system reset and starts initialization by a system reset, and completes all initialization. a monitoring circuit that generates an initialization completion signal when the main power is turned on, and a signal that prohibits access to the system bus to a group of processor modules connected to the system bus when the main power is turned on; The processor module lock circuit generates a signal to release the inhibition of access to the system bus based on the processor module lock circuit. Therefore, the processor module is prohibited from accessing the system bus as soon as the power is turned on, and the bus access prohibition is canceled when the initialization of each common Ia device is completed by a system reset, thereby preventing memory contents from being destroyed. The common II device can be effectively protected.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a system including a common equipment protection device according to the present invention.

According to the figure, the processor module PM1111,
PM 11 , PM 11o, ...m+++
n PM711□ are each connected to the system bus 10,
In addition, the common memory stored in the rack 13 or CR
CM for common equipment such as common I10 devices such as T, printers, etc.
12. 0M212□, . . . 0M11112m are also connected to the system bus 10.

In addition, a setup circuit 20 and a processor/sevenboard 1
A lock (PML) circuit 30 is connected between the common equipment and the system bus 10, which constitute the common equipment protection device of the present invention.

The setup circuit 20 inputs the system reset signal SR to the input terminal, and allows access to the system bus from the terminal F by the initialization completion signals of the common devices 121 to 12I11 inputted to the terminals E1 to E, respectively. bus lock release permission signal (SPL)
Output. This SPL signal is input to the B terminal of the processor module lock circuit 30, and the enable signal generated when the power is turned on is input to the A terminal of the processor module lock circuit 30.
An access prohibition signal (PLS) is output from the C terminal to each processor module 111 to 11□.

FIG. 2 is a circuit diagram showing an example of the hit-up circuit 20, including reset input terminals R1 to R0 to which a system reset signal SR is input, and common devices 121 to 12. Setup completion signal representing initialization or reset and end of unique programming @SP1~SPl
・An RS having input terminals 81 to 81 to S for inputting
The logic of flip-flops FF1211 to FF211Il and their Q1 to QI and l outputs! ! It consists of an AND gate 22 which outputs the product. flipflop 2
AND game when 11 to 21 are set]・22
The “1” level signal output from the
The output signal of the gate 22 is the bus lock release enable signal SPL.
It is output from terminal F to the PML circuit as a signal.

FIG. 3 is a circuit diagram showing details of the PML circuit 30,
The A terminal is a set input terminal that inputs the enable signal EA when the power is turned on, and the B terminal is the SP of the setup circuit 20.
R S becomes the reset input terminal that inputs the L signal output.
It consists of a flip-flop FFx, and its Q output becomes an access prohibition signal.

Note that this PML circuit is used in a multi-processing system that has a supervisory module (SVM) located above a group of processor modules, by prohibiting the supervisory module from accessing the system bus after the main power is turned on. This allows modules to preferentially use the system bus, but in the present invention, the setup circuit 20 controls access to the system bus of each processor module 111 to 11□ instead of the supervisor module. are doing.

The operation of the common equipment protection circuit as described above will be explained next.

First, when the main power is turned on, the enable signal M is sent from the power supply.
Since the EA is sent out, the flip-flop FF 30 is set, and its Q output becomes "H" as a bus lock signal (1) L S as each processor...7 Joules 111
.about.11□, the processor/module group is unable to access the system bus 10. When the system reset signal SR is applied to the system bus 10 and the setup circuit 20 in this state, each common device 121 to 12° that receives the system reset signal SR through the system bus starts resetting and programming. The common devices that have been initialized each output a set-up completion signal gsp1 to gsp1 to S1.The system reset signal SR is input to the set-up circuit 20 and outputs a set-up completion signal gsp1 to gsp1 to each of the seven lip-flops 211 to 2.
Since 1111 is in the reset state, each Q output is set to 1 by the input of the setup completion signals SP1 to SPI.
"'" is input to the AND gate 22. Therefore, when the initialization of all common devices is completed, the bus lock release signal SPL of "Hn level" is output from the F terminal of the setup circuit 20. Ru. This signal is PML3
Since it is a reset input of 0, PM L 30
is reset and its output is the access prohibition signal PL.
S becomes L'', the bus lock is released, and each processor module 111 to 112 can access the system bus 10.

In the above embodiment, the setup circuit monitors the completion of initialization of all common devices, but some of the common devices are known to have a short initialization time. There is also. To prohibit access to the system bus, it is sufficient to monitor the common devices that have the best time between initializations, so the setup circuit includes those whose initialization times are unknown, and the initialization of only common devices whose initialization times are known and long. Gotan may also be input.

Furthermore, although an RS flip-flop circuit is used as the setup circuit PM1 circuit, other configurations may be used as long as they can maintain a constant state depending on the input signal.

〔Effect of the invention〕

As described above, according to the present invention, access to the system bus of a group of processor modules is prohibited by the processor module lock circuit when the main power is turned on, and the system is monitored after initialization of all common devices is completed by system reset. The completion signal output from the circuit is processed by the processor.
Since it is input to the module lock circuit to permit access to the system bus of the processor module BY, the common A unit can be reset using the system reset signal, and by unifying the reset system,
There is no need to separately provide a local reset switch or a local reset generation circuit in the common Ia device. Furthermore, destruction of common equipment can be prevented without complicated operations, and reliability can be improved. Furthermore, since the system bus can be accessed immediately after the initialization of all common devices is completed, waiting time is reduced and system efficiency can be improved.

[Brief explanation of drawings]

FIG. 1 is a system configuration diagram showing a mobile protection system including a common device protection device according to the present invention, and FIG. 2 is a circuit diagram showing an embodiment of a setup circuit included in the common device protection device according to the present invention. , Fig. 3 is a symbolic diagram showing one embodiment of the processor/joule lock circuit in the common equipment protection device, Fig. 4 is a perspective view showing the configuration of the conventional Processera V module and common equipment, and Fig. 5 The timing is 1- in accordance with the conventional reset timing. 1-1.11-11. ...processor mo1 n
1 Joule, 2~2.121~12Ill...Common machine 1
Illumination unit, 10... System bus, 20... Setup circuit, 21-21. 22...AND goo m, 30...RS flip flop 0 knob.

Claims (1)

[Claims] 1. Initialization of all the common devices by receiving an initialization completion signal from a plurality of common devices connected to a system bus that is reset by a system reset and whose initialization is started by the system reset. a monitoring circuit that generates an initialization completion signal upon completion of the initialization; and a monitoring circuit that generates a signal that prohibits access to the system bus to a group of processor modules connected to the system bus when the main power is turned on; a processor module lock circuit that generates a signal for canceling prohibition of access to the system bus based on the output of the common equipment protection device. 2. Claims in which the monitoring circuit includes a plurality of state holding circuits that hold the state based on initialization completion signals from each common device, and an AND circuit that outputs a matching signal of these outputs. Common equipment protection device as described in paragraph 1. 3. The common equipment protection device according to claim 2, wherein the state holding circuit is an RS flip-flop circuit. 4. The common equipment protection device according to claim 1, wherein the processor/module lock circuit is an RS flip-flop circuit with a power supply enable signal as a set input and a monitoring circuit output as a reset input. 5. Claims 1 to 4, wherein the monitoring circuit generates an initialization completion signal from the outputs of only the common equipment whose initialization time is unknown and the common equipment whose initialization time is known to be long. A common equipment protection device described in any of the following.