JPS62184537A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To surely protect the secret of software with respect to the 3rd party by substantially destructing an internal circuit so as to disable the function of the circuit if one or several dissidences of a password are found. CONSTITUTION:A comparator circuit CMP compares a password which is stored in a ROM and read out to a data bus with an input signal supplied from a specific external terminal, and decides coincidence or dissidence of them. A counter circuit counts a dissidence output, and a boosting circuit VG operates if the number of said outputs becomes plural. The circuit VG forms a higher voltage than a power source voltage VCC, and generates a boosting voltage VCC' producing a latchup in an internal CMOS circuit. The action of the boosting circuit VG develops a latchup in the CMOS internal circuit including an important function comprising one chip microcomputer, whereby the circuit is destructed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and for example, to a technique effective for use in a semiconductor integrated circuit device having a microcomputer function.

[Conventional technology]

In a 1-chip microcomputer, the built-in R
It performs predetermined information processing according to a program written in the OM. Regarding such one-chip microcomputers, there is ``Hitachi Microcomputer Data Book 8-bit Single Chip 1'' published by Hitachi, September 1988.

[Problem that the invention seeks to solve]

If the stored information written in the built-in ROM is allowed to be output to an external terminal, the contents of the program will be known to a third party, which is undesirable from the viewpoint of software protection. However, in this test, it is necessary to read out the stored contents to an external terminal.

Therefore, the inventor of the present application considered satisfying the above-mentioned contradictory requirements.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device that has both the functions of protecting the security of information stored in a built-in storage device and testing the same.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a security protection circuit is provided that destroys the internal circuit upon detection of one or more mismatches in passwords for outputting stored information of a storage circuit in which a program or data is written to an external terminal.

[For production]

According to the above-described means, since the internal circuit is destroyed due to the mismatched password output, it is possible to prevent a third party who does not know the password from decoding the program or data.

[Embodiment 1] FIG. 1 shows a block diagram of an embodiment of an L-chip microcomputer according to the present invention. In the same figure, the semiconductor integrated circuit device fiLsI indicated by a broken line constitutes a one-chip microcomputer as a whole, and can be made by using a single chip such as single crystal silicon, although not particularly limited by known CMOS integrated circuit manufacturing technology. is formed on a semiconductor substrate.

The symbol CPU is a microprocessor, and its main constituent blocks are exemplarily shown as a representative.

A is accumulator, X is index register, CC
is the condition code register, SP is the stack pointer, PCH and PCL are the program counters, and CPU-
C0NT is a CPU controller, and ALU is an arithmetic logic unit.

Since the configurations of these microprocessors CPU are well known, detailed explanation thereof will be omitted.

Denoted by symbol I10 is an input/output boat,
It contains a data transmission bidirectional register inside. Also, what is indicated by the symbol I is an input-only port.

What is indicated by the symbol O8C is an oscillation circuit, which forms a highly accurate reference frequency signal using an external crystal resonator Xtal, although it is not particularly limited. This reference frequency signal forms the clock pulses required in the microprocessor CPU. Further, the reference frequency signal is also used as a reference time pulse of a timer.

This timer consists of counter C0UNT, prescaler P
and a controller C0NT.

The symbol RAM is a random access
It is a memory and is mainly used as a temporary data storage circuit.

The symbol ROM is a read-only memory in which programs and data for various information processing are written. Although not particularly limited, a mask ROM is used as the ROM in this embodiment.

The above circuit blocks are connected to each other by a bus BUS, with the microprocessor CPU as the center. This bus βUS includes a data bus and an address bus.

In the microcomputer of this embodiment, in order to control the output of the information stored in the ROM to the external terminal for security protection, in other words, a password is used to identify a password to start the operation of sending the contents of the ROM to the external terminal. have a function. This password identification function is provided by the following comparison circuit CMP, although it is not particularly limited. The comparison circuit CMP is connected to the RO read out on the data bus.
The password stored in M is compared with the input signal (password) supplied from a specific external terminal to determine whether they match or do not match. This mismatch output is counted by a counter circuit as described later, although it is not particularly limited. The booster circuit VG is activated by multiple mismatched outputs. The booster circuit VG forms a high voltage higher than the power supply voltage Vcc, and, for example, the internal 0M03 as described later.
A boosted voltage Vcc that causes roughness in the circuit
This boosted voltage Vcc' is transmitted, for example, to the 0M03 circuit constituting the microprocessor CPU.In other words, it causes the 0M03 circuit to launch up. As a result of this operation, latch-up occurs in the CMO8 internal circuit, which has an important function constituting the 1-chip microcomputer, and the circuit is destroyed.

Note that the comparison circuit CMP is put into an operating state when a test mode is instructed, for example, by a control signal given to the CPU from the outside, and any of the input/output ports which is put into an operating state at this time! 10 or an input-only boat ■ (It is even more desirable that a boat that is valid during such a test not be disclosed to a third party) Determine inconsistency. In addition, instead of installing the comparison circuit CMP, the arithmetic and logic operation unit (UNISO) AL included in the microprocessor CPU
The password comparison operation may be performed using the logic operation function in U.

FIG. 2 shows a block diagram of an embodiment of a security circuit including the comparison circuit CMP and booster circuit VG.

Although not particularly limited, when the test mode is set, the input-only port (2) is automatically activated, and a signal from the external terminal Din is transmitted to the data bus BUS in synchronization with the inverted clock signal φ. In the same figure, input-only boat I
One input circuit making up the circuit is exemplarily shown. Although not particularly limited, in an 8-bit single-chip microcomputer, the input circuit is comprised of eight pieces, and an 8-bit input signal (password) is supplied onto eight data buses.

The 8-bit password supplied onto the data bus BUS is held in a flip-flop circuit F2 which receives the input signal in synchronization with the same inverted clock signal φ. This flip-flop circuit F2 is also composed of eight flip-flop circuits.

The ROM is read out in synchronization with a non-inverted clock signal φ. That is, the read signal (password) of the ROM automatically selected by the test mode instruction is output to the data bus BUS via the output circuit DO which is activated by the clock signal φ. The above output circuit DO also consists of 8 pieces, and the 8 pieces read out from the ROM.
A read signal consisting of bits is output to the data bus BUS.

The 8-bit read signal supplied onto the data bus BUS is held in a flip-flop circuit F1 which takes in the input signal in synchronization with the same non-inverted clock signal φ. This flip-flop circuit F1 is also 8
It consists of flip-flop circuits.

The signals taken into the flip-flop circuits Fl and F2 are supplied to the digital comparator DC. This digital comparator DC consists of eight sets of exclusive OR circuits (match/mismatch circuits) and an AND(
It consists of an AND circuit such as an AND) gate circuit.

In this embodiment, although not particularly limited, the output signal of the digital comparator DC is output to the binary counter circuit FF.
'Supplied to. This counter circuit FF consists of a binary counter circuit consisting of 3 bits, and its final stage bit output is supplied to an AND gate circuit G. This results in
The AND gate circuit G opens its gate by the same mismatch output five times, and supplies the clock signal φ to the booster circuit VC, although this is not particularly limited. Although not shown, the counter circuit FF is brought into a reset state by a reset signal supplied prior to the test node.

The booster circuit VC receives the clock signal φ and generates a voltage Vcc'' higher than the power supply voltage Vcc.

This boosted voltage Vcc' is not particularly limited, but is 0M
P-channel MOS FETQl that constitutes the 05 circuit
source. This MOS F ) F, TQl
A power supply voltage Vcc is supplied to the N-type well region (substrate gate) in which the substrate gate is formed. As a result, the boosted voltage Vcc'
When this occurs, a forward current flows between the source of the P-channel MO3FET QI and the substrate gate, which acts as a trigger and turns on the parasitic thyristor element in the well-known 0M03 circuit, causing CMOS latch-up. Although not particularly limited, the MO3FETs QI and Q2 are configured to constitute an important circuit in the microprocessor CPU, or a dummy circuit provided in the vicinity, for reliable security protection.

As a result, the internal circuit is destroyed due to five password mismatches, so that the microcomputer becomes inoperable from now on and the above-mentioned security protection can be performed.

FIG. 3 shows a circuit diagram of an embodiment of the booster circuit VG.

The pulse signal φ passed through the AND gate circuit G is applied to one electrode e of the capacitor C1 via an inverter circuit IV.
1. The other electrode e2 of this capacitor C1
MO3 in the form of a diode is connected between
FETQ3 is provided.

The voltage of the electrode e2 is MO3F F in diode form.
, TQ4 to capacitor C2.

The capacitor C2 has a diode type MO3FE.
An initial voltage is applied via TQ5. As a result, when the pulse signal φ is not supplied, the output voltage Vc
c' is Vcc-Vth(
Vth is the threshold voltage of MO3FETQ5.

When the pulse signal φ is supplied due to the mismatch of the passwords, the boosted voltage Vcc' that is higher than the power supply voltage Vcc is generated by the following operation.

When the output signal of the inverter circuit IV is at a low level such as the ground potential of the circuit, the MO3FET is connected to the capacitor C1.
Precharging is performed via Q3. by this,
The potential of the other electrode e2 of the capacitor C1 is Vcc-V
th (Vth is the threshold voltage of MO3FETQ3), when the output signal of the inverter circuit IV is set to high level (Vcc), the potential of the electrode e2 increases to 2Vcc due to the charge pump action. - A high voltage such as Vth is applied. This voltage 2Vcc-Vth at the other electrode e2 is transmitted to the capacitor C2 via the MO3FETQ4. This makes the capacitor C
The voltage Vcc' of capacitors C1 and C02 is set to a high voltage according to the charge distribution of capacitors C1 and C02. Thereafter, by repeating the same operation, the boosted voltage Vcc' is raised to a voltage higher than the power supply voltage Vcc, causing the latch-up.

[Embodiment 2] FIG. 4 shows a circuit diagram of a main part of another embodiment of the present invention.

In this embodiment, in order to cause chimp-up in the 0M03 circuit, the boosted voltage Vcc' generated by the booster circuit VG, which is automatically activated when the power is turned on, is
It is stored in a capacitor C2' having a relatively large capacitance value. A MO3FET Q6 is provided in parallel with this capacitor C2'. The output signal of the counter circuit FF as shown in FIG. 2 is supplied to the gate of this MO3FETQ6. As a result, when the comparison circuit DC detects a password mismatch output a plurality of times, the MO8FET Q6 is turned on, and the boosted voltage Vcc' stored in the capacitor C2' is discharged at some point. As a result, a spike-like current with a relatively large current value flows through the ground line of the circuit.Since the ground line of the zero circuit includes a non-negligible resistance component and an inductance component, the current generates spike-like noise.

This noise serves as a trigger for causing the same latch-up as described above, for example, in order to raise or lower the ground potential of the N-channel MOS FET constituting the 0M03 circuit.

As a result, the 0M03 circuit placed near the MO3FET Q6 is destroyed, rendering the 1-chip microcomputer inoperable in the same way as described above, and protecting its security.

The effects obtained from the above embodiments are as follows.

+11 If the password to activate the internal ROM read mode does not match once or multiple times,
By causing latch-up in the 0M03 circuit and destroying the circuit function, it is possible to securely protect the security of software by a third party.

(2) Since the ROM can be read by using a password, it is possible to easily test the ROM.

(3) By making the password input terminal secret as well, it is possible to obtain the effect that, in combination with the above-mentioned circuit destruction, decoding the password can be made even more complicated.

(4) ROM by fuse means etc. after testing.
Compared to devices such as those that completely prohibit output functions to external terminals, as long as you know the password, you can test the contents at any time, making it extremely convenient for failure analysis and maintenance in the market.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, built-in ROM
is a variety of programmable R that is written electrically.
It may also be one that uses OM. In addition, circuit destruction
In addition to using the CMOS launch-up mentioned above, the wires constituting a specific important circuit can be broken by rush current using the boosted voltage, etc., or the fuse means can be cut, thereby operating the internal circuit. Anything that substantially disables the function may be used.

Further, the system configuration of the l-chip microcomputer can take various embodiments, and may include a built-in addition circuit such as an A/D converter for functional expansion.

The above explanation has mainly been about the application of the invention made by the present inventor to a one-chip microcomputer, which is the background field of application, but the invention is not limited thereto. It can be widely used in various semiconductor integrated circuit devices having microcomputer functions such as IC cards.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, by using a password to activate the read mode of the built-in ROM, it is possible to read the built-in ROM, and if the password does not match once or multiple times, the internal circuit is essentially destroyed and the circuit function is disabled. By disabling the software, security protection of the software by a third party can be ensured.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an l-chip microcomputer to which the present invention is applied; FIG. 2 is a block diagram showing an embodiment of an InI3 protection circuit including a comparator circuit and a booster circuit; FIG. 3 is a circuit diagram showing one embodiment of the booster circuit, and FIG. 4 is a circuit diagram of a main part of a security protection circuit showing another embodiment of the present invention. CPU-C0NT...CPU controller, ALU...
Arithmetic 4FI IT unit, A...accumulator, X
・・Index register, CC・・Condition code register, SP・・Stack pointer, PCI, P
CL...Program counter, RAM...Random access memory, ROM...Read-only memory, Ilo...I/O port,!・Input-only port, O
SC: Oscillation circuit, C0UNT: Counter, C0NT
・・Controller, PR・・Prescaler, BUS・・
Bus, CMP...comparison circuit, DC...digital comparator, Fl~F4...flip-flop circuit, VG...
・Boost circuit, G...AND gate Figure 1 Figure 2; φ1 low] Figure 3 Figure 4 MP

Claims (1)

[Scope of Claims] 1. A password identification function for making it possible to output the stored information of the memory circuit to an external terminal, and a security protection circuit that destroys the internal circuit based on the result of the mismatch of the passwords. A semiconductor integrated circuit device comprising: 2. When the above-mentioned security protection circuit detects a plurality of password mismatch outputs, the internal CMO is activated by a boosted voltage.
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device causes latch-up in the S circuit. 3. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device has a microcomputer function, and the storage circuit is a ROM in which the program or data thereof is stored. .