JPS6214996B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital VTR that records color video signals in the form of digital signals.

When digitally recording a color video signal, if the digital signal converted from the color video signal is recorded as is, the bit rate of the recording signal will become high, resulting in an increase in tape consumption.

Therefore, in a typical digital VTR, a digital signal is distributed to a plurality of channels, and this is recorded as a multi-track by a plurality of rotating magnetic heads.

Figure 1 shows an example of such a digital VTR recording system. In this example, an NTSC color video signal is converted to a digital signal, and is alternately recorded between the A channel and the B channel for each sample. The two channels of digital signals are supplied to two rotating magnetic heads arranged in-line and recorded as two magnetic tracks per field.

That is, the color video signal is supplied to the input processor 12 through the input terminal 11, the synchronizing pulse and the burst signal are separated or removed, and the synchronizing pulse and the burst signal are supplied to the master clock forming circuit 21 to synchronize with the burst signal. In addition, a clock pulse having a frequency that is, for example, three times as high as the frequency f _c is formed, and this clock pulse and synchronizing pulse are supplied to the control signal forming circuit 22 to generate identification signals, sampling pulses, and various other signals related to lines, fields, frames, and channels. timing signals are formed, and these signals are respectively supplied to predetermined circuits.

Further, in the processor 12, the color video signal from which synchronization pulses and burst signals have been removed is processed by A/
The signal is supplied to the D converter 13. In this case, the sampling frequency is 3f _c , and f _c =455/2f _h (f _h : horizontal frequency), so the number of samples in one horizontal period is 682.5 samples, but the number of samples has a fraction of 0.5. Considering that there is no need to sample in the horizontal blanking period, and that the digital signal is distributed into two channels, the number of samples in the effective video area in each horizontal period is set to 576 samples, as shown in Figure 6. will be allocated to. However, HD
is the horizontal sync pulse and BS is the burst signal (these have been removed but are shown for convenience).

Furthermore, the number of lines in one field is 262.5 lines, of which 10.5 lines are occupied by vertical synchronization pulses and equalization pulses. Test signals such as VIR and VIT are inserted into the vertical retrace interval, and these are also considered valid data.
Therefore, the number of effective video lines in one field period is set to 252, and the 12th to 263rd lines are considered effective video lines in odd-numbered fields, and the 274th to 525th lines in even-numbered fields.

In this way, in the converter 13, the color video signal is sampled based on the above points, and is A/D converted, for example, into an 8-bit parallel digital signal (PCM signal) per sample.
quantized to

This digital signal is then supplied to the interface 14 and distributed alternately to the A channel and the B channel for each sample. That is, among the 576 samples of one line, the digital signal of the odd-numbered sample is supplied to the time-base compression circuit 15A of the A channel, and the digital signal of the even-numbered sample is supplied to the time-base compression circuit 1 of the B channel.
5B, and the time axis is 41/44 as described later.
This compressed two-channel digital signal is sent to error correction encoders 16A and 16B.
and recording processors 17A and 17B, and are converted into signals in the format shown in FIGS. 7 and 8.

Here, in Fig. 7, A of the signal of one field is
or B channel signal, which is 13×22
Each block consists of three sub-blocks SB, and one block has one line of color video signal data. Therefore, one subblock SB has data for 1/3 line, but this subblock SB is
As shown in FIG. 8, it sequentially includes a 24-bit block synchronization signal SYNC, a 16-bit identification signal ID and address signal AD, 768-bit (96 samples) data, and a 32-bit CRC code.

Here, the synchronization signal SYNC is the signal ID,
Used for synchronization when extracting AD, data, and CRC codes. Also, the identification signal ID indicates whether this channel (track) is A or B, whether the line, field, or frame is an odd number,
Indicates whether the address signal AD is even or
indicates the address (subblock number) of the subblock SB. Furthermore, the data is an original digitized color video signal, and the CRC code is used to detect data errors during playback.

As mentioned above, the number of effective lines in one field period is 252, so the number of blocks for one field is 252, but these 252 blocks are arranged in a 12 x 21 matrix as shown in Figure 7. At the same time, horizontal direction (row direction) parity data is added to the 13th column, and vertical direction (column direction) parity data is added to the 22nd row, resulting in a total of 13 × 22 blocks. It is said that

In this case, sub-block SB and in turn SB ₁ ~
Assuming SB ₈₅₈ , for the first line SB ₁ SB ₄ SB ₇ ......SB ₃₄ = SB ₃₇ SB ₂ SB ₅ SB ₈ ......SB ₃₅ = SB ₃₈ SB ₃ SB ₆ SB ₉ ......SB ₃₆ = _As shown in SB _{39 ,} addition [ _mod .
Horizontal parity data is formed in the same manner for the subsequent 2nd to 21st rows.

Also, for the first column, SB ₁ SB ₄₀ SB ₇₉ ...... SB ₇₈₁ = SB ₈₂₀ and the vertical parity data of the first column
SB ₈₂₀ is formed, and vertical parity data is formed in the same manner for the 2nd to 13th columns.

Note that these horizontal and vertical parity data and CRC code are used to improve the data error correction ability during reproduction, and the parity data is also 840 bits.

The signal processing that forms this parity data and CRC code and adds it to the data is
This is done in encodings 16A and 16B. Also, synchronization signal SYNC, identification signal ID, address signal
The signal processing that forms the AD and adds it to the data is
This is performed in processors 17A and 17B.

Processors 17A and 17B also perform block encoding to convert the number of bits in one sample from 8 bits to 10 bits. This block encoding uses DSV (DC level) of the 10-bit (2 ¹⁰ ways) codes.
is 0 or close to 0.2 Choose ⁸ codes, make a one-to-one correspondence with the original 8-bit code, and create 10
D of the recorded signal.
Set ^{the SV} to 0 as much as possible, that is, “0”
This conversion is performed so that "1" and "1" appear almost uniformly. This block encoding is performed because a general magnetic head cannot reproduce the DC component during reproduction.

Furthermore, in the processors 17A and 17B,
The block-encoded digital signal in 10-bit units is converted from a parallel signal to a serial signal in order starting from sub-block _SB1 . Further, a preamble signal and a postampule signal are added before and after the digital signal for one field. In addition,
The pit rate of the signal after serial conversion is 3f _c × 8 × 1/2 × 44/41 × 10/8 = 57.62 [Mb
/s].

Then, this serial digital signal is transmitted to the rotating magnetic heads 1A, 1 through the recording amplifiers 18A, 18B.
B is supplied. The heads 1A, 1B are provided in-line in close proximity, as shown in FIGS. 3 and 4, for example, and the heads 1A, 1B are
is rotated at the field frequency in synchronization with the color video signal. And this head 1A, 1B
The magnetic tape 2 is wound obliquely in an Ω-shape over an angular range of approximately 360 degrees with respect to the rotating circumferential surface of the magnetic tape 2, and is run at a constant speed.

Therefore, as shown in FIG. 5, the A channel digital signal is recorded by the head 1A as one diagonal track 3A per field, and at the same time the B channel digital signal is recorded by the head 1B. One diagonal track 3B per field is recorded in parallel and close to track 3A. In this example, heads 1A,
A track width and spacing of 1B is selected so that one set of tracks 3A, 3B corresponds to one of the SMPTE "C" format video tracks.
Further, 4 is a control track.

By the way, in this case, if we look at each channel, recording will be done using a one-head system, so one head
There is a missing period in the records of A and 1B, and SEPTE
In the "C" format, the time that can be recorded on tracks 3A and 3B is about 250 horizontal periods, and if you take a margin into account, it is 246 horizontal periods.

On the other hand, as shown in FIGS. 7 and 8, the number of samples (number of bits) in one subblock is 105 samples (840 bits), and the number of subblocks in one field period is 858. Therefore, the number of samples in one field period is 105 x 858 = 90090 [samples], which can be seen from Figure 6. , corresponding to 264 horizontal periods. Therefore, data for 264 horizontal periods is recorded in 246 horizontal periods.

Therefore, the time axis of the signal is compressed in the time axis compression circuits 15A and 15B, that is, the time axis is compressed to 246/264=41/44.

In addition, as described above, the subsequent circuits 16A to 17B
Since various signals are added in the time axis compression circuits 15A and 15A, the gaps for these additional signals are also
15B.

Color video signals are digitally recorded in the above manner.

FIG. 2 shows an example of a reproduction system. That is, tracks 3A and 3B are connected by heads 1A and 1B.
The digital signals of each channel are simultaneously reproduced from the
The signal is supplied to the reproduction processors 32A and 32B through the signal line B, where it is converted from a serial signal to a parallel signal, and is block decoded from the 10-bit code to the original 8-bit code signal. A clock is also formed from the digital signal reproduced by the PLL.

Then, this parallel 8-bit digital signal is
TBC (time base collector) 33A, 33B
is supplied to eliminate time axis fluctuations. In this case, the TBCs 33A and 33B have memories, and the block synchronization signal SYNC is used to cue the next signal, and the clocks from the processors 32A and 32B are used to write to the memories, which are formed by the internal sync. The readout from the memory is performed by the clock, and time axis fluctuations are removed.

Signals from the TBCs 33A and 33B are then supplied to error correction decoders 34A and 34B through an interchanger 41, which will be described later. These decoders 34A and 34B have field memories and input address signals AD for each subblock SB.
At the same time, the data is written to the field memory according to the
Data errors are corrected using the CRC code and horizontal and vertical parity data. Note that when there are many errors and cannot be corrected using the CRC code and parity data, the data of that subblock SB is not written to the field memory, and therefore the data one field before is read.

The error-corrected data is then supplied to the time axis expansion circuits 35A and 35B to become the original time axis data, and this output is supplied to the interface 36 to convert it into the original one-channel digital signal. Furthermore, this digital signal is supplied to the D/A converter 37 and converted into an analog color video signal. This color video signal is then supplied to an output processor 38, where a synchronization pulse and a burst signal are added to form the original color video signal, which is output to an output terminal 39.

A color video signal is reproduced in the above manner.

Note that when dubbing is performed between digital VTRs, the playback VTR circuits 34A, 34B, 3
7, 38 and recording VTR circuits 12, 13, 1
6A and 16B are bypassed. Further, the tracking servo during recording and playback may be the same as in an analog VTR.

According to such a digital VTR, tape consumption can be made equal to or less than that of a conventional analog VTR. Moreover, since it is digitally processed, there is almost no deterioration in image quality even if dubbing is repeated.

By the way, helical scan type analog
VTRs are designed to perform high-speed searches, in which the tape is played back while running at a higher speed than when it was recorded, in order to conveniently find the beginning of the tape and check its contents.

However, in such a digital VTR, simply playing back tape 2 while running it at high speed causes heads 1A and 1B to play track 3.
A and 3B are crossed diagonally, and at this time, head 1A of the A channel plays track 3B of the B channel, and head 1B of the B channel plays track 3A of the A channel. I can't.

Therefore, in order to enable this high-speed search,
This VTR is provided with an interchange gear 41. That is, during a high-speed search, the channel identification signal of the identification signal ID included in each sub-block SB is extracted from the digital signal in the interchanger 41, and based on this channel identification signal, the digital signal is originally identified for each sub-block SB. will be routed to the correct channel.

Therefore, during a high-speed search, even if the heads 1A, 1B reproduce tracks 3B, 3A of the opposite channel, the reproduced signals are returned to the correct channel at the interchanger 41, so that a high-speed search can be performed.

However, simply providing the interchange gear 41 in this manner is not sufficient, and it is also necessary to solve the following points.

During high-speed search, it is necessary to align the reference phases of carrier color signals (phases of color subcarriers).

That is, in the NTSC system, 1:2 interlaced scanning is performed, and the color subcarrier frequency f _c is f _c =455/2f _h as described above, so the waveform of the carrier color signal is FIG. 9 shows a diagram corresponding to the scanning lines. However, in this figure, for clarity, the color components are assumed to be constant, and the solid lines indicate the waveforms for odd-numbered fields, and the broken lines indicate the waveforms for even-numbered fields. Further, numbers [1] to [525] indicate line numbers for each frame, and codes L _1-1 to _{L 2-263} indicate line numbers for each field _.
In _L2-263 , the front suffixes 1 and 2 indicate an odd field (first field) and an even field (second field), and the rear suffixes 1 to 263 indicate the line number in each field. Note that in this figure, for the sake of simplicity, the odd-numbered fields are 262 lines and the even-numbered fields are 263 lines.

And, for example, lines in odd frames
L _2-1 , L _1-1 signals and even frame lines
Although the signals L _2-1 and L _1-1 belong to different fields, when they are converted into digital signals, they become sub-blocks SB ₁ to _{SB 3} . Similarly, for signals on other lines, equal signals in later subfixes may belong to different fields.
The subblock numbers will be the same, and therefore the address signals AD will also be the same.

On the other hand, during high-speed search, heads 1A and 1B
scans tracks 3A and 3B diagonally, so
The reproduced A channel or B channel digital signal for one field includes signals of different fields. Therefore, error correction is not performed in the decoders 34A and 34B, and the reproduced digital signal is written to the corresponding address of the field memory in accordance with the address signal AD for each sub-block SB, but at this time, Some of the signals to be written are for odd fields, others for even fields, and some addresses are not written to.

During a high-speed search, for example, the signal of line L1-1 of an odd frame is written to the address corresponding to the first line of the field memory, and the signal of line _L1-1 of the odd frame is written to the address corresponding to the second line. When the L _2-2 signals are written, there is no problem even if they are read out continuously during reading.

However, during high-speed search, for example, the signal of line L 2-1 of an odd frame is written to the address corresponding to the first line of the field memory, and the signal of line L _2-1 of an even frame is written to the address corresponding to the second line. If signals _1-2 are written, the odd frame line will be used when reading.
L _2-1 signal followed by lines L _1-2 in even frames
will be read out, and this line L _2-1 and
At the joint with L _1-2 , the reference phase of the carrier color signal is reversed.

That is, if odd frame signals and even frame signals are mixed and written into the field memory, the reference phase of the carrier color signal will be reversed at the joint.

In reality, since signals are written in sub-block units, such phase inversion may occur in sub-block units.

Therefore, during a high-speed search, it is necessary to detect and correct the inversion of the reference phase of the carrier color signal, but the digital signal is an A/D converted signal of the luminance signal and the carrier color signal. Therefore, the digital signal state is separated into a luminance signal and a carrier color signal, and the separated carrier color signals are corrected for phase inversion and then combined again.

Therefore, the digital signal must be in a form that can be directly separated into a luminance signal and a carrier color signal without D/A conversion.

Even if the problem is solved, the sampling point for the carrier color signal becomes a problem during high-speed search.

That is, in the above-mentioned VTR, the sampling frequency in A/D conversion during recording is three times the color subcarrier frequency f _c , so the first sampling is, for example, on the (B-Y) axis of the carrier color signal. If sampling is performed at a phase of 0°, 120°, and 240° with respect to the (B-Y) axis, the carrier color signal is shown in Figure 10A. , the points marked with black circles are sampled.

Then, when is solved, during high-speed search, the carrier color signal of line L _2-1 of the odd frame and the carrier color signal of line L _1-2 of the even frame are as shown in FIG. 10B. The reference phase is continuous.

However, the sampling points for the carrier color signals of these lines L _2-1 and L _1-2 are
This is the point with a black circle, so this line L _2-1
The periodicity of the sampling points is disturbed at the joint between the carrier color signal of line L1-2 and the carrier color signal of line _L1-2 . Since signals are written in units of subblocks, disturbances in the periodicity of sampling points may occur at the joints of subblocks. Therefore, during high-speed search,
Color reproduction with the correct hue may not be possible.

Furthermore, it is necessary to take into consideration the case where it is not possible to correct errors in the reproduced digital signal using the CRC code and parity data during normal reproduction.

That is, as described above, the decoders 34A,
In 34B, signal errors are corrected using a CRC code and horizontal and vertical parity data during normal playback, but if there are many errors, these CRC codes and parity data may not be able to correct them.

If the error cannot be corrected in this way, the subblock with the error is replaced with another subblock, but as is clear from FIG. 9, for example, line L _2-2 and line It is spatially separated by two lines from line L _2-1 one horizontal period ago. But the line
L _2-2 and line L _1-2 or L _1-1 one field period earlier are spatially separated by only one line. Therefore, when errors cannot be corrected using the CRC code or parity data, if a signal from a line one field period ago is used instead, the vertical correlation is large and errors are less noticeable.

However, in this case, if the signal on line L _1-1 were substituted for the signal on line L _2-2 , the reference phase of the carrier color signal would be reversed, so the line
The in-phase signal of L _1-2 will be used instead. Similarly, for example, for the signal on line L _1-1 of an even frame, the signal on line L _2-2 of an odd field, which is one field period earlier, is substituted. That is, in general, in order to substitute one signal (subblock) for another signal (subblock), it is necessary to substitute a signal (subblock) one line below one field period ago.

This invention aims to provide a digital VTR recording method that takes into account the above points.

Therefore, in this invention, as shown in FIG. 11, valid data is divided into N blocks (N≧2 integer) for each horizontal period, a channel is set for each block, and this A -N channel signals are recorded as tracks 3A to 3N, respectively. However, in this case, each block is
It is composed of M subblocks (M≧1, an integer), and each subblock is configured to have data for L consecutive cycles (L≧1, an integer) of the carrier color signal. Further, the sampling frequency is set to be K times the color subcarrier frequency (an integer of K≧3).

FIG. 12 shows an example of this invention. In this example, N=3, M=2, L=32, W=4
This is the case. That is, in the A/D converter 13, the color video signal has a sampling frequency of _4fc , and one sample is quantized into 8 bits, and as shown in FIG. This digital signal is supplied to the interface 14 to display the first consecutive 1/1 signal for each horizontal period.
The 256 samples of the 3 lines are distributed to the A channel, the 256 samples of the continuous 1/3 line in the center are distributed to the B channel, and the 256 samples of the continuous 1/3 line at the end are distributed to the C channel.

These channels A to C operate in the same way as the recording system shown in FIG. 1, and corresponding circuits are given the same reference numerals with suffixes A to C.

However, in this case, these 256 samples constitute one block, and one block is divided into two subblocks, and one subblock has 128 samples (1024 bits) of valid data, as well as the block synchronization signal SYNC, identification signal ID, and address. It also has signal AD and CRC codes.

Also, in each channel, the number of blocks for one field is 252, which is equal to the 14th block.
As shown in the figure, they are arranged in a 12×21 matrix, and horizontal parity data and vertical parity data are added to the 13th column and 22nd row. Furthermore, the time axis compression is 123/130 times.

The signals of each channel are then supplied to heads 1A to 1C arranged inline, and three mutually parallel tracks 3A to 1C per field.
Recorded as 3C. In this case, one set of tracks 3A to 3C corresponds to one SMPTE "C" format video track.

On the other hand, the playback system is basically the same as the playback system shown in FIG. be done.

Recording and playback are performed as described above, but
According to the recording method of the present invention, all of the following points can be solved or satisfied.

Next, let me explain these points. In addition,
Since each channel has the same configuration, the suffixes A to C of the reference symbols will be omitted in the following description.

About During high-speed search, the luminance signal and carrier color signal can be separated from the reproduced digital signal.

Since the sampling frequency during A/D conversion is four times the color subcarrier frequency f _c (K=4), for example, as shown in FIG. 15, regarding the carrier color signal,
Sampling will be performed at points of 0°, 90°, 180°, and 270°. Therefore, if the signal level at each sampling point is S ₁ , S ₂ , S ₃ , S ₄ , the color video signal Sk is Sk=Y+1/1.14(R-Y) cosω _c t+1/2.03 (B-Y) sinω _c t≡Y+DRcosω _c t+DBsinω _c
t ω _c =2πf _c DR=1/1.14(RY) DB=1/2.03(B-Y) Therefore, S ₁ =Y ₁ +DR ₁ S ₂ =Y ₂ +DB ₂ S ₃ = Y ₃ − DR ₃ S ₄ = Y ₄ − DB ₄ . And the bands of the signals R-Y and B-Y are
Around 500kHz, sampling frequency 4f _c (〓
14.3MHz), that is,
Since the amplitude changes of the signals RY and BY are sufficiently slow compared to the sampling period, DR ₁ 〓 _{DR 3} DB ₂ 〓 DB ₄ .

Therefore, _S1 + _S3 /2= _Y1 + _Y3 /2+1/2(DR1 _{- DR3} )= _Y1 + _Y3 /2=Y1S2+ _S42 = _{Y2 + Y4} /2+ ₁ /2 (DB ₂ - DB ₄ ) = _{Y 2} + Y ₄ /2 = Y ₁ DR ₁ = S ₁ - _{Y 1} DB ₂ = S ₂ - Y ₂ - DR ₃ = S ₃ - _{Y 1} - DB ₄ = S ₄ - Y It becomes ₂ . Therefore, if there is a digital signal for one cycle (sampling output), the luminance signal and the carrier color signal can be separated from the digital signal.

Furthermore, in this case, the digital signal is continuous for 32 cycles (L = 32) per subblock, so it is possible to sufficiently separate the luminance signal and carrier color signal, and when this separation is performed using a digital filter. , can be done reliably.

Furthermore, when the sampling frequency is 3f _c , Therefore, Y=S ₁ +S ₂ +S ₃ /3 DR=S ₁ −Y DB=(S ₂ −S ₃ )/√3, and the luminance signal and carrier color signal can be separated. The same applies to the case of K≧5.

Regarding the periodicity of sampling points during high-speed search is not disturbed.

That is, each subblock has a carrier color signal.
Since each 1/3 line is continuously included, the periodicity of the sampling points will not be disturbed even during high-speed search.

Regarding normal playback, even when error correction using CRC codes and parity data is not possible, the conspicuousness of errors and the continuity of the reference phase of the carrier color signal can be easily resolved.

FIG. 16A schematically shows the field memory of the error correction decoder 34 in each channel of the reproduction system. AD ₁ to AD ₅₇₂ each indicate the memory area or address for one subblock, and therefore one row is 1 line (in terms of data amount, 1/
3 lines) memory area.

And there are no signal errors. Or the error is
To explain the case where correction can be made using the CRC code and parity data, in the odd field period of the I-th frame period, as shown in FIG. These data are sequentially written and then read out. Furthermore, writing is performed in the even field period of this I-th frame period as well as in the previous field period, and this is read out.

Then, in the odd field period of the next (I+1)th frame period, as shown in FIG. 16C, the signal is written with the address shifted by one line, and this signal is read out. Further, the even field period of this (I+1)th frame period is also written and read in the same manner as the previous field period.

Then, in the odd field period of the (I+2)th frame period, as shown in FIG. 16D, the signal is written and read with the address further shifted by one line. Further, this (I+2)th even field period is also written and read in the same manner as the previous field period.

Similarly, if there is no signal error,
If the error can be corrected using the CRC code and parity data, writing is performed with the address shifted by one line for each frame.

However, some errors in the odd field signal
If the error cannot be corrected with the CRC code and parity data, for example, if the error in subblock SB ₁ of the odd field in the (I+1)th frame period cannot be corrected, the previous field period is the frame period. are different, so the first
6 As shown in Figure E, other sub-blocks SB ₂ ~
For SB ₅₇₂ , the address is shifted by one line and written, but the subblock with the error
Only SB ₁ is not written to.

Therefore, sub-block SB ₄ of the even field period of the I-th frame period remains in the memory area where sub _- block SB ₁ was supposed to be written.
is nothing but the sub-block one field before and one line below. Therefore, if the contents of this memory are read out as they are, the output will be one in which the errors have been corrected using a signal with a high correlation;
The continuity of the reference phase of the carrier color signal is also maintained, and there is no phase reversal.

Also, some errors in the even field signals
If the CRC code and parity data cannot be corrected, for example, the sub-block of the even field period of the (I+1)th frame period
If the error in SB ₁ cannot be corrected, the frame period is the same as the previous field period, so other subblocks SB ₂ to SB 2 are corrected as shown in FIG. 16F.
As for SB ₅₇₂ , the address is not shifted and it is written, but only the erroneous sub-block SB ₁ is not written high.

Therefore, in this case, the erroneous subblock SB ₁ has been substituted with the subblock one field before and one line below, so that the error is not noticeable and a phase inversion occurs in the reference phase of the carrier color signal. Never.

That is, according to the recording method of the present invention, even if errors cannot be corrected using the CRC code and parity data during reproduction, the errors can be easily corrected.

Note that during a high-speed search, if the address at the time of writing to the field memory is shifted as shown in Figure 16, address control becomes complicated, so during a high-speed search, the address remains constant, that is, even if the sub-block number is the same. For example, it is better to always write to the same address.

In this manner, according to the recording method of the present invention, the following points during high-speed search and during normal playback can be solved or satisfied. Slow playback and still playback can also be performed in color.

[Brief explanation of the drawing]

1 to 11 and 13 to 16 are diagrams for explaining this invention, and FIG. 12 is a system diagram of an example of this invention. 11 to 18C are recording systems.

Claims (1)

[Claims] 1. A color video signal is quantized at a sampling frequency that is K times the color subcarrier frequency (an integer of K≧3), and this quantized digital signal is quantized for L cycles of the carrier color signal (L≧1). (integer) into N channels (N≧2 integer),
A color video signal recording method in which the N divided channels are recorded as N mutually parallel tracks by N rotary heads.