JP2881820B2 - Data encoding circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a digital VTR (video tape recorder).
The present invention relates to a data encoding circuit used for an encoder circuit or the like.

[Summary of the Invention]

The present invention provides a data encoding circuit that distributes an input digital signal for one field to at least two recording channels and divides the signal into a predetermined number of recording blocks, and shuffles the divided signals to perform block encoding. By using a memory having at least three blocks for shuffling and delaying the read timing from the memory of one of the recording channels to correct the recording phase difference between the recording channels, the time for writing to and reading from the memory can be reduced. The margin is enlarged, the allowable phase shift amount between the input video signal and the recording reference signal is enlarged, and the recording phase difference based on the difference in position between the recording heads for each recording channel is corrected by the same memory. Things.

[Prior Art] Digital VT for digitizing and recording video signals
The format of R (video tape recorder) is
There are known a so-called DI format in which component signals of a luminance signal and a chroma signal are digitized, and a so-called D2 format in which a composite signal of a television standard such as NTSC or PAL is directly digitized. In these digital VTR formats, an input digital signal for one field is divided into a predetermined number of blocks, and the divided signals are subjected to block coding by so-called shuffling.

For example, FIG. 4 shows a data encoding circuit on the recording side of a so-called D2 format digital VTR, that is, a so-called encoder circuit.

In FIG. 4, a digital video signal supplied to an input terminal 11 is sent to a line shuffle circuit 12 and
After the effective data in the line (one horizontal period, 1H) is shuffled, it is sent to the outer ECC encoder (or outer parity adding circuit) 13. For example, in the case of so-called PAL system, the input video signal V _in as shown in FIG. 5 IH = 64 .mu.s
After taking out 948 samples as effective data in ec and performing the above-mentioned in-line shuffling, the outer ECC encoder 1
Sent to 3. The word length of each sample data is 8 bits (1 byte). In the case of the so-called NTSC system, as shown in parentheses in the figure, 1H = 63.55 μsec
Thus, the number of valid data is 768 samples. Numerical values in the following description indicate the case of the PAL system, and the case of the NTSC system is shown in parentheses.

The outer ECC encoder 13 divides the shuffled valid data into two channels, that is, channel 0 and channel 1, and then divides the 474 (38)
4) The byte data is divided into six equal parts, and six outer parity blocks are generated by adding a 4-byte outer parity code to the 79 (64) byte data, and the data DPA and DP shown in FIG. 5 are generated.
Output B. These output data DPA and DPB are sent to the sector shuffle circuit 14, and data for one sector 76 (85) lines is written / read to / from the shuffle memory and sector shuffled.

Here, FIG. 6 shows valid data in one field, and 948 (768) samples per line and 304 (25)
5) Sample data of a line is distributed to channel 0 and channel 1 in a so-called checkerboard pattern in which one sample is alternately inverted between lines. Also,
Valid data in one field is 4 every 76 (85) lines
(3) It is divided into two segments, and a channel is composed of channel 0 and channel 1 of each segment. That is, one sector is 474 (384) per line.
Since 76 (85) lines are sampled, the number of sample words or bytes per sector is 474 x 76 = 36024 [words or bytes]: PAL (384 x 85 = 32640 [words or bytes]: NTSC) Become. FIG. 7 shows a data arrangement state in one sector when writing / reading to / from one sector memory provided in the sector shuffle circuit 14. That is, first, 474 (384) words obtained by dividing 474 (384) words per line into six outer parity blocks are obtained.
(64) A four-word outer parity code is added to each block of words, and this is performed for the above-mentioned 76 (85) lines, so that 76 (85) × 6 = 456 (510) bytes in the horizontal direction. A capacity space of 79 (64) + 4 = 83 (68) words is formed in the vertical direction. The data in each line is rearranged (shuffled) at a cycle of 12 samples. Six subarrays (small arrays) of 76 (85) bytes are arranged in the horizontal direction of the sector array. At the time of data recording, the subarrays are sequentially read in the horizontal direction from the lower left corner in FIG. 8 words = 8 bytes of inner ECC per byte sub-array
(Internal parity code) is added. At this time, as shown in FIG. 7, a SYNC (synchronization pattern) and an ID (identification pattern) are added to each of the two inner parity blocks to form one sync block. The first parity block in one sync block is the ID (identification pattern) described above.
Also included.

Referring back to FIG. 4, four sector memories MA1, MA2, MB1, and MB2 are provided in the sector shuffle circuit 14, and are allocated to the channels 0 and 1 from the outer ECC encoder 13, respectively. The obtained sample data is sent to the sector memories MA1, MA2 and MB1, MB2 via the changeover switches SA1 and SB1 in the sector shuffle circuit 14, respectively. FIG. 8 shows the write (W) and read (R) timings for these four sector memories MA1 to MB2 in the case of the PAL system. Two memories of one channel, for example, MA1 , MA2 so that the data for one sector is written to one side and read from the other side. Sector memory
The data of channel 0 read from MA1 and MA2 is output via the changeover switch SA2, and is output from the sector memories MB1 and MA2.
Channel 1 data read from MB2 is output via changeover switch SB2.

Here, the data write operation to the sector shuffle circuit 14 is controlled by a write control signal or the like timing generating circuit 31 is generated based on the synchronizing signal of the input video signal V _in from the input terminal 11, the data read The operation is controlled by a read control signal or the like generated by the timing generation circuit 33 based on a recording reference signal supplied via the input terminal 32. This takes into account that the recording data is output at the timing read from the sector shuffle circuit 14, and adjusts this to the recording reference signal.

Each data of the channels 0 and 1 from the sector shuffle circuit 14 is sent to the SY through the changeover switches 15A and 15B, respectively.
It is sent to the NC, ID, and inner ECC addition circuits 16A and 16B. The output data from the additional circuits 16A and 16B is based on a sync block obtained by adding SYNC (synchronous pattern) and ID (identification pattern) to two inner parity blocks as shown in FIG. A plurality of these constitute a video sector. Audio data, which will be described later, is added to the front and rear positions of the video sector, and the recording data DA and DB for each channel as shown in FIGS.
Is formed. Then, the recording data DA from one of the SYNC, ID and inner ECC adding circuits 16A is channel-coded as it is by the channel coding circuit 18A and is taken out from the output terminal 19A, and the recording data DB from the other adding circuit 16B is delayed. After becoming delay data DDB delayed by a phase difference of a recording head described later in a circuit 17, a channel encoding circuit 18B
And is extracted from the output terminal 19B.

The recording timing signal from the timing generation circuit 33 is
The signal is taken out via the output terminal 34A as it is and via the output terminal 34B via the delay circuit 17. As the basic pulse of this timing signal, for example, the segment pulse SP shown in FIG. 9 can be considered. This segment pulse
SP is a head switching timing pulse for forming the helical track, and has a period of 1/4 of one field in the case of the PAL system (1/3 of one field in the NTSC system).

The recording signal extracted from the output terminal 19A is
The recording signals taken out from the recording heads HA and HC of the rotary head device shown in FIG.
B, sent to HD. Here, the recording heads HA and HB are arranged at substantially the same position, and the recording heads HC and HD are arranged at substantially the same position.
C and HD are 180 ° on the rotating drum 1 rotating in the direction of the arrow r.
The magnetic tape 2 is wound around the rotary drum 1 at an angle range of approximately 180 ° and guided in the direction of arrow t. Are in sliding contact with the magnetic tape 2. For this reason, the recording signal from the output terminal 19A is switched and sent to the side of the recording heads HA and HC that comes into sliding contact with the magnetic tape 2 every half rotation of the rotary drum 1, and the recording signal from the output terminal 19B is The recording heads HB, HD are switched to the side that comes into sliding contact with the magnetic tape 2 by switching every half rotation of the rotary drum 1. At this time, the recording heads HA and HB (or the recording heads
HC and HD), a pair of helical tracks TA and TB (or TC and TD) are recorded and formed at the same timing on the magnetic tape 2 as shown in FIG. In the PAL system, one field of video signal is recorded on four pairs (eight) of helical tracks, whereas in the NTSC system, one field is recorded on three pairs (six) of helical tracks. ing.

By the way, each of the recording heads HA of channels 0 and 1
Since the HBs (or the recording heads HC and HD) cannot be physically arranged at the same position, they are arranged with a predetermined angle difference (for example, 4.22 °) (and a head height difference (not shown)). This is when each print head HA and HB
(Or HC and HD), which is the difference between the drum rotation phase and the difference in the tape sliding start timing, that is, the difference in the recording tamping. Therefore, the recording head HA (HC)
The recording signal of channel 1 supplied to the recording head HB (HD) is delayed by a predetermined time corresponding to the drum rotation phase difference with respect to the recording signal of channel 0 supplied to the recording head HB (HD). The shift of the recording timing based on the phase difference is corrected.

Next, for the audio signal, the sampling frequency is set to 48 kHz, and the sample word length is set to 20 bits. For each audio sector, 240 samples in the PAL system (266 or 267 samples in the NTSC system) 4) are supplied to the input terminal 21 shown in FIG. The input audio signal AU _in is converted by the byte conversion circuit 22 such that 5 words of 8 bits are assigned to the 2 samples of 20 bits. Auxiliary data is added, resulting in 608 (680) bytes of data per audio sector. In the outer ECC addition circuit 24, 4
An outer parity block to which an outer parity code of bytes is added is generated as 76 (85) blocks. In the next audio fuffling circuit 25, sector shuffling is performed by collectively writing the outer parity blocks for one sector into the shuffle memory and then reading out the data. Therefore, the data written to the audio shuffle memory is (8 + 4) × 76 × 4 = 3648 [bytes]: PAL ((8 + 4) × 85 × 4 = 4080 [bytes]: NTSC). From the audio shuffle circuit 25, at each timing according to the format of FIG.
0, AU1, AU2, AU3 are read out and changeover switches 15A and 15B
And SYNC, ID and inner ECC adding circuit 1
Sent to 6A and 16B. Each audio data AU0 ~
AU3 is double-written respectively. For example, the audio data AU0 and AU1 in the area sent to the head HA in the recording data of channel 0 shown in FIG. 9 are the audio data in the recording data of channel 1 immediately before. It is the same as AU0 and AU1. Therefore, the recording track corresponding to one segment of the audio signal and the video signal is as shown by the hatched portion in FIG. 11, in which the audio data of the four sectors on the upper end side of the tape is the fourth copy, and the lower end side is the second copy.

[Problems to be solved by the invention]

By the way, the timing of writing / reading data to / from the memories MA1 to MB2 in the sector shuffle circuit 14 in the so-called D2 format is very tight, and especially in the case of the PAL system, it is clear from FIG. As you can see, there is little time to spare. Moreover, the actual video data writing timing is shifted by several lines in accordance with the sequence of the color field, so that the margin is further reduced. In addition, if there is a phase shift between the input video signal and the recording reference signal, the write operation and the read operation may overlap, and there is a risk that normal operation may not be performed.

In addition, a delay circuit 17 is required to correct a recording phase difference caused by a difference in the position of each recording head between the channels 0 and 1 and a shift in head sliding contact timing, and a delay memory for this is required. Become.

The present invention has been made to solve such a drawback, and not only can the time margin for writing / reading data to / from a memory be expanded, but also the correction of a recording phase difference between recording channels can be performed. It is another object of the present invention to provide a data encoding circuit which does not require a dedicated delay memory.

[Means for solving the problem]

As shown in FIG. 1, a data encoding circuit according to the present invention distributes an input digital signal for one field to at least two recording channels (for example, channels 0 and 1) and a predetermined number (for a PAL system, for example). 4. In the case of the NTSC system, in a data encoding circuit for dividing into 3) recording blocks (video sectors) and shuffling (sector shuffling) to block-encode the divided signals, a memory for shuffling is used. At least three blocks (sector memories MA1 to MA3 or MB1 to MB3) are used, and the read timing from at least one recording channel memory (MB1 to MB3) is set to the other memory (MA1 to MA3).
The above problem is solved by correcting the recording phase difference between the recording channels with a delay compared to the read timing from 1 to MA3).

[Action]

By configuring the shuffling memory with three blocks (three video sectors), the time margin for writing and reading to and from the memory is expanded, and the allowable phase shift amount between the input digital signal and the recording reference signal is expanded. Also, by correcting the recording phase difference based on the difference in position between the recording heads for each recording channel with the same memory,
There is no need to separately provide a delay memory for correcting the recording phase difference.

〔Example〕

FIG. 1 is a block circuit diagram showing a data encoding circuit as one embodiment of the present invention. The data encoding circuit of this embodiment is a so-called D2 format digital VTR.
This is preferable when applied to a recording-side encoder circuit of a (video tape recorder).

In FIG. 1, a digital video signal in which one sample word is 8 bits (1 byte) is supplied to an input terminal 11. The input video signal V _in is sent to the line shuffling circuit 12, the valid data in one line is shuffled. The outer ECC encoder 13 divides the shuffled valid data into two channels, that is, channel 0 and channel 1, then divides each channel data into six equal parts, and adds a 4-byte outer parity code. Then, the data is sent to the sector shuffle circuit 10 for each channel. The above is the same as the description of FIG. 4 described above.

The memory in the sector shuffling circuit 10 has a three-block configuration for each channel, and each has a memory capacity of three sectors. That is, three sector memories MA1 to MA3 are stored for channel 0, and three sector memories MA1 to MA3 are stored for channel 1.
Two sector memories MB1 to MB3 are provided, and writing (W) and reading (R) are controlled with respect to these memories MA1 to MA3 at timings shown in FIG. For example, for sector memories MA1 to MA3 of channel 0, while writing to memories MA1 and MA2, memory MA3
From the memory MA2 while writing to the memories MA2 and MA3, and reading from the memory MA2 while writing to the memories MA3 and MA1. The same applies to the sector memories MB1 to MB3 of channel 1. Thereby, writing (W) / reading (R) of each memory is performed.
Of the input video signal and the terminal, not to mention that the time margin of
Even if a phase shift occurs with respect to the recording reference signal supplied to 32, for example, a phase difference of about several tens of lines can be sufficiently dealt with, and the allowable phase shift amount can be increased.

Further, a timing generation circuit 33A for channel 0 and a timing generation circuit 33B for channel 1 are provided independently,
By delaying the read timing for the sector memories MB1 to MB3 of channel 1 by the rotational phase difference between the head pair HA and HB (or between HC and HD) before the memory read timing of channel 0, for example, a delay using a counter or the like With the simple configuration of simply providing the device 36, the head rotational phase difference can be compensated, and the delay circuit 17 of FIG.
The circuit configuration can be greatly simplified.

Since the other configuration and operation of FIG. 1 are the same as those of the circuit of FIG. 4, the same reference numerals are given to the corresponding portions, and the description will be omitted.

Here, the sector memories MA1 to M1 used in the actual circuit
Considering A3 (or MB1 to MB3), the available capacity of the memory IC is usually a power of two, so that the conventional two sector memories MA1 to MA2 (or MB1 to MB3) are used.
It can be seen that the number of parts (the number of memory ICs) does not increase or decrease when using the three sector memories MA1 to MA3 (or MB1 to MB3) as in this embodiment. That is, the capacity of the sample data of one video sector is 37848 bytes in the PAL system (34680 in the NTSC system).
Bytes, the same applies hereafter), and 75696 (6936
0) bytes. Since this is larger than 2 ¹⁶ = 65536, a memory IC having 2 ¹⁷ = 131072 bytes must be used. On the other hand, in order to obtain a memory capacity of 113544 (104040) bytes in three video sectors as in the present embodiment, the above-mentioned memory IC of 2 ¹⁷ = 131072 bytes is sufficient, so that an actual circuit is configured. Above, there is no need to increase the number of memory devices. FIG. 3 shows a division form or a mapping form of the memory device at this time.
In FIG. 3, each memory block M1 to M3 corresponds to each of the sector memories MA1 to MA3 (or MB1 to MB3),
In the figure, the values for the PAL system are shown, and NTS is shown in parentheses.
Numerical values for the C method are shown.

Note that the present invention is not limited to only the above-described embodiment. For example, the audio shuffling memory may be divided and provided (shared) in the same memory IC. The memory may be configured with four blocks (four sectors) or more. In addition, it goes without saying that various changes can be made without departing from the spirit of the present invention.

〔The invention's effect〕

According to the data conversion circuit of the present invention, since a memory for shuffling for block encoding (for example, sector shuffling in video sector units) adopts a three-block (three video sectors) configuration, The time margin for writing / reading to / from the memory is greatly increased, and for example, the allowable value of the phase shift between the input digital signal and the recording reference signal can be greatly expanded. In addition, since the shift of the recording timing caused by the difference in the position of the recording head for each recording channel can be simultaneously performed by also using the above memory, it is not necessary to separately provide a delay memory for correcting the deviation. Thus, the circuit configuration can be simplified.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing a schematic configuration of an embodiment of a data encoding circuit according to the present invention, FIG. 2 is a time chart for explaining the operation, and FIG. 3 is a division of a memory device constituting a sector memory. Fig. 4 shows the form.
FIG. 5 is a block circuit diagram showing a conventional example of a data encoding circuit as an encoder circuit provided on the recording side of the VTR. FIG. 5 is a time chart showing valid data and an outer parity block in one line of an input video signal. FIG. 7 is a diagram showing channel distribution and segment division of valid data in one field, FIG. 7 is a diagram showing an arrangement state of sample data in one sector and a sync block, and FIG. 8 is a diagram for each sector memory in a sector shuffle circuit. 9 is a time chart for explaining write / read operations and recording data, FIG. 9 is a time chart showing recording data corresponding to a recording track, FIG. 10 is a schematic plan view of a rotary head device, and FIG. 11 is a magnetic tape FIG. 3 is a schematic front view showing an upper recording track pattern. 10 Sector shuffle circuit 11 Video input terminal 12 Line shuffle circuit 13 Outer ECC addition circuit 14 Sector shuffle circuit 16A, 16B SYNC, ID, inner ECC addition circuit 17 Delay circuit 21 …… Audio input terminal 24 …… Outer ECC addition circuit 25 …… Audio shuffle circuit MA1 to MB3 …… Sector memories 31, 33 …… Timing generation circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G11B 20/10 G11B 20/12 G11B 20/18

Claims (1)

(57) [Claims] 1. A data encoding circuit for distributing an input digital signal for one field to at least two recording channels and dividing it into a predetermined number of recording blocks, and shuffling the divided signals for block encoding. A data encoding circuit comprising: a memory for shuffling having at least three blocks; and a timing for reading from at least one recording channel from the memory is delayed to correct a recording phase difference between the recording channels. .