JPS62149207A - Current conversion circuit - Google Patents

Abstract

PURPOSE:To attain linear conversion or nonlinear conversion, to apply the titled circuit to a function conversion such as multiplication of division and to improve the degree of freedom of a conversion coefficient by providing a coupling circuit comprising plural-stage of transistors (TR) and a differential amplifier or the like. CONSTITUTION:The coupling circuits Fa, Fb consist of m-stage (m>=1) of TRs Qa1...Qam and Qb1...Qbm respectively, and a bias voltage is applied to bases of the 1st stage TRs Qa1, Qb1 from a bias power supply VB1. The emitters of the TRs Qa1, Qb1 are connected to the base of the TR of the next stage, the TRs are connected similarly sequentially and an output terminal of the circuits Fa, Fb is connected to the bases of TRs Qy, Qx constituting the differen tial amplifier. In connecting the collector of the TR Qy to any emitter of one of the TRs Qb1...Qbm, a junction voltage of the connected TR is proportional to a current Iy. Thus, the linear conversion or nonlinear conversion is attained and the titled circuit is applicable to the function conversion such as multiplica tion or division and the degree of freedom of the conversion coefficient is im proved.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to current conversion circuits, and the present invention relates to semiconductor integrated circuits (2% of current conversion circuits).
It can be easily integrated into an IC (IC) and is suitable for use in amplifier circuits, etc.

[Technical background of store opening]

An example of a conventional current conversion type amplifier circuit is shown in FIG.

In FIG. 14, transistors Ql and Q2 are each supplied with a voltage from a reference bias voltage source VBI, and a transistor Q3 whose emitter constitutes a differential amplifier.
．． Connected to the pace of Q4. Each transistor Ql
, Q2 are connected to the voltage source Vcc, and the collectors of transistors Q3 . Q40 pace has two input terminals PI and P''-
Q3. The emitters of Q4 are commonly read and connected to a reference potential point (earth) K via a constant current source ISI. and transistor Q3. The collector of Q4 is connected to output terminals P3 and P4.

When determining the relationship between input and output in the circuit shown in FIG. 14, the following equation holds true from FIG.

VB]-4F]-Vy4=VB1-VF2-VF3
−・(1)Yaw)teVFx+VF4=Vn2+VF3・
-(2) (However, VFI~VF4 is the transistor Q1~
This is the pace-emitter voltage of Q4. ) It is well known that the pace-emitter junction of a transistor (including a diode) is given by the following equation.

T In ...(3) VF=lower “t” However, K is Boltzmann's constant and T is the absolute temperature.

T is the electron charge, In is the emitter current of the transistor (
(substantially collector current), Is is the saturation current of the transistor.

If the circuit shown in FIG. 14 is constructed on a semiconductor substrate, the transistors Q1 to Q4 can have substantially the same characteristics.
The emitter current or collector current of each transistor is II to I4. The current flowing through the input/output terminals P1 to P4 is I
Assuming p1 to IP4.

■U=IP], l2=IP2. l3=IP3. l4=I
It is P4.

Substituting equation (3) into equation (2) yields.

IP]・IP4=IP2・IF5・
...(4) holds true. Also, the current value of the current source I s ]- is.

l51=IP3-4-IF5...
- (5), which follows from equations (4) and (5).

- In this way, an output signal responsive to the input signal is obtained at the output terminal.

[Problems with background technology]

It can be seen from the above equation (6) that if Ipco or IF5 is used as an input signal, IF5 does not become a linear output function, and '
Although the current conversion type has advantages, it has the disadvantage that linear conversion cannot be performed due to nonlinear conversion. Furthermore, there is no degree of freedom in setting conversion coefficients such as amplification and attenuation, and its applicability is limited.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a current conversion circuit that can perform linear conversion and nonlinear conversion, and can also be applied to functional conversion such as multiplication and exponentiation, and has an increased degree of freedom in conversion coefficients.

[Summary of the invention]

The present invention provides a first
．． a differential amplifier comprising a second transistor;

m by a transistor pace-emitter junction or a diode junction equivalent to this pace-emitter junction characteristic.
(m≧1) semiconductor junctions, and if 2m>1, the first. a second junction circuit, in which at least each first stage consists of a pace-emitter junction of transistors, the paces of the first stage transistors are connected to a bias power supply, and the output terminals of each final stage are connected to the first stage, respectively;
．． and the one connected to the pace of the second transistor.

means for connecting the collector of the first transistor to the output of a semiconductor junction of one of the second junction circuits;

a third transistor having a conductor connected to the bias power source and an emitter connected to the collector of the second transistor;

Said 1st. input current supply means connected to the output end of the semiconductor junction of at least one stage of the second junction circuit;

A current conversion circuit comprising means for extracting an output from a line connected to at least one of the collector of the first transistor and the collector of the third transistor.

[Embodiments of the invention]

The circuit of the present invention will be explained with reference to the drawings. Prior to the explanation, each symbol used in one sentence will be defined as follows.

n as a subscript indicating a series of numbers Qn:) Ranjistor.

Dn: Diode or transistor configured as a diode.

Rn: resistance and resistance value.

Cn: Capacitor and capacitance value.

Pn: terminal.

Vcc: power supply and voltage value.

VB port: Bias power supply and bias voltage value.

VF:) Junction and junction voltage between the pace and emitter of a transistor.

Vpn: VF value of Qn, or voltage value across Dn.

The emitter current or collector current of In:Qn (the current amplification factor is sufficiently large so that both are substantially equal) or the diode current flowing to Dn, and their current values.

IPn: Current flowing through Pn and current value.

ISn: Constant current source and constant current source value when In is used as a special voltage current source.

Ion: DC component and DC value when In is divided into DC and AC components.

ΔIn: AC component and AC value when In is divided into DC and AC components.

β: Current amplification factor Figure 1 shows the basic configuration of the present invention, with 2m stages (m≧1
) transistor Qa1...Q a m and Qb
l...Qbm constitute junction circuits Fa and Fb, and a bias voltage is supplied from a bias power supply VBI to the first stage transistors Qal and Qbl. The emitters of these transistors QaxtQbl are connected to the paces of the transistors in the next stage, and in the same way, the transistors in each stage have their paces connected to the emitters of the previous stage, their emitters to the paces of the subsequent stage, and the final stage transistor Q a m.

The emitter of Qbm, that is, the output terminal of the junction circuits Fa and Fb is a transistor Qy that constitutes a differential amplifier.

Each is joined to the pace of Qx.

Qax...Qam and Q b 1. −=Qb
The collector of (m-1) is connected to the voltage source Vcc and +Q”
The collector of is connected to the emitter of the transistor riff,
The collector of Q7 is connected to the output terminal Px, and also Q b
The collector of m is connected to the output terminal PY. The collector of Qy is connected to the emitter of the transistor of junction circuit Fb (emitter of Qbm). Furthermore, Q7
The pace of is connected to the bias power supply vB].

Also, terminals Pal...Pam, Pbl...Pbm
are each transistor Qal...Qam, Qhl...
- Q b is a current supply terminal connected to the emitter of m, and terminal PO is a current supply terminal connected to the common emitter of Qx and Qy.

If the circuit shown in FIG. 1 is constructed on the same semiconductor chip, each transistor can be made to have similar characteristics, so equation (3) can be applied to each transistor.

From FIG. 1, the following conditional expressions hold true. However, the presence of the transistor Q7 is not included for convenience's sake, and it is assumed that β of each transistor is large and the base current of the transistor can be ignored.

Further, it is assumed here that no current is supplied to the terminal Pbm.

VB 1-(VFal-)-=+VFam) 2V'F
Y=vBl-(VF'b1+-+VFbm)-VTPx
... (8) Rearranging equation (8).

VFal+・+VFam+vFY=VFbkoten−・+
VFbrn+Vyx ---(9) (9) Formula (
3) Substituting into the equation yields K as follows.

Ial*-・-*IamsIY=I))la-・-*I
bmaIX ・(10) Using equations (7) and (10).

Ib]--Ib (m-1) Ipb]--Ipb
(m-1) (11) Ipy=Ipo-Ipx
-(12)(+1) and (12) have a mutually antiphase relationship and can be used as a differential output of a general differential amplifier.

Various current conversion functions can be easily created by selecting either the input current (input signal) or the fixed current (bias) as the terminal current term on the right side of equation (11).

(A) to (F) K An example will be described.

(A) When one of the terms of one molecule is input (for example, lPa1), lPh1...IPb(rr?-1)...(13
) This is a linear current conversion function. If Kl〉1, P12
1 circuit, Q(Kl(1) is an attenuation circuit.

If K1=1, it becomes a 1:1 current conversion circuit.

(B) Two or more terms of one molecule are input (for example, lPa1.
lPa2), Ipbx *-...IPb(m-1)...(14) This is a multiplication (product) function, and if 2=1, it will be a complete product output.

(C) 9 When one of the numerator terms and one of the denominator terms is human power (e.g. Ipal, Iph]), this is a function of the reed (quotient), and when 3 = 1, the output of the complete quotient becomes.

(B) and (C) can also be applied using one input as an input signal and the other input as a gain control signal.

Generally, if you include the input signal term in the numerator and denominator, Ix can create 14 numbers that are a combination of products and quotients. For example, when used in a logic circuit, IPan and lPbn are ゝゝ0.
If the input signal is #□1#, it will be A for IPan human power.
A NAND circuit can be used for the ND circuit and lPbn input.

(D) Two numerator terms are inputs of n I III and n
One input is equal (for example, Ipax=Ipa2=...
...=IPanx input denominator term has 02 inputs and n2 inputs are equal (for example, Ipb1=Ipb2=-
・-・==IPbn2) When...(16) This is a power function. If Ipa] = Ipb] then I
x=ni4(Ipal)n1n2 −・−・(
17) nl) If n2, then (nl-n2) power conversion function, n
If l(n2, then it becomes the reciprocal function of the conversion function to the power of (n2-nl).

In (E) and (D), if only molecules are input (n2=
(equivalent to 0) IPbl・・・・・・・・・IpbmThis is n1
It becomes a power conversion function.

In (F) and (D), if only the denominator is input (corresponds to nx=o)...(19) This becomes a squared reciprocal conversion function.

As described above, various conversion functions can be easily created using Figure 2.

In Figure 1, where such characteristics can be obtained, (1
1) To obtain a function like the formula, the current proportional to Iy is F
This means that the collector of Qy is connected to the emitter of any one of qbx to Qbm, and the junction voltage of the connected transistor is proportional to IY. This is a configuration in which a current flows. Conversely, by placing a transistor between Q a l and Q a m in which a current proportional to Ix flows, the emitter potentials of rQ7 and Qb become equal, and in other words, the emitter potentials of Qx and Qy become equal. Since the collector potentials are equal, the collector-emitter potentials of QX and QY become equal, and the influence of the Early effect can be eliminated, and good symmetry characteristics between IPX and IPY can be obtained.

Furthermore, although the junction circuits Fa and Fb are shown as m-stage configurations of NPN transistors in FIG.
type transistor junction.

Any combination of diode junctions (pace-collector shorted transistors) and any number of stages of Fa and Fb are possible.

Next, specific examples will be described.

FIG. 2 shows a simple example in which both junction circuits Fa and Fb are arranged in one stage. In this case, one transistor serves as both the first stage and the last stage.

In FIG. 2(A), the collector of Q8 is connected to the emitter of transistor Qal, and the emitter of Qa is connected to resistor R,
1 to the reference potential point (earth). The pace of Q8 is also connected to terminal P3. The collector of Q9 is connected to the emitters of Qx and Qy, the emitter of Q9 is connected to the ground point via a resistor R2, and the pace of Q9 is connected to terminal P4. In addition, terminals Px and Py are resistive loads R13
, R4 to the voltage source Vcc.

In Figure 2, Ipax in Figure 1 corresponds to I8, and Ipax in Figure 1 corresponds to I8.
po corresponds to engineering 9. Terminals P3 and P4 are connected to a predetermined bias VB3. It is assumed that VB4 is applied.

Now, assume that a DC voltage component EO3 and an AC voltage component ΔEO3 are applied to the terminal P3, and a DC voltage component BO4 is applied to the terminal P4.

I 9=I O9=□ ・・・・・・・・・(
21) (However, v'P=vF8#v'IP9)I
The relationship between px and force 8 is as shown in Figure 2 (B).

The operating point changes depending on what value Ioa is set to IO9. For example, 30 points in Figure 2 (B).

Consider point bO and point co. aOX and aOY are both l0
This is the case where 8=IO9 is set.

aox (Ioa9. l09) is the operating point at output terminal Px, a OY (IO9, O) is the operating point at output terminal Py
This is the operating point at . The AC component ΔIos has a half-wave detection effect at each of these points.

The bO point is when l08=10.

This is a trap for the same operating point at the output terminals PK and PY. Also, 00 points are when IO8<-T-K is set.

The output is.

IPx=Io8+ΔWork08〈l09・・・(22)I
PY=IO9-(Ios+Δtechnical08)...
・(23) becomes. Looking at equation (23), if IO9 is varied, the DC level amount of (IO9-108) will change.

The output at terminal PY is of variable level shift type and has an opposite phase (P
1 to 1) for x. Looking at equation (22), the waveform of ΔIos can be sliced by varying IO9.

Next, consider the case where R03 is applied to the terminal P3 and E04+ΔEO4 is applied to the terminal P4.

l8=IO8, l9=IO9+ΔIO9...(24
).

Since IPX=IO8, IPY=IO9+Δl09-Ioa ・-
(25), the signal amplified by the transistor Q9 passes through Qy and appears at the terminal Py, and the amount of level shift can be controlled by controlling Ios. Such control can be applied, for example, to brightness signal control of color television receivers.

Generally, a differential amplifier is used when outputs of the same amplitude are obtained with mutually opposite phases. On the other hand, considering the conditions of direct connection between two circuits, when the differential amplifier input is directly connected to the previous stage, offset is likely to occur unless the DC bias between the two points is equalized as a differential input, and it has the disadvantage that it is difficult to ensure linear operation. are doing. In this regard, in the circuit shown in FIG. 2, when the terminal P3 is directly connected to the previous stage, VB1. The potential of terminal P4 can be set independently if the dynamic range is set to an appropriate size, and direct connection is easy.

Next, FIG. 3 shows another embodiment of the present invention. This figure 3 shows * Qa, Qa2 connected to Darlington, Qbz
, Qx are connected by Darlington. Terminal Pa2 is connected to Q a 2, and QX.

The emitter of Qy is grounded via a current source Iso.

In the case of a one-stage configuration as shown in FIG. 2, if β is sufficiently high, the linearity may deviate as shown by the dashed-dotted line in the region near aOX where the limiter is applied due to the characteristics shown in FIG. 2(B). This is because as Ix increases and Iy decreases, the collector current of Qy attenuates, but on the other hand, the base current of Qx increases and cannot be ignored, and even if Is is increased, the emitter current of Qbl decreases. This is because it does not decrease sufficiently.

In FIG. 3, the effect of the pace current of Qx described above can be reduced, and since the pace current of Qx further terminates at Qb2 and flows to the emitter of Qbl, it has almost no effect.

FIG. 4 shows an embodiment of differential voltage input and differential current output.

Connect the base of Q a 1 to input bin P4. Connect the base of transistor Q]0 to input bin P3, and
:Qa] are connected to the emitters of current sources IS2. Connect ISN and connect R5 between the emitters.

Terminal P3. Assume that the following input is added to P4.

To P3 Bp3=Eop3+ΔEP3...
(26) To P4 Ep4=Eop4+ΔFSP4
...(27) However, gop3. Eop4 is a DC potential, and ΔEp3°ΔEP4 is an AC input. Here, Eops=Eop4. Further, it is assumed that l52=IS1. Since no direct current flows through the equation 5, the following equation is obtained.

R, 5 Since it can be approximately set as Vy a 1#Vp 1o (26
)formula.

Using equation (27), the AC component of Is is therefore P3. It is proportional to the difference input between P4.

Next, FIG. 5 shows a multiplication circuit in which m=2K junction circuits Fa and Fb are selected. In this circuit, Qa 1゜Q a 2
Terminals Fax and Pa2 are connected to the emitter of Qbz, and a current source ISb2 is connected to the emitter of Qbz.

The input/output characteristics of this circuit are given as follows.

This circuit serves as a multiplication circuit for an input signal of DC or DC plus AC as an input condition, but in the case of only AC, an input component is generated in addition to the multiplication component. Now let's call IPa and Ipaz. Iopax and Iopa2 are DC components.

ΔlPa1. ΔIpa2 is an alternating current component. Substituting equation (30) into equation (29) yields.

becomes. If Iopal and Iopa2 are input bias values, the output will be the 2.3.4 term on the right side, but only the 4th term is a multiplication proportional output, and the 2nd and 3rd terms need to be removed.

An example for removing the second and third terms above is shown in FIG.
It is shown in FIG.

Figure 6 CQ a 1. Q a 2 collector and terminal P
y is connected to output terminal Pro, and Q7. The collector of QM is connected to voltage source Vcc. From the figure, IPyo=IpY+Ia1-1-Is2-・(32)I
PY is from formula (2) and formula (31), and Ial is I
pax and Is2 is Ipaz, so equation (32) is ΔlPa1−ΔlPa2 - □ ... (33) Sb
It becomes 2. Here, if l5b2=Iopa1=Iopaz, equation (33) becomes, and if the AC component of 1 PYO is ΔIpyo, the AC multiplication output can be obtained.

FIG. 7 shows another AC multiplier circuit in which the collector of *Q"+Qa2 is connected to a current mirror (Qll.

Connect to the input of Ql2) and output (collector of Ql2)
is connected to the terminal PK, and the connection point between the collector of Qb2 and PK is the output terminal Pxo.

From the figure, the IPKO is as follows.

Ipxo=Ipr-Ixz+IsM ---
(36) Since 112 is the sum of Ipal and Ipaz (
Equation 36) uses equation (31), where l5b2=IOPa1. If = IOPa2, then
Equation (37) is obtained, where P(0 is the output of only the alternating current component).

In this way, Pxo as shown in FIGS. 6 and 7.

By canceling the component proportional to the PYO input signal, the multiplication output can be obtained. still.

There are various methods other than those shown in Figures 6 and 7.

Depending on the input conditions, the multiplication circuit can be applied to a squaring circuit or a frequency doubling circuit.

For example, in FIGS. 6 and 7, by inputting ΔIpa]==wIpa2, a square circuit for AC signals can be created.

In addition, in Fig. 5, the input is Ipa] = Iopa] + ΔIpal... (41) I
paz=Iopaz-1-xIpa2=Iopax-<
If the condition is Ipal-.(42), then the equation (29) is obtained, and the squared output can be easily obtained.

Note that equations (41) and (42) are calculated using differential amplifier Qx3. It can be easily made by using Qx4 and connecting the collectors to Pal and Pa2, respectively.

In addition, the square circuit can also be obtained by expanding FIGS. 6 and 7 into FIGS. 9 and 10.

In both of these, Q a 2 is replaced with a diode Da2. Using Figure 9, sM...(44) Ipyo=Iso-4P! -1-Work Pa2sba Here, if we choose 2 IOP a 2=I S b 2, then ΔI p Y O=--(ΔIpa2) 2 -
... (47)sb2. FIG. 10 can also be obtained in the same manner.

Furthermore, in the circuits shown in Figures 6 and 7, if the input condition is an AC signal and signals with a phase shift of 90 degrees are used, the frequency is 2.
It becomes a multiplier circuit. now.

IPal=IOPal-1-IMSstnωt
- River (48) Ipa2=IopalIya ca1
Let ωt −·(49).

ΔIpal=IMs sinωt, ΔIPa2=I
Mc cos ωt −(50), so 1 For example, (5
By substituting Equation 0) into Equation (38), IMC. In FIG. 11, only a part of the input is shown, and Fax and Pa2 are constant current source sa1. l
5az and a resistor R5 between input terminal P7 and Pax.
Also, a capacitor C1 is interposed between P and Pa2.

If the alternating current component at P7 is ΔE7, then ΔI Pa 1=-*ΔEI7 ΔIpaz=j ωc, *ΔEy, and ΔIpayu and ΔlPa2 are signals with a 90 degree difference.

Further, according to the present invention, a circuit with cubic characteristics can also be realized.

Figure 12 shows a cube circuit where Qal, Daz, Da
3).

(Qbl, Qb2. Dbs), Q y , Q
x, Q7.

Qal-1, Qb2-1. QY-x, Qx-1,Q
7-1 each transistor, and Iso, l5b3
．． Current source of l5o-1, l5b3-1, Pa3.
Pxl, PY2. It has a Pxo terminal. From the figure, Iax=Ipa3 Ipa3 is Ipas=Iopa:y, +ΔIpa3
−= (54), the output is IPKO=Ia+
IP'XI-)-IPY2+□(ΔIpas)3...
−(55)(Isbs)” In equation (55), the condition where the coefficient of the term ΔlPa3.(ΔIpas) becomes zero is determined. In this case, equation (55) is therefore ΔI P M O = −□ −(ΔI P a
3) 3, and only the 3(Isbs)3 power component is obtained.

Further, FIG. 13 shows another embodiment of the present invention.
This is a circuit in which a conversion circuit L1 made up of type transistors and a conversion circuit L2 made up of PNP type transistors are combined in parallel. (In) is a block diagram, (B) is a concrete circuit, (
C) shows the characteristics.

This circuit is a circuit in which Ll works when the input signal applied to terminal Pz is positive, and L2 works when it is negative (C)
No. 1. Obtain characteristics in the I quadrant.

The operating input point is Ipz=Q as a bias. It is also possible to obtain different gains for positive and negative.

Further, the present invention can realize various circuits other than those described above by setting input signal conditions, etc., and its application range is wide.

〔Effect of the invention〕

As described above, according to the circuit of the present invention, linear characteristics and limiter characteristics can also be obtained. Also, it is possible to obtain a negative phase output (differential type).

Furthermore, it is possible to create circuits with power characteristics such as multiplication and division by 1, 2 and 3, and also 1 frequency doubling circuits. In addition, current differential input and current differential output are possible, and the range of applications is wide.

These circuits are suitable for semiconductor integration, are stable against temperature and element fluctuations, are in current mode, are advantageous for lower voltages, and are capable of microcurrent operation, reducing power consumption. It also has the effect of being able to stabilize β.

[Brief explanation of drawings]

Schematic drawings and characteristic diagrams, FIGS. 3 to 12 are circuit diagrams showing other specific embodiments, FIG. 13 is a block diagram and circuit diagram showing still other specific embodiments, and their characteristic diagrams, and FIG. 14 1 is a circuit diagram showing a conventional current conversion circuit. Fa, Fb... Junction circuit Qax~Qam, Qb Yu~Qbm... Transistors forming the junction circuit. Q7... Transistor. QX, QY...Transistors that form a differential amplifier. Pax ~Pam, Pbx-Pbm, Po...
Magnetic current supply terminal. Px, Py...output terminals. Inn...Current source. vBl ... Bias power supply agent Patent attorney Nori Ken Yudo Uji Hiroshi Uji1'a1 Pan I'(11'bm P
bl Fig. 1 vcc PY px M2 Fig. 3 Fig. 4 Fig. 11 Yllx Fig. 5 CC AC lit calculation Fig. 6 Fig. 7171 1'Y + to Fig. 8 Fig. 9 Fig. 10 Fig. 11 VCCP IO Fig. 12 IPKO・IPTO Figure 13

Claims (1)

[Claims] A differential amplifier comprising first and second transistors whose emitters are commonly connected to a reference current terminal, and a base-emitter junction of the transistors or a diode junction having the same base-emitter junction characteristics. m by
(m≧1) semiconductor junctions, and if m>1, they are connected in series, and at least the first stage consists of a base-emitter junction of a transistor, and the base of the first stage transistor is biased. A first junction circuit connected to a power supply and having an output terminal of the final stage connected to the base of the first transistor, and m semiconductor junctions (m≧1) similar to the first junction circuit. If m>1, they are connected in series, and at least the first stage consists of a base-emitter junction of a transistor, the base of the first stage transistor is connected to the bias power supply, and the output terminal of the final stage is connected to the second transistor. a second junction circuit connected to the base of the first transistor; means for connecting the collector of the first transistor to the output of a semiconductor junction of one of the second junction circuits; and a base connected to the bias power supply. , a third transistor whose emitter is connected to the collector of the second transistor; input current supply means connected to the output end of the semiconductor junction of at least one stage of the first and second junction circuits; A current conversion circuit comprising means for extracting an output from a line connected to at least one of the collector of the first transistor and the collector of the third transistor.