JPS6142885B2 - - Google Patents

Description

Detailed Description of the Invention The present invention relates to a signal processing device that can be used in modulation circuits and phase detection circuits, which has little leakage between two input signals, is not affected by mismatching of resistive elements, and does not require adjustment. The object of the present invention is to provide a signal processing device suitable for semiconductor integration.

As a conventional example, a balanced modulator composed of cross-connected differential amplifiers will be explained with reference to FIG.

In FIG. 1, the current flowing through each circuit can be expressed as I ₁ +I ₂ =I ₅ I ₃ +I ₄ =I ₆ I ₅ +I ₆ =I ₇ .

In a modulator circuit, a linear response of the circuit to an input signal is required for only one input. This linear input is the modulation input and is represented by V ₂ in the figure. Yet another input V ₁ in the circuit is a carrier wave input and is driven with a constant amplitude signal. The input level of modulation input V ₂ is (V _T ...approximately 26 mV at emitter current 1 mA)
As shown in Figure 2, the input range is severely limited, and the stability of _the circuit due to temperature is also _poor . The method used is to insert a series resistor Re. In this case, I ₅ Re≫V _T , I ₆ Re≫V _T , and the current difference between I ₅ and I ₆ is directly proportional to the input signal V ₂ , so the range in which the modulation input operates linearly is It can be expanded.

However, by connecting the series resistor Re to the emitters of the transistors T ₅ and T ₆ , the mismatch between the currents _{I 5} and I ₆ caused by the mismatch of the resistor elements _becomes Even when the base potentials are equal, that is, when the modulation signal _V2 is zero, a DC offset will occur at the corresponding terminals, which is a drawback that significantly reduces the performance of the circuit. The above-mentioned mismatching of resistive elements, etc. is an unavoidable problem even with semiconductor integration, and is a cause of deteriorating characteristics such as carrier wave suppression in a balanced modulator. For example, in the circuit shown in Figure 2, the matching accuracy of the emitter series resistor Re is about 2% in semiconductor integrated circuits, but due to the influence of this mismatch, the carrier wave suppression ratio is -34 dB, which is satisfactory. Suki characteristics cannot be obtained. Therefore, in normal use, an adjustment circuit is added outside the IC to adjust this mismatch. For this
This increases the number of IC terminals and increases the number of man-hours required for adjustment.

The present invention aims to provide a device that does not require such an external adjustment circuit, and embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 shows a circuit diagram of a balanced modulator in one embodiment of the present invention. A common DC power supply 19 is connected to the bases of transistors 1 and 2 of the emitter follower circuit.
A DC bias is applied to the transistor 1 through resistors 17 and 18, respectively, and a modulation signal source _S1 is further connected to the base of the transistor 1.

Current sources 20 and 21 having the same current value are connected to the emitter of the transistor 1 and the emitter of the transistor 2 constituting the emitter follower circuit, and through resistors 13 and 14 having the same value,
The collectors of transistors 3 and 4 are connected. The emitters of the transistors 3 and 4 are differentially coupled and connected to a current source 25, and a carrier wave input source _S2 is connected between their bases.

The transistors 7 and 8 are transistors that are selected depending on their levels, and their emitters are coupled and connected to a common current source 22, and an output signal is taken out from a terminal 36. 2
5 is a current source connected between the emitters of transistors 3 and 4 and ground.

The circuit operation of the device shown in FIG. 3 will be explained using FIG. 4. The signal of the carrier wave input source S ₂ is as shown in FIG. 4a, and the signal of the modulation input source S ₁ is as shown in FIG. 4b. By means of a common power supply 19, transistors 1 and 2
Assuming that the DC levels given to are J and l in Figure 4 c and d, the emitter of transistor ₁ has a waveform (Figure 4 c ) will appear. Since current sources 20 and 21 are connected to the emitters of transistors 1 and 2, respectively, the emitter potential becomes a voltage lower than the base potential by the base-to-emitter potential, and its output impedance is independent of the emitter potential. Since the emitter current is caused to flow by a constant current source, approximately re=V _T /I _E , which is a sufficiently low value compared to the resistors 13 and 14 .

(However, I _E ...emitter current flowing to transistors 1 and 2 from current sources 20 and 21) Also, since the collectors of transistors 1 and 2 are connected to the power supply, they function as common collector amplifiers (generally called emitter followers) with a constant voltage. Acts as a source. Also, resistors 13 and 14 serve as collector load resistances of the differentially coupled transistors 3 and 4.
The output taken out from the transistors 1,
Differential transistors 3 and 4 are alternately switched by the carrier wave _S2 , and the emitter potential of the current source 2 is changed to the current source 2.
As a result of flowing the current of No. 5 as the collector current, the fourth
The result is as shown in waveforms c and d in the figure.

As is clear from _FIGS . 3 and 4, the current value I ₀ of the current source 25 and , load resistance 13,
The waveform has a potential corresponding to the voltage drop (I ₀ ×R ₀ ) with respect to the resistance value R ₀ of No. 14, and a voltage drop corresponding to k or m.

Waveform c switched by this carrier wave
and d are applied to the bases of transistors 7 and 8, respectively, and a waveform with a higher potential is output to the emitter depending on the phase of the carrier wave, so that from the terminal 36, as shown in FIG. It is possible to obtain a signal in which the phase of the carrier wave is reversed by 180° between the higher and lower potential of the modulated wave based on the DC potential of . This means that balance modulation has been carried out.

In the above explanation, the case where the modulated signal of _S1 is input has been described, but it is clear that good carrier wave suppression characteristics are also exhibited even when the modulated signal is inputted to zero. This is because when there is no input of the modulation signal of S ₁ , a common DC potential is applied to both transistors 1 and 2, and the carrier wave of S ₂ is As a result, the signal output from the emitters of transistors 7 and 8, which compare the voltage levels, becomes zero.

In the circuit of the present invention, the only factor that worsens the carrier wave suppression characteristic is the difference in DC potential in the circuit up to the transistor that performs level selection, and this DC potential is determined by the base-emitter voltage Vbe of each transistor. The only difference is When integrated with semiconductors, each transistor
The matching accuracy of Vbe is about 1mv, so if the modulation signal input level is, for example, 0.5vpp,
The carrier wave suppression ratio is approximately 48 dB, and it is possible to obtain characteristics without any problems as a balanced modulation circuit. This fact could also be confirmed through experiments. If the input level is further increased, this characteristic will improve proportionally.

Furthermore, although resistive elements are used in the circuit shown in Fig. 3, as is clear from the above explanation, even if there is a mismatch in the voltage drop I ₀ R ₀ due to each resistor, this circuit Of the carrier waves used for switching, only the phase component having a high potential (portion with no voltage drop) is taken out, so there is no problem with carrier wave suppression.

In this way, according to the circuit shown in FIG. 3, a signal whose carrier wave is sufficiently suppressed can be obtained.

In the above embodiments, it has been explained that the circuit according to the present invention is used in a balanced modulator, but the circuit configuration of the present invention can also be used in a phase detection circuit. In this case, it is sufficient to change the amplitude modulated signal to the signal source _S1 and the AC signal for detection to the signal source _S2 .

As described above, according to the present invention, it is possible to construct a modulation circuit that is not affected by resistance mismatch and has good carrier wave suppression characteristics, and also eliminates the need for an external adjustment circuit and uses inductance and capacitance. This makes it suitable for semiconductor integrated circuits.

[Brief explanation of the drawing]

1 and 2 are circuit diagrams of a conventional signal processing device, FIG. 3 is a circuit diagram of a signal processing device according to an embodiment of the present invention, and FIG. 4 a, b, c, d, and e.
is a waveform diagram for explaining the operation of the device. 1, 2...transistor, 19...DC power supply,
S ₁ , S ₂ ... Signal source, 3, 4, 5, 6, 7, 8,
9, 10, 11, 12...transistor, 36,
27, 28...output terminal, 13, 14, 15, 1
6...Resistance.

Claims (1)

[Claims] 1. A first AC input signal and a DC voltage are superimposed on the base of the transistor of the first emitter follower circuit, a first constant current source is connected to the emitter of the transistor of the first emitter follower circuit, and a first constant current source is connected to the emitter of the transistor of the first emitter follower circuit. A DC voltage having the same value as the above DC voltage is applied to the base of the transistor in the second emitter follower circuit, and a second constant current source having the same current value as the first constant current source is applied to the emitter of the transistor in the second emitter follower circuit. A first switching circuit and a second switching circuit are connected, and a second AC input signal is printed, and a first switching circuit and a second switching circuit are provided in which conduction and interruption states differ from each other depending on the polarity of the signal, and a transistor of the first emitter follower circuit is provided. The emitter of the transistor of the second emitter follower circuit is connected to the reference potential point via the first resistor and the first switching circuit, and the emitter of the transistor of the second emitter follower circuit is connected to the second resistor and the second switching circuit.
is connected to a reference potential point via a switching circuit, and an output obtained at the connection point between the first switching circuit and the first resistor and an output obtained at the connection point between the second switching circuit and the second resistor. 1. A signal processing device comprising a signal extraction circuit that extracts a signal having a high potential by comparing the output with the output of the signal.