JPH0453047Y2

JPH0453047Y2 -

Info

Publication number: JPH0453047Y2
Application number: JP17251984U
Authority: JP
Priority date: 1984-11-14
Filing date: 1984-11-14
Publication date: 1992-12-14
Also published as: JPS6188322U

Description

【考案の詳細な説明】（考案の技術分野）本考案はモノリシツクIC化に適した乗算回路
において、電源雑音の影響を緩和する構成に関す
るものである。[Detailed Description of the Invention] (Technical Field of the Invention) The present invention relates to a structure for mitigating the influence of power supply noise in a multiplication circuit suitable for monolithic IC implementation.

（従来技術とその問題点）第１図に従来の乗算回路の構成を示す。ここ
で、トランジスタ１と２のエミツタ相互間及びト
ランジスタ３と４のエミツタ相互間がそれぞれ接
続され、前記トランジスタ１と３のコレクタ相互
間及び前記トランジスタ２と４のコレクタ相互間
がそれぞれ接続されて出力ポート□６，□７へのパス
が形成され、前記トランジスタ１と４のベース相
互間及び前記トランジスタ２と３のベース相互間
がそれぞれ接続されて、第１の入力ポート□４，□５
が形成され、前記トランジスタ１，２のエミツタ
とトランジスタ５のコレクタが相互接続され、前
記トランジスタ３，４のエミツタとトランジスタ
６のコレクタが相互接続されて前記トランジスタ
５及びトランジスタ６が差動対を構成しそれらの
エミツタがそれぞれ抵抗器を介して定電流源を構
成するトランジスタ７に接続され、前記差動対ト
ランジスタ５及び６の入力側に第２の入力ポート
□２，□３が形成されている。この乗算回路におい
て、入力ポート□２，□３にＸ、入力ポート□４，□５
に
Ｙの信号を入力したとすると、出力ポート□６また
は□７からはＺ＝XYに相当する信号が取り出され
る。本乗算回路は、変調器，復調器、重み付け回
路等各種の回路に適用することができる。例え
ば、変調器として使う場合には入力ポート□４，□５
から搬送波を入力し、入力ポート□２，□３からベー
スハンド信号を入力して使用する。(Prior art and its problems) FIG. 1 shows the configuration of a conventional multiplier circuit. Here, the emitters of transistors 1 and 2 and the emitters of transistors 3 and 4 are connected, and the collectors of transistors 1 and 3 and the collectors of transistors 2 and 4 are connected, respectively, for output. Paths to ports □6 and □7 are formed, and the bases of the transistors 1 and 4 and the bases of the transistors 2 and 3 are connected, respectively, to the first input ports □4 and □5.
are formed, the emitters of the transistors 1 and 2 and the collector of the transistor 5 are interconnected, and the emitters of the transistors 3 and 4 and the collector of the transistor 6 are interconnected, so that the transistors 5 and 6 form a differential pair. Their emitters are respectively connected to a transistor 7 constituting a constant current source via a resistor, and second input ports □2, □3 are formed on the input side of the differential pair transistors 5 and 6. . In this multiplication circuit, input ports □2, □3 have X, input ports □4, □5
If a Y signal is input to the output port □6 or □7, a signal corresponding to Z=XY is taken out from the output port □6 or □7. This multiplication circuit can be applied to various circuits such as modulators, demodulators, and weighting circuits. For example, when using it as a modulator, input ports □4, □5
A carrier wave is input from , and a base hand signal is input from input ports □2 and □3 for use.

しかし、乗算器の線型性、即ち二つの入力の積
の出力が正しく得られる入力レベルの範囲には限
度があり、この範囲が狭いと入力レベルを大きく
とることが出来ず、電源等の雑音に対しては十分
なＳ／Ｎを保つことが出来ない欠点があつた。こ
れは、特に高精度を要求される多値変調器等に適
用した場合問題となる。乗算器の線型出力は抵抗
２６（あるいは抵抗２７）及び、そこに流れる電
流の積できまる（例えば、P.R.Gray and.R.G.
Meyer，“Analysis and design of analog
integrated circuits”，John Willey ＆Sons，
PP158〜162を参照）。線型出力を増加するには電
流を増加したり、電源電圧を高くしたうえで抵抗
を高くする必要があり、何れも消費電力を増加さ
せるという問題点がある。 However, there is a limit to the linearity of a multiplier, that is, the input level range in which the output of the product of two inputs can be correctly obtained.If this range is narrow, the input level cannot be set high, and noise from the power supply However, there was a drawback that a sufficient S/N ratio could not be maintained. This becomes a problem especially when applied to a multilevel modulator or the like that requires high precision. The linear output of the multiplier is determined by the product of the resistor 26 (or resistor 27) and the current flowing there (for example, PRGray and.RG
Meyer, “Analysis and design of analog
integrated circuits”, John Willey & Sons,
see PP158-162). In order to increase the linear output, it is necessary to increase the current, raise the power supply voltage, and increase the resistance, all of which have the problem of increasing power consumption.

（考案の目的）本考案は、これらの欠点を解決するため、乗算
回路を構成する差動対トランジスタの入力段エミ
ツタフオロアの出力抵抗を分割してその差動対ト
ランジスタに入力するように構成して入力段での
雑音レベルを下げることによつて電源雑音の影響
を受けにくいようにしたモノリシツクIC化乗算
回路を提供するものである。(Purpose of the invention) In order to solve these drawbacks, the present invention is configured so that the output resistance of the input stage emitter follower of the differential pair transistors constituting the multiplier circuit is divided and inputted to the differential pair transistors. The present invention provides a monolithic IC multiplier circuit that is less susceptible to power supply noise by lowering the noise level at the input stage.

（考案の構成と作用）以下本考案を詳細に説明する。(Structure and operation of the idea) The present invention will be explained in detail below.

第２図は本考案の実施例であつて、入力段のエ
ミツタフオロアの出力抵抗２３，４４及び２９，
４５が分割されて差動対トランジスタ５，６に入
力されている他は第１図に示す従来形式の乗算回
路と同様である。入力ポート□２，□３に入力された
信号と□４，□５に入力された信号の積の形の出力が
出力ポート□６，□７から取り出される。変調器とし
て用いる場合には入力ポート□４，□５から搬送波を
入力し、入力ポート□２，□３からベースバンド信号
を入力する。その際、入力段エミツタフオロアの
出力抵抗２３，４４，２９，４５を分割して入力
差動トランジスタ５，６に入力しているため、エ
ミツタフオロアの出力端に生じる雑音レベルを下
げることができる。また、乗算動作を行つている
トランジスタ１，２，３，４，５，６，７および
抵抗２４，２５，２６，２７，２８の部分が第１
図と第２図の部分で同じだとすると、第２図の場
合第１図の場合に比べてより大きな入力信号を入
力ポート□２，□３から入力できる。即ち、第２図に
示す本考案による乗算回路の場合、第１図の乗算
回路に比べてトランジスタ５，６のベース端子に
おける雑音の影響を小さくすることが可能とな
る。 FIG. 2 shows an embodiment of the present invention, in which the output resistors 23, 44 and 29 of the emitter follower in the input stage,
45 is divided and inputted to differential pair transistors 5 and 6, but is similar to the conventional multiplication circuit shown in FIG. An output in the form of a product of the signals input to input ports □2 and □3 and the signals input to □4 and □5 is taken out from output ports □6 and □7. When used as a modulator, carrier waves are input from input ports □4 and □5, and baseband signals are input from input ports □2 and □3. At this time, since the output resistors 23, 44, 29, and 45 of the input stage emitter follower are divided and inputted to the input differential transistors 5 and 6, the noise level generated at the output end of the emitter follower can be reduced. In addition, the transistors 1, 2, 3, 4, 5, 6, 7 and the resistors 24, 25, 26, 27, 28 that perform the multiplication operation are the first
Assuming that the parts in the figure and FIG. 2 are the same, a larger input signal can be inputted from the input ports □2 and □3 in the case of FIG. 2 than in the case of FIG. 1. That is, in the case of the multiplication circuit according to the present invention shown in FIG. 2, it is possible to reduce the influence of noise at the base terminals of the transistors 5 and 6 compared to the multiplication circuit shown in FIG.

なお、抵抗２３，４４の分割比と抵抗２９，４
５の分割比は同一の分割比であり、入力信号のレ
ベルにより適宜選択して設定することができる。 In addition, the division ratio of resistors 23 and 44 and the resistors 29 and 4
The division ratio of 5 is the same division ratio, and can be appropriately selected and set depending on the level of the input signal.

（考案の効果）以上説明したように、本考案による乗算回路
は、入力信号のレベルを高くすることができるた
め、電源雑音の影響を緩和することができる。従
つて、高精度の多値変調器を実現することが可能
である。(Effects of the Invention) As described above, the multiplication circuit according to the invention can increase the level of the input signal, and therefore can alleviate the influence of power supply noise. Therefore, it is possible to realize a highly accurate multilevel modulator.

[Brief explanation of the drawing]

第１図は、従来の乗算回路例を示す回路図、第
２図は本考案の乗算回路例を示す回路図である。 □０，□１……電源電圧印加端子、□２，□３……入
力
ポート、□４，□５……入力ポート、□６，□７……出
力
ポート。 FIG. 1 is a circuit diagram showing an example of a conventional multiplication circuit, and FIG. 2 is a circuit diagram showing an example of a multiplication circuit according to the present invention. □0, □1... Power supply voltage application terminal, □2, □3... Input port, □4, □5... Input port, □6, □7... Output port.

Claims

[Scope of utility model registration request]

The emitters of the first and second transistors are connected to each other, and the emitters of the third and fourth transistors are connected to each other, and the collectors of the first and third transistors are connected to each other, and the emitters of the third and fourth transistors are connected to each other. The collectors are connected to each other to form a path to the output port, and the bases of the first and fourth transistors are connected to each other, and the bases of the second and third transistors are connected to each other.
The bases of the transistors are connected to each other to form a first input port, the emitters of the first and second transistors and the collectors of the fifth transistor are connected to each other, and the third and fourth transistors are connected to each other. and the collector of the sixth transistor are interconnected, the fifth transistor and the sixth transistor constitute a differential pair, and their emitters constitute a constant current source via a resistor, respectively. connected to the transistor of
A second input port is formed on the input side of the fifth and sixth transistors constituting the differential pair, and a multiplication output of the input to the first input port and the input to the second input port is formed. in the multiplication circuit configured to take out from the output port, the output obtained by dividing the output resistance of the emitter follower is applied to inputs to the fifth and sixth transistors forming the differential pair. A monolithic IC multiplication circuit characterized by: