JP2005236971A - Low-noise bias circuit for differential, and differential signal processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a low-noise bias circuit for differential wherein distortion property is ensured simultaneously with obtaining good noise property. <P>SOLUTION: A collector of a transistor Q11 is connected to a voltage supplying point (Vcc) through a resistor R15. A base of the transistor Q11 is connected to a base of a transistor Q1 through resistors R13 and R11 which are connected in series. A connection point of the resistor R11 and the resistor R13 is further connected to the collector of the transistor Q11. At a connection point A, a collector of a transistor Q12 is connected to the voltage supplying point through a resistor R16. A base of the transistor Q12 is connected to a base of a transistor Q2 through resistors R14 and R12 which are connected in series. A connection point of the resistor R12 and the resistor R14 is further connected to the collector of the transistor Q12. By the above configuration, high frequency grounding is performed at the connection point A. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a differential low-noise bias circuit and a differential signal processing apparatus, and more specifically, a differential low-noise bias circuit that supplies a low-noise DC voltage to differential transistors, and a bias thereof The present invention relates to a differential signal processing apparatus using a circuit.

  With the rapid spread of wireless communication devices such as mobile phones, there is an increasing need for miniaturization of functional parts (wireless circuit parts) that process wireless signals. For this reason, in the field of wireless communication equipment, the trend in recent years is to make the wireless circuit part an IC. In order to make this wireless circuit unit into an IC, it is necessary to make an amplifier, an oscillator, etc., which have been conventionally made up of individual components and modules, into an IC.

23 and 24 show a circuit configuration of a general conventional differential signal processing device (differential amplification device) (see Patent Document 1 and Patent Document 2).
First, the conventional differential signal processing device 501 shown in FIG. 23 includes a bias circuit 511 and a differential amplifier circuit 521. The differential low noise bias circuit 511 includes resistors R111 to R114 and an NPN-type bipolar transistor Q111. The differential amplifier circuit 521 includes NPN-type bipolar transistors Q1 to Q4 and a bias circuit b.

  In the differential amplifier circuit 521, a differential signal (IN) is input to the bases of the transistors Q1 and Q2, respectively, and a predetermined bias current is supplied from the bias circuit 511. The emitters of the transistors Q1 and Q2 are both grounded. The emitters of the transistors Q3 and Q4 are connected to the collectors of the transistors Q1 and Q2, respectively. A predetermined potential is supplied to the bases of the transistors Q3 and Q4 by the bias circuit b.

  In the bias circuit 511, the collector of the transistor Q111 is connected to the voltage supply point (Vcc) via the resistor R114. The base of the transistor Q111 is connected to the collector (connection point E) via the resistor R113. The collector (connection point E) of the transistor Q111 is connected to the base of the transistor Q1 of the differential amplifier circuit 521 via the resistor R111 and to the base of the transistor Q2 of the differential amplifier circuit 521 via the resistor R112. . The emitter of the transistor Q111 is grounded.

  A conventional differential signal processing device 502 shown in FIG. 24 includes a bias circuit 512 and a differential amplifier circuit 521. The differential low noise bias circuit 512 includes resistors R111 and R112, NPN bipolar transistors Q111 and Q112, and bypass capacitors C111 and C112. The differential amplifier circuit 521 is as described above.

  The collector of the transistor Q111 is connected to the voltage supply point (Vcc), and the emitter thereof is grounded via the bypass capacitor C1. The collector of the transistor Q112 is connected to the voltage supply point, and the emitter thereof is grounded via the bypass capacitor C2. A predetermined reference voltage (Vref) is commonly supplied to the bases of the transistors Q111 and Q112. The emitter of the transistor Q111 is connected to the base of the transistor Q1 of the differential amplifier circuit 521 via the resistor R111. The emitter of the transistor Q112 is connected to the base of the transistor Q2 of the differential amplifier circuit 521 via the resistor R112.

With this configuration, the conventional differential signal processing devices 501 and 502 amplify the differential signal input to the bases of the transistors Q1 and Q2, and output the amplified signals from the collectors of the transistors Q3 and Q4 (OUT). .
JP 2003-133862 A JP 2003-209446 A

  The bias circuits 511 and 512 used in the above-described conventional differential signal processing apparatuses 501 and 502 are generally suitable for circuits that handle low-frequency signals. Therefore, if the bias circuits 511 and 512 are used as they are in a circuit that handles a high-frequency signal, particularly a wireless circuit that requires low noise, the following problems arise.

  First, in the conventional differential signal processing apparatus 501, the differential signal input to the bases of the transistors Q1 and Q2 is canceled at the connection point E via the resistors R111 and R112. It can be regarded as a high-frequency grounding point. However, if the values of the resistors R111 and R112 are small due to this virtual grounding, there is a problem that noise components easily flow from the connection point E to the bases of the transistors Q1 and Q2, and noise characteristics deteriorate. On the other hand, if the values of the resistors R111 and R112 are large, there is a problem that distortion characteristics due to nonlinearity of input / output signals deteriorate. In addition, since the voltage drop allowed in the resistors R111 and R112 is limited by the voltage at the voltage supply point, the values of the resistors R111 and R112 cannot be increased too much.

  In the conventional differential signal processing apparatus 502, the differential signal input to the base of the transistor Q1 is grounded via the resistor R111 and the capacitor C111, and the differential signal input to the base of the transistor Q2. Is grounded through a resistor R112 and a capacitor C112. Therefore, the emitters (connection point F) of the transistors Q111 and Q112 can be regarded as virtual high-frequency ground points, respectively. For this reason, similarly to the differential signal processing apparatus 501, if the values of the resistors R111 and R112 are small, the noise characteristics deteriorate, and if the values of the resistors R111 and R112 are large, the distortion characteristics deteriorate. Further, since the differential signal processing apparatus 102 includes capacitors C111 and C112 in the configuration, there is a problem that the chip area becomes large when an IC is formed.

  As described above, since the noise characteristic and the distortion characteristic are in a trade-off relationship, the bias circuits 511 and 512 of the conventional differential signal processing devices 501 and 502 cannot be applied to a circuit that simply handles a high-frequency signal. . Therefore, in the field of wireless communication devices, there has been a problem that it is necessary to devise a new low-noise bias circuit that has both noise characteristics and distortion characteristics for high-frequency signals.

  Therefore, an object of the present invention is to reduce the loss due to the resistance of the bias circuit, ensure a distortion characteristic and at the same time obtain a good noise characteristic, and a differential using the bias circuit. A signal processing apparatus is provided.

  The present invention is directed to a differential low noise bias circuit that supplies a low noise bias current to the base or gate of a differential transistor. In order to achieve the above object, the differential low-noise bias circuit of the present invention includes first to fourth resistors, first and second transistors, and a connection between the first resistor and the third resistor. The DC voltage is supplied from the voltage supply point to the point, the connection point between the second resistor and the fourth resistor, the collector or drain of the first transistor, and the collector or drain of the second transistor via the ground element.

  One end of the first resistor is connected to one base or gate of the differential transistor. One end of the second resistor is connected to the other base or gate of the differential transistor. One end of the third resistor is connected to the other end of the first resistor. One end of the fourth resistor is connected to the other end of the second resistor. The base or gate of the first transistor is connected to the other end of the third resistor. The base or gate of the second transistor is connected to the other end of the fourth resistor.

  The ground element typically includes a fifth resistor that connects a connection point between the first resistor and the third resistor, a collector or drain of the first transistor, and a voltage supply point, and a second resistor and a fourth resistor. The connection point and the sixth resistor connecting the collector or drain of the second transistor and the voltage supply point.

  Alternatively, the ground element includes a fifth resistor that connects the collector or drain of the first transistor and the voltage supply point, a sixth resistor that connects the collector or drain of the second transistor and the voltage supply point, and a base or gate. A third transistor connected to the collector or drain of the first transistor and having an emitter or source connected to the connection point of the first resistor and the third resistor; a base or gate connected to the collector or drain of the second transistor; A fourth transistor having an emitter or source connected to a connection point between the second resistor and the fourth resistor; a first capacitor connecting the collector or drain of the first transistor and the emitter or source; and a collector of the second transistor or It is comprised with the 2nd capacitor which connects a drain and an emitter or a source.

  Alternatively, the ground element includes a fifth resistor connecting the collector or drain of the first transistor and the collector or drain of the second transistor and the voltage supply point, and a base or gate connected to the collector or drain of the first transistor and the emitter. Alternatively, the third transistor whose source is connected to the connection point of the first resistor and the third resistor, the base or gate is connected to the collector or drain of the second transistor, and the emitter or source is the second resistor and the fourth resistor. And a fourth transistor connected to the connection point.

  The first to fourth transistors may be either NPN type bipolar transistors or N channel type MOS field effect transistors. In this case, the emitters or sources of the first and second transistors may be directly grounded, grounded via a resistor, or grounded via an inductor.

  The first to fourth transistors may be either PNP type bipolar transistors or P channel type MOS field effect transistors. In this case, the emitters or sources of the first and second transistors are each connected to a voltage supply point, connected to a voltage supply point via a resistor, or connected to a voltage supply point via an inductor. That's fine.

  In particular, in order to maximize the effects of the present invention, it is preferable that the connection from the grounding element to the voltage supply point or the grounding point is made by a single wiring.

  The differential low-noise bias circuit is combined with the following differential signal processing circuit that performs predetermined differential signal processing using a low-noise bias current to form various differential signal processing devices. Can do.

  A transistor having one end of the first resistor connected to the base or gate and a transistor having one end of the second resistor connected to the base or gate, the two transistors having an emitter or a source that is high-frequency grounded; This is a differential signal processing circuit configured to amplify and output a signal that is differentially input to a base or a gate from a collector or a drain.

  Alternatively, a transistor having one end of the first resistor connected to the base or the gate and a transistor having one end of the second resistor connected to the base or the gate, the two transistors having a collector or a drain having a predetermined value This is a differential signal processing circuit configured to output a signal connected to a potential and differentially input to a base or a gate by impedance conversion from an emitter or a source.

  Or a transistor having one end of the first resistor connected to the base or the gate and a transistor having one end of the second resistor connected to the base or the gate. The two transistors have a common connection of the emitter or the source. The first signal is input to the emitter or the source, the second signal is input to the base or the gate, and the first signal and the second signal are mixed and output from the collector or the drain. This is a differential signal processing circuit. Here, a transistor having one end of the first resistor connected to the base or gate and a transistor having one end of the second resistor connected to the base or gate, each having an emitter or a source connected in common, respectively. A differential signal processing circuit configured to input the first signal in opposite phase to the emitters or sources of the two further provided transistors may be used.

  Or a transistor in which one end of the first resistor is connected to the base or gate, a transistor in which one end of the second resistor is connected to the base or gate, and a collector or base of the base or gate of one transistor and the other transistor, or The two transistors are differential signal processing circuits configured to output a differential signal oscillated from the collector or the drain, with the emitter or the source being grounded at a high frequency, and having two capacitors connected to the drain.

  Here, the third transistor having one end of the first resistor connected to the base or gate, the fourth transistor having one end of the second resistor connected to the base or gate, and a predetermined potential connected to the base or gate. A fifth transistor in which the collector or drain of the third transistor is connected to the emitter or source, and a sixth transistor in which a predetermined potential is connected to the base or gate and the collector or drain of the fourth transistor is connected to the emitter or source; In the third and fourth transistors, the emitter or source is grounded at high frequency, and the signals that are differentially input to the bases or gates of the third and fourth transistors, respectively, are the collectors or drains of the fifth and sixth transistors. It may be a differential signal processing circuit that is amplified and output from the signal.

  In this differential signal processing circuit, the collector or drain of the fifth transistor and the base or gate of the third transistor are connected via the first feedback circuit, and the collector or drain of the sixth transistor and the base or gate of the fourth transistor are connected. The gate may be connected via a second feedback circuit. For the first and second feedback circuits, a series circuit of resistors may be used, or a parallel circuit of resistors and capacitors may be used.

  The differential signal processing apparatus of the present invention described above includes a duplexer sharing an antenna at the time of transmission and reception, an oscillator, an amplifier for amplifying a reception signal output from the duplexer, and a reception output amplified by the amplifier. It consists of a receiving circuit composed of a demodulator that demodulates with a signal, an oscillator, a modulator that modulates the transmission signal with the signal of the oscillator, and an amplifier that amplifies the transmission signal output from the modulator and outputs it to the duplexer The present invention can be applied to a wireless circuit device including a transmission circuit. Further, a coupler that extracts a part of the transmission signal output from the amplification unit of the transmission circuit, a level detection circuit that detects the power level of the transmission signal extracted by the coupler, and a power level detected by the level detection circuit In addition, a control circuit that changes current consumption of the amplification unit, demodulation unit, and oscillation unit of the reception circuit may be further provided. Alternatively, the reception signal output from the amplification unit of the reception circuit is input, the level detection circuit that detects the power level of the reception signal, and the amplification unit of the reception circuit, and the demodulation according to the power level detected by the level detection circuit And a control circuit for changing the current consumption of the oscillation unit and the oscillation unit. Alternatively, the reception signal output from the amplification unit of the reception circuit and the reception signal output from the demodulation unit are input, and the level detection circuit that detects and compares the power levels of the two reception signals, and the detection by the level detection circuit A control circuit that changes the current consumption of the amplification unit, the demodulation unit, and the oscillation unit of the reception circuit according to the compared power level difference may be further provided.

  In such a radio circuit device, an amplifier, an oscillator, a modulator, and a demodulator are controlled during signal transmission to increase (or decrease) the transmission power of the transmission circuit and increase (or decrease) the current consumption of the reception circuit. Should be controlled simultaneously. The differential low noise bias circuit of the present invention can also be used in a double circuit.

  With the above configuration, in the differential low noise bias circuit of the present invention, it is possible to reduce the loss due to the resistance in the circuit to achieve low noise and to improve the noise characteristics.

  A feature of the present invention resides in a differential low noise bias circuit that achieves both distortion characteristics and noise characteristics by a unique circuit configuration. This differential low-noise bias circuit can be used in various combinations with conventional or novel differential signal processing circuits. In each of the following embodiments, a differential low noise bias circuit will be described by taking as an example a device combined with a differential signal processing circuit that functions as a differential amplifier, an impedance converter, a mixer, and an oscillator.

(First embodiment)
FIG. 1 is a circuit configuration diagram of a differential signal processing apparatus 1 according to the first embodiment of the present invention. In FIG. 1, the differential signal processing apparatus 1 includes a differential low noise bias circuit 111 and a differential amplifier circuit 121. The differential low noise bias circuit 111 includes resistors R11 to R16 and NPN bipolar transistors Q11 and Q12. The differential amplifier circuit 121 includes NPN-type bipolar transistors Q1 to Q4 and a bias circuit b.

  First, the configuration and operation of the differential low-noise bias circuit 111 will be described. The collector of the transistor Q11 is connected to the voltage supply point (Vcc) via the resistor R15. The base of the transistor Q11 is connected to the base of the transistor Q1 of the differential amplifier circuit 121 via resistors R13 and R11 connected in series. The connection point between the resistor R11 and the resistor R13 is further connected to the collector of the transistor Q11. The emitter of the transistor Q11 is grounded. On the other hand, the collector of the transistor Q12 is connected to the voltage supply point at the connection point A through the resistor R16. Since the connection point A is located on the axis of symmetry of the differential amplifier circuit 121, it functions as a virtual ground (a differential signal ground element). The base of the transistor Q12 is connected to the base of the transistor Q2 of the differential amplifier circuit 121 via resistors R14 and R12 connected in series. The connection point between the resistor R12 and the resistor R14 is further connected to the collector of the transistor Q12. The emitter of the transistor Q12 is grounded.

  Next, the configuration and operation of the differential amplifier circuit 121 will be described. The differential signals (IN) are input differentially to the bases of the transistors Q1 and Q2 (that is, one signal is input in the same phase and the opposite phase), and from the differential low noise bias circuit 111. A predetermined bias current is supplied. The emitters of the transistors Q1 and Q2 are commonly connected and grounded. Since the emitter is virtually grounded by this common connection, the transistors Q1 and Q2 operate as a grounded-emitter amplifier. The emitters of the transistors Q3 and Q4 are connected to the collectors of the transistors Q1 and Q2, respectively, and the signals output from the collectors of the transistors Q1 and Q2 are input to the emitters of the transistors Q3 and Q4. The bases of the transistors Q3 and Q4 are connected in common, and a predetermined bias current is supplied from the bias circuit b. Since the base becomes a virtual ground due to this common connection, the transistors Q3 and Q4 operate as a base-grounded amplifier. The amplified signal (OUT) is output from the collectors of the transistors Q3 and Q4.

  A first feature of the differential low-noise bias circuit 111 is that a bias unit that supplies a bias current to the base of the transistor Q1 and a bias unit that supplies a bias current to the base of the transistor Q2 are individually configured. is there. Further, the second feature is that the voltage supply to the resistors R15 and R16 is performed through the only connection point A, and the wiring from the voltage supply point to the resistor R15 and the wiring from the resistor R16 are made common. . For example, in the implementation of an IC, the voltage supply line to the connection point A are routed by a single wire, branched from the connection point A, and wired to the resistors R15 and R16 at a shortest distance. By wiring in this way, the effect of the second feature can be maximized.

  As described above, in the differential signal processing device 1 according to the first embodiment having the above-described configuration, the connection point A is a virtual high-frequency grounding point at which the differential signal input to the bases of the transistors Q1 and Q2 is canceled. (Hereinafter referred to as a virtual ground point). Therefore, the resistance value between the virtual ground point (connection point A) and the base of the transistor Q1 is increased by the resistance R15, and the resistance value between the virtual ground point and the base of the transistor Q2 is the resistance value. Increased by R16. Therefore, according to the differential signal processing apparatus 1 according to the first embodiment, with respect to the distortion characteristics, the values of the resistors R11 and R12 can be reduced to ensure desired characteristics, and the resistance R15 with respect to the noise characteristics. Since the resistance value is increased by R16 and R16, the characteristics are improved as compared with the prior art. Further, by sharing the wiring from the voltage supply point to the resistor R15 and the resistor R16, it is possible to omit a capacitor for bypassing the AC component that is necessary when the wiring is not shared.

(Second Embodiment)
FIG. 2 is a circuit configuration diagram of the differential signal processing device 2 according to the second embodiment of the present invention. In FIG. 2, the differential signal processing device 2 includes a differential low-noise bias circuit 112 and a differential amplifier circuit 121. The differential low noise bias circuit 112 includes resistors R11 to R16, NPN-type bipolar transistors Q11 and Q12, N-channel MOS field effect transistors Q13 and Q14, and bypass capacitors C11 and C12. The differential amplifier circuit 121 is as described in the first embodiment.

  The configuration and operation of the differential low noise bias circuit 112 will be described. The collector of the transistor Q11 is connected to the voltage supply point (Vcc) via the resistor R15. The collector of the transistor Q11 is grounded by the bypass capacitor C11. The emitter of the transistor Q11 is grounded. The base of the transistor Q11 is connected to the base of the transistor Q1 of the differential amplifier circuit 121 via resistors R13 and R11 connected in series. The connection point between the resistor R11 and the resistor R13 is connected to the source of the transistor Q13. The gate of the transistor Q13 is connected to the collector of the transistor Q11. The drain of the transistor Q13 is connected to the voltage supply point, and the substrate is grounded. On the other hand, the collector of the transistor Q12 is connected to the voltage supply point at the connection point B via the resistor R16. The collector of the transistor Q12 is grounded by the bypass capacitor C12. The emitter of the transistor Q12 is grounded. The base of the transistor Q12 is connected to the base of the transistor Q2 of the differential amplifier circuit 121 via resistors R14 and R12 connected in series. The connection point between the resistor R12 and the resistor R14 is connected to the source of the transistor Q14. The gate of the transistor Q14 is connected to the collector of the transistor Q12. The drain of the transistor Q14 is connected to the voltage supply point, and the substrate is grounded.

  The first feature of the differential low noise bias circuit 112 is that a bias unit for supplying a bias current to the base of the transistor Q1 and a bias unit for supplying a bias current to the base of the transistor Q2 are individually configured. is there. The second feature is that the voltage supply to the resistor R15 and the resistor R16 is performed through the only connection point B, and the wiring from the voltage supply point to the resistor R15 and the wiring from the resistor R16 are made common. . Further, the third feature is that transistors Q13 and R13 are connected between the connection point of the resistors R11 and R13 and the collector of the transistor Q11, and between the connection point of the resistors R12 and R14 and the collector of the transistor Q12, respectively. This is because Q14 is inserted.

  Thus, in the differential signal processing apparatus 2 according to the second embodiment having the above-described configuration, the connection point B can be regarded as a virtual ground point where the differential signals input to the bases of the transistors Q1 and Q2 are canceled. Therefore, the resistance value between the virtual ground point (connection point B) and the base of the transistor Q1 is increased by the resistance R15, and the resistance value between the virtual ground point and the base of the transistor Q2 is the resistance value. Increased by R16. Furthermore, since the transistors Q13 and Q14 are inserted, the impedance is increased accordingly. Therefore, according to the differential signal processing apparatus 2 according to the second embodiment, it is possible to further improve the noise characteristics as compared with the first embodiment. In addition, since the collectors of the transistors Q11 and Q12 are high-frequency grounded by the pass capacitors C11 and C12, it is possible to prevent noise generated in the transistors Q11 and Q12 from being input to the bases of the transistors Q1 and Q2.

(Third embodiment)
FIG. 3 is a circuit configuration diagram of the differential signal processing device 3 according to the third embodiment of the present invention. In FIG. 3, the differential signal processing device 3 includes a differential low noise bias circuit 113 and a differential amplifier circuit 121. The differential low noise bias circuit 113 includes resistors R11 to R15, NPN bipolar transistors Q11 and Q12, and N channel MOS field effect transistors Q13 and Q14. The differential amplifier circuit 121 is as described in the first embodiment.

  The configuration and operation of the differential low noise bias circuit 113 will be described. The collector (connection point C) of the transistor Q11 is connected to the voltage supply point (Vcc) via the resistor R15. The emitter of the transistor Q11 is grounded. The base of the transistor Q11 is connected to the base of the transistor Q1 of the differential amplifier circuit 121 via resistors R13 and R11 connected in series. The connection point between the resistor R11 and the resistor R13 is connected to the source of the transistor Q13. The gate of the transistor Q13 is connected to the collector (connection point C) of the transistor Q11. The drain of the transistor Q13 is connected to the voltage supply point, and the substrate is grounded. On the other hand, the collector of the transistor Q12 is connected to the collector (connection point C) of the transistor Q11. The emitter of the transistor Q12 is grounded. The base of the transistor Q12 is connected to the base of the transistor Q2 of the differential amplifier circuit 121 via resistors R14 and R12 connected in series. The connection point between the resistor R12 and the resistor R14 is connected to the source of the transistor Q14. The gate of the transistor Q14 is connected to the collector (connection point C) of the transistor Q12. The drain of the transistor Q14 is connected to the voltage supply point, and the substrate is grounded.

  The first feature of the differential low noise bias circuit 113 is that a bias unit that supplies a bias current to the base of the transistor Q1 and a bias unit that supplies a bias current to the base of the transistor Q2 are individually configured. is there. The second feature is that transistors Q13 and R13 are connected between the connection point of the resistors R11 and R13 and the collector of the transistor Q11, and between the connection point of the resistors R12 and R14 and the collector of the transistor Q12, respectively. This is because Q14 is inserted. Furthermore, the third feature is that the collector of the transistor Q11 and the collector of the transistor Q12 are connected in order to eliminate the bypass capacitors C11 and C12.

Thus, in the differential signal processing device 3 according to the third embodiment having the above-described configuration, the connection point C can be regarded as a virtual ground point where the differential signals input to the bases of the transistors Q1 and Q2 are canceled. Therefore, the resistance value between the virtual ground point (connection point C) and the base of the transistor Q1 is increased by the impedance of the inserted transistor Q13, and the resistance between the virtual ground point and the base of the transistor Q2 is increased. The value is increased by the impedance of the inserted transistor Q14. Therefore, according to the differential signal processing device 3 according to the third embodiment, it is possible to further improve the noise characteristics as in the first embodiment. In addition, since a bypass capacitor for grounding the collectors of the transistors Q11 and Q12 can be omitted, the number of components and the chip occupation area can be reduced when an IC is formed.
The differential signal processing device 3 according to the third embodiment is connected by connecting a matching circuit matched at the fundamental frequency to the input and connecting a matching circuit matched at the second harmonic frequency to the output. It may be used as a double circuit.

(Circuit configuration change example related to the first to third embodiments)
In the first to third embodiments, the case where the differential low-noise bias circuits 111 to 113 are combined with the differential amplifier circuit 121 has been described. However, the differential amplifier circuit 121 is only an example of a differential amplifier circuit, and the differential low-noise bias circuits 111 to 113 are respectively connected to the differential amplifier circuits 122 to 124 shown in FIGS. The same effect can be obtained. 4 to 6 illustrate, as an example, a configuration to which a circuit based on the differential low-noise bias circuit 113 is applied.

FIG. 4 shows a differential signal using a differential amplifier circuit 122 configured so that the emitters of the transistors Q1 and Q2 are grounded via resistors R1 and R2 in order to reduce current variations due to transistor variations. 3 is a circuit example of a processing device 4; In order to match the variation characteristics, it is preferable that the emitters of the transistors Q11 and Q12 of the differential low-noise bias circuit 114 are also grounded via resistors R17 and R18 as shown in FIG. .
FIG. 5 uses a differential amplifier circuit 123 configured such that the emitters of the transistors Q1 and Q2 are grounded via the inductors L1 and L2 in order to further improve the distortion characteristics of the differential signal processing device. 3 is a circuit example of a differential signal processing device 5.
6 uses a differential amplifier circuit 124 configured to connect the collectors of the transistors Q1 and Q2 to the voltage supply point (Vcc) via resistors R3 and R4, respectively, and output a signal from the collector. 3 is a circuit example of a differential signal processing device 6; In the circuit of the differential signal processing device 6, a wide-band amplifier can be realized because the load is a resistance.

(Fourth embodiment)
In the above embodiment, the differential signal processing apparatus in the case where the differential signal processing circuit is a differential amplifier has been described. Next, in the following embodiment, a differential signal processing apparatus when the differential signal processing circuit is other than a differential amplifier will be described.

  FIG. 7 is a circuit configuration diagram of the differential signal processing device 7 according to the fourth embodiment of the present invention. In FIG. 7, the differential signal processing device 7 includes a differential low noise bias circuit 114 and an impedance conversion circuit 125. The differential low noise bias circuit 114 is as described in the circuit configuration modification example of the third embodiment. The impedance conversion circuit 125 includes NPN bipolar transistors Q1 and Q2 and resistors R1 and R2.

  The configuration and operation of the impedance conversion circuit 125 will be described. The differential signals (IN) are input to the bases of the transistors Q1 and Q2, respectively, and a predetermined bias current is supplied from the differential low-noise bias circuit 114. The collectors of the transistors Q1 and Q2 are connected to a voltage supply point (Vcc). The emitter of the transistor Q1 is grounded through the resistor R1. The emitter of the transistor Q2 is grounded through the resistor R2. That is, this configuration forms an emitter follower circuit. The differential signal input to the bases of the transistors Q1 and Q2 is output from the emitters of the transistors Q1 and Q2 (OUT).

  Thus, the differential signal processing device 7 according to the fourth embodiment having the above-described configuration is the same as the differential signal processing device 3 according to the third embodiment and the differential signal processing device 4 of the circuit configuration modification example. The effect of can be obtained.

(Fifth embodiment)
FIG. 8 is a circuit configuration diagram of the differential signal processing device 8 according to the fifth embodiment of the present invention. In FIG. 8, the differential signal processing device 8 includes a differential low noise bias circuit 113 and a mixer circuit 126. The differential low noise bias circuit 113 is as described in the third embodiment. The mixer circuit 126 includes NPN-type bipolar transistors Q1, Q2, Q5, and Q6, and inductors L1 and L2.

  The configuration and operation of the mixer circuit 126 will be described. The bases of the transistors Q1 and Q6 and the bases of the transistors Q2 and Q5 are connected in common, respectively. Local differential signals (LO) are input to the bases of the transistors Q1, Q2, Q5, and Q6, respectively, and a predetermined bias current is supplied from the differential low-noise bias circuit 113. The emitters of the transistors Q1 and Q2 are connected in common and are grounded via the inductor L1. The emitters of the transistors Q5 and Q6 are connected in common and are grounded via the inductor L2. An input differential signal (IN) is input to the common connection point of the emitters of the transistors Q1 and Q2 and the common connection point of the emitters of the transistors Q5 and Q6, respectively. The collectors of the transistors Q1 and Q5 and the collectors of the transistors Q2 and Q6 are connected in common, respectively. With this configuration, a double balance mixer circuit is formed. The input differential signal and the local differential signal are mixed by the transistors Q1, Q2, Q5, and Q6, and the added or subtracted signals are output from the collectors of the transistors Q1 and Q5 and the collectors of the transistors Q2 and Q6, respectively. (OUT).

  Thus, the differential signal processing apparatus 8 according to the fifth embodiment having the above-described configuration can obtain the same effects as those of the differential signal processing apparatus 3 according to the third embodiment. Needless to say, a single balance mixer circuit is formed by only the pair of transistors Q1 and Q2 or the pair of transistors Q5 and Q6 of the mixer circuit 126. In this case, one of the input differential signals and the local differential signal are mixed and output from the collector.

(Sixth embodiment)
FIG. 9 is a circuit configuration diagram of the differential signal processing device 9 according to the sixth embodiment of the present invention. In FIG. 9, the differential signal processing device 9 includes a differential low noise bias circuit 113 and an oscillation circuit 127. The differential low noise bias circuit 113 is as described in the third embodiment. The oscillation circuit 127 includes NPN-type bipolar transistors Q1 and Q2, inductors L3 and L4, and capacitors C1 to C4.

  The configuration and operation of the oscillation circuit 127 will be described. A predetermined bias current is supplied from the differential low-noise bias circuit 113 to the bases of the transistors Q1 and Q2. The collectors of the transistors Q1 and Q2 are connected to a voltage supply point (Vcc) via inductors L3 and L4, respectively. The emitters of the transistors Q1 are commonly connected and grounded. A DC cut capacitor C1 is inserted between the base of the transistor Q1 and the collector of the transistor Q2. A DC cut capacitor C2 is inserted between the base of the transistor Q2 and the collector of the transistor Q1. A bias current is supplied from the voltage supply point (VT) to the collector of the transistor Q1 via the DC cut capacitor C3 and to the collector of the transistor Q2 via the DC cut capacitor C4. That is, this configuration forms an LC type voltage controlled oscillation circuit. Since the outputs from the collectors of the transistors Q1 and Q2 are input to the bases of the transistors Q2 and Q1 with positive feedback, oscillation occurs. The oscillation frequency is determined by the resonance frequency of inductors L3 and L4 and capacitors C3 and C4 connected in parallel between the collector of transistor Q1 and the collector of transistor Q2.

  Thus, the differential signal processing device 9 according to the sixth embodiment having the above configuration can obtain the same effects as those of the differential signal processing device 3 according to the third embodiment.

(Seventh embodiment)
In the first to sixth embodiments, the differential low-noise bias circuit of the present invention has been described with a circuit configuration using an NPN bipolar transistor and an N-channel MOS field effect transistor. However, the differential low-noise bias circuit of the present invention can be configured to use a PNP bipolar transistor and a P-channel MOS field effect transistor according to the configuration on the differential signal processing circuit side. It is. Therefore, in the seventh embodiment, a circuit example in which the circuit configuration of the first embodiment is changed to an NPN bipolar transistor will be described as a representative.

  FIG. 10 is a circuit configuration diagram of the differential signal processing apparatus 10 according to the seventh embodiment of the present invention. In FIG. 10, the differential signal processing apparatus 10 includes a differential low noise bias circuit 115 and a differential amplifier circuit 128. The differential low noise bias circuit 115 includes resistors R11 to R16 and PNP-type bipolar transistors Q11 and Q12. The differential amplifier circuit 128 includes PNP-type bipolar transistors Q1 to Q4 and a bias circuit b.

  The configuration and operation of the differential low noise bias circuit 115 will be described. The emitter of the transistor Q11 is connected to the voltage supply point (Vcc). The base of the transistor Q11 is connected to the base of the transistor Q1 of the differential amplifier circuit 128 via resistors R13 and R11 connected in series. The connection point between the resistor R11 and the resistor R13 is connected to the collector of the transistor Q11. The collector of the transistor Q11 is grounded via a resistor R15. On the other hand, the emitter of the transistor Q12 is connected to a voltage supply point. The base of the transistor Q12 is connected to the base of the transistor Q2 of the differential amplifier circuit 128 via resistors R14 and R12 connected in series. The connection point between the resistor R12 and the resistor R14 is connected to the collector of the transistor Q12. The collector of the transistor Q12 is grounded at the connection point D through the resistor R15.

  Next, the configuration and operation of the differential amplifier circuit 128 will be described. The differential signals (IN) are input to the bases of the transistors Q1 and Q2, respectively, and a predetermined bias current is supplied from the differential low noise bias circuit 115. The emitters of the transistors Q1 and Q2 are connected in common and connected to a voltage supply point. The emitters of the transistors Q3 and Q4 are connected to the collectors of the transistors Q1 and Q2, respectively, and the signals output from the collectors of the transistors Q1 and Q2 are input to the emitters of the transistors Q3 and Q4. The bases of the transistors Q3 and Q4 are connected in common, and a predetermined bias current is supplied from the bias circuit b. The amplified signal (OUT) is output from the collectors of the transistors Q3 and Q4.

  Thus, also in the differential signal processing apparatus 10 according to the seventh embodiment having the above-described configuration, the connection point D can be regarded as a virtual ground point where the differential signals input to the bases of the transistors Q1 and Q2 are canceled. Therefore, according to the differential signal processing apparatus 10 according to the seventh embodiment, it is possible to further improve the noise characteristics as in the first embodiment.

  The bipolar transistors Q1 to Q4, Q11, and Q12 included in the differential signal processing devices 1 to 10 according to the first to seventh embodiments may be replaced with MOS field effect transistors. Conversely, the MOS field effect transistors Q13 and Q14 may be replaced with bipolar transistors.

(Eighth embodiment)
FIG. 11 is a circuit configuration diagram of the differential signal processing apparatus 11 according to the eighth embodiment of the present invention. In FIG. 11, the differential signal processing device 11 includes a differential low noise bias circuit 114 and a differential amplifier circuit 129. The differential low noise bias circuit 114 is as described in the third embodiment and the related circuit configuration modification example. The differential amplifier circuit 129 includes NPN-type bipolar transistors Q1 to Q4, resistors R1, R4, R5, and R6, and capacitors C5 and C6.

  The configuration and operation of the differential amplifier circuit 129 will be described. A differential signal (IN) is input differentially to the bases of the transistors Q1 and Q2, and a predetermined bias current is supplied from the differential low-noise bias circuit 114. The emitters of the transistors Q1 and Q2 are grounded via resistors R1 and R2, respectively. The emitters of the transistors Q3 and Q4 are connected to the collectors of the transistors Q1 and Q2, respectively, and the signals output from the collectors of the transistors Q1 and Q2 are input to the emitters of the transistors Q3 and Q4. The bases of the transistors Q3 and Q4 are connected in common, and a predetermined bias current is supplied from the bias circuit b. The amplified signal (OUT) is output from the collectors of the transistors Q3 and Q4.

  On the other hand, the collector of the transistor Q3 is connected to the base of the transistor Q1 via a capacitor C5 and a resistor R5 connected in series. Similarly, the collector of the transistor Q4 is connected to the base of the transistor Q2 via a capacitor C6 and a resistor R6 connected in series. This connection forms a path through which the amplified signal output from the collectors of the transistors Q3 and Q4 is fed back to the bases of the transistors Q1 and Q2, respectively.

  As described above, the differential signal processing apparatus 11 according to the eighth embodiment having the above configuration negatively feeds back the output signal using the differential amplifier circuit that performs inverting amplification and the feedback circuit. This further improves the linearity of the differential amplifier circuit. Therefore, a differential signal processing device having a wider dynamic range (low noise and low distortion) can be realized as compared with the differential signal processing device 3 according to the third embodiment.

(Ninth embodiment)
FIG. 12 is a circuit configuration diagram of the differential signal processing device 12 according to the ninth embodiment of the present invention. In FIG. 12, the differential signal processing device 12 includes a differential low noise bias circuit 113 and a differential amplifier circuit 130. The differential low noise bias circuit 113 is as described in the third embodiment. The differential amplifier circuit 130 includes NPN-type bipolar transistors Q1 to Q4, inductors L1 and L2, resistors R5 and R6, and capacitors C5 to C8.

  The configuration and operation of the differential amplifier circuit 130 will be described. A differential signal (IN) is differentially input to the bases of the transistors Q1 and Q2, and a predetermined bias current is supplied from the differential low-noise bias circuit 113. The emitters of the transistors Q1 and Q2 are grounded via inductors L1 and L2, respectively. The emitters of the transistors Q3 and Q4 are connected to the collectors of the transistors Q1 and Q2, respectively, and the signals output from the collectors of the transistors Q1 and Q2 are input to the emitters of the transistors Q3 and Q4. The bases of the transistors Q3 and Q4 are connected in common, and a predetermined bias current is supplied from the bias circuit b. The amplified signal (OUT) is output from the collectors of the transistors Q3 and Q4.

  On the other hand, the collector of the transistor Q3 is connected to one end of the capacitor C5. The other end of the capacitor C5 is connected to the base of the transistor Q1 through a capacitor C7 and a resistor R5 connected in parallel. Similarly, the collector of the transistor Q4 is connected to one end of the capacitor C6. The other end of the capacitor C6 is connected to the base of the transistor Q2 via a capacitor C8 and a resistor R6 connected in parallel. This connection forms a path through which the amplified signal output from the collectors of the transistors Q3 and Q4 is fed back to the bases of the transistors Q1 and Q2, respectively.

  As described above, the differential signal processing apparatus 12 according to the ninth embodiment having the above configuration negatively feeds back an output signal by using the differential amplifier circuit that performs inverting amplification and the feedback circuit. In addition, the phase difference from 180 degrees between the input and output signals caused by using the inductor in the differential amplifier circuit is improved by rotating the phase of the output signal and negatively feeding it back to the input. Therefore, the linearity of the differential amplifier circuit is further improved by the interaction between the inductor and the negative feedback as compared with the differential signal processing apparatus 11 according to the eighth embodiment.

(Tenth embodiment)
In the above embodiment, the differential signal processing device having various functions has been described. In the following embodiments, a wireless circuit device using these differential signal processing circuits will be described.

  FIG. 13 is a circuit configuration diagram of the wireless circuit device 13 according to the tenth embodiment of the present invention. In FIG. 13, a radio circuit device 13 includes an antenna 201, a duplexer 202, a low noise amplifier 203, a filter 204, a demodulator 205, a modulator 206, a power amplifier 207, oscillators 208 and 209, Local signal amplifiers 210 and 211. The low noise amplifier 203, the filter 204, the demodulator 205, the oscillator 209, and the local signal amplifier 211 form a receiving circuit. Modulator 206, power amplifier 207, oscillator 208, and local signal amplifier 210 form a transmission circuit. The duplexer 202 is used to share the transmission circuit and the reception circuit with one antenna 201. The demodulator 205 operates as a downmixer. Modulator 206 operates as an upmixer.

  In the above configuration, any of the differential signal processing apparatuses described in the first to third, eighth, and ninth embodiments is applied to the low noise amplifier 203, the power amplifier 207, and the local signal amplifiers 210 and 211. Further, the differential signal processing apparatus described in the fifth embodiment is applied to the demodulator 205 and the modulator 206. Further, the differential signal processing device described in the sixth embodiment is applied to the oscillators 208 and 209.

In the receiving circuit, a signal received by the antenna 201 is input to the low noise amplifier 203 via the duplexer 202. The output signal after being amplified by the low noise amplifier 203 is input to the demodulator 205 via the filter 204. The demodulator 205 demodulates the signal input from the low noise amplifier 203 using the local signal generated by the oscillator 209 and amplified by the local signal amplifier 211. The signal demodulated by the demodulator 205 is output as a BB signal to a BB circuit (not shown).
In the transmission circuit, the BB signal output from the BB circuit is input to the modulator 206. The modulator 206 modulates the signal input from the BB circuit using the local signal generated by the oscillator 208 and amplified by the local signal amplifier 2190. The signal modulated by the modulator 206 is amplified by the power amplifier 207 and then transmitted from the antenna 201 via the duplexer 202.

  As in the tenth embodiment, by applying the differential signal processing device according to the first to ninth embodiments to the configuration of the wireless circuit device 13, a wide dynamic range (low noise and low distortion) can be obtained. ) A wireless circuit device can be realized.

(Eleventh embodiment)
FIG. 14 is a circuit configuration diagram of the radio circuit device 14 according to the eleventh embodiment of the present invention. In FIG. 14, a radio circuit device 14 includes an antenna 201, a duplexer 202, a low noise amplifier 203, a filter 204, a demodulator 205, a modulator 206, a power amplifier 207, oscillators 208 and 209, Local signal amplifiers 210 and 211 and a control circuit 212 are provided.

  As can be seen from FIG. 14, the radio circuit device 14 according to the eleventh embodiment uses a control circuit 212, and a low noise amplifier 203, a demodulator 205, a modulator 206, a power amplifier 207, oscillators 208 and 209, local Controlling the signal amplifiers 210 and 211 is different from the radio circuit device 13 according to the tenth embodiment.

  The control by the control circuit 212 is performed as follows. In the radio circuit device for simultaneous transmission and reception, part of transmission power at the time of transmission leaks to the reception circuit side, resulting in reception interference. Therefore, the dynamic range of the receiving circuit is most necessary when the transmission power is large. Therefore, in the radio circuit device 14, the control circuit 212 changes the currents of the low noise amplifier 203, the demodulator 205, the modulator 206, the power amplifier 207, the oscillators 208 and 209, and the local signal amplifiers 210 and 211. . Specifically, when the transmission circuit current is increased to increase the transmission power, the current consumption of the reception circuit is increased. Conversely, when the transmission circuit current is decreased to decrease the transmission power, the current consumption of the reception circuit is decreased. FIG. 15 shows a configuration example of the differential low-noise bias circuit 116 capable of switching current.

  As in the eleventh embodiment, by applying the differential signal processing device according to the first to ninth embodiments to the configuration of the wireless circuit device 14, the dynamic range in which the influence of transmission power leakage is reduced. A wide (low noise and low distortion) wireless circuit device can be realized.

(Twelfth embodiment)
FIG. 16 is a circuit configuration diagram of a radio circuit device 16 according to the twelfth embodiment of the present invention. In FIG. 16, the radio circuit device 16 includes an antenna 201, a duplexer 202, a low noise amplifier 203, a filter 204, a demodulator 205, a modulator 206, a power amplifier 207, a coupler 213, and an oscillator 208. 209, local signal amplifiers 210 and 211, a level detection circuit 214, and a control circuit 215.

  As can be seen from FIG. 16, the radio circuit device 16 according to the twelfth embodiment is based on the transmission power value detected by the coupler 213 and the level detection circuit 214, on the reception circuit side (low noise amplifier 203, The control of the demodulator 205, the oscillator 209, and the local signal amplifier 211) is dynamically different from the radio circuit device 14 according to the eleventh embodiment.

  The control by the coupler 213, the level detection circuit 214, and the control circuit 215 is performed as follows. A part of the transmission power output from the power amplifier 207 is extracted by the coupler 213 and input to the level detection circuit 214. The level detection circuit 214 detects the level of the extracted transmission power and notifies the control circuit 215 of it. The control circuit 215 controls increase / decrease in current values of the low noise amplifier 203, demodulator 205, oscillator 209, and local signal amplifier 211 constituting the receiving circuit according to the detection result of the level detection circuit 214. FIG. 17 shows a configuration example of the level detection circuit 214.

As in the twelfth embodiment, by applying the differential signal processing device according to the first to ninth embodiments to the configuration of the wireless circuit device 16, the influence of the transmission power leakage is measured by measuring the transmission power. A wireless circuit device with a reduced dynamic range (low noise and low distortion) can be realized.
Note that a method of extracting a part of transmission power output from the power amplifier 207 is not limited to the method using the coupler 213 described above. For example, the transmission power output from the power amplifier 207 may be simply distributed at a ratio that does not affect transmission.

(13th Embodiment)
FIG. 18 is a circuit configuration diagram of a radio circuit device 18 according to the thirteenth embodiment of the present invention. In FIG. 18, a radio circuit device 18 includes an antenna 201, a duplexer 202, a low noise amplifier 203, a filter 204, a demodulator 205, a modulator 206, a power amplifier 207, oscillators 208 and 209, Local signal amplifiers 210 and 211, a level detection circuit 216, and a control circuit 215 are provided.

  As can be seen from FIG. 18, the radio circuit device 18 according to the thirteenth embodiment can dynamically perform control on the receiving circuit side by the control circuit 215 based on the received power level detected by the level detection circuit 216. This is different from the radio circuit device 16 according to the twelfth embodiment.

  The control by the level detection circuit 216 and the control circuit 215 is performed as follows. In the radio circuit device for simultaneous transmission and reception, when the reception power including the interference wave is large, the dynamic range of the reception circuit is most necessary. Therefore, in the wireless circuit device 18, the level detection circuit 216 is connected after the low noise amplifier 203 in order not to deteriorate the noise characteristics. When the reception power increases, the consumption current of the reception circuit increases, and when the reception power decreases, the consumption current decreases. Do to reduce.

  The received signal combined with the desired wave and the interference wave is input to the low noise amplifier 203 and amplified to a predetermined level. The amplified received signal is input to the demodulator 205 and the level detection circuit 216 through the filter 204. The level detection circuit 216 detects the total power level of the disturbing wave before the demodulator 205 and the desired wave and notifies the control circuit 215 of it. The control circuit 215 controls the increase / decrease of the current values of the low noise amplifier 203, the demodulator 205, the oscillator 209, and the local signal amplifier 211 constituting the reception circuit according to the detection result of the level detection circuit 216. FIG. 19 shows a configuration example of the level detection circuit 216.

  As in the thirteenth embodiment, by applying the differential signal processing device according to the first to ninth embodiments to the configuration of the wireless circuit device 18, the influence of the transmission power leakage is measured by actually measuring the received power. A wireless circuit device with a reduced dynamic range (low noise and low distortion) can be realized.

(Fourteenth embodiment)
FIG. 20 is a circuit configuration diagram of the radio circuit device 20 according to the fourteenth embodiment of the present invention. 20, the radio circuit device 20 includes an antenna 201, a duplexer 202, a low noise amplifier 203, filters 204 and 217, a demodulator 205, a modulator 206, a power amplifier 207, and oscillators 208 and 209. And local signal amplifiers 210 and 211, a level detection circuit 218, and a control circuit 215.

  As can be seen from FIG. 20, the radio circuit device 20 according to the fourteenth embodiment dynamically performs control on the receiving circuit side by the control circuit 215 based on the two received power levels detected by the level detection circuit 218. This is different from the radio circuit device 18 according to the thirteenth embodiment. By detecting these two power levels, it is possible to realize control based on the ratio between the disturbing wave and the desired wave, which was impossible with the radio circuit device 18.

  The control by the level detection circuit 218 and the control circuit 215 is performed as follows. The dynamic range of the receiving circuit is most necessary when the interference wave is large and the desired wave is small. Therefore, in the radio circuit device 20, the total power level Ptotal of the desired wave and the interference wave before being input to the demodulator 205 and the power of only the desired wave after passing through the demodulator 205 and the low-pass filter 217. Two levels, Pdesire, are detected. Then, both power levels are compared, and the power consumption of the receiving circuit is increased as the interference wave power level with respect to the desired wave power level increases.

  FIG. 21 is a diagram showing the relationship between the power level of the desired wave and the jamming wave of the input reception signal and the controlled current value. FIG. 21 (a) shows a case where the power level of the desired wave is much higher than the power level of the jamming wave. FIG. 21B shows a case where the power level of the desired wave is slightly higher than the power level of the disturbing wave. In these two cases, since amplification processing is performed based on the power level of the desired wave, the level detection circuit 218 determines the total power level Ptotal output from the filter 204 and the power level Pdesire output from the filter 217. Are detected at substantially the same level (Ptotal≈Pdesire). Therefore, when this level relationship is detected, the control circuit 215 performs control to make the power consumption of the receiving circuit smaller than the standard.

  (C) of FIG. 21 is a case where the power level of a desired wave is a little smaller than the power level of an interference wave. In this case, since the amplification process is performed based on the power level of the interference wave, the total power level Ptotal output from the filter 204 is higher than the power level Pdesire output from the filter 217 in the level detection circuit 218. , Detected at a slightly larger level (Ptotal> Pdesire). Therefore, when this level relationship is detected, the control circuit 215 performs control to standardize the power consumption of the receiving circuit.

  FIG. 21 (d) shows a case where the power level of the desired wave is much smaller than the power level of the jamming wave. In this case, since the amplification process is performed based on the power level of the interference wave, the total power level Ptotal output from the filter 204 is higher than the power level Pdesire output from the filter 217 in the level detection circuit 218. , Detected at a very large level (Ptotal >> Pdesire). Therefore, when this level relationship is detected, the control circuit 215 performs control to increase the power consumption of the receiving circuit from the standard.

  As in the fourteenth embodiment, by applying the differential signal processing apparatus according to the first to ninth embodiments to the configuration of the radio circuit device 20, the ratio of the interference wave and the desired wave of the received signal Thus, a wireless circuit device with a wide dynamic range (low noise and low distortion) in which the influence of transmission power leakage is reduced can be realized.

  The differential low noise bias circuit of the present invention can be used in combination with a differential signal processing circuit such as a differential amplifier, an impedance converter, a mixer, or an oscillator, and in particular, a radio circuit of a radio communication device that handles a high frequency signal. Suitable for use in departments.

1 is a circuit configuration diagram of a differential signal processing apparatus 1 according to a first embodiment of the present invention. The circuit block diagram of the differential signal processing apparatus 2 which concerns on the 2nd Embodiment of this invention. The circuit block diagram of the differential signal processing apparatus 3 which concerns on the 3rd Embodiment of this invention. The circuit block diagram of the other differential signal processing apparatus 4 relevant to 3rd Embodiment The circuit block diagram of the other differential signal processing apparatus 5 relevant to 3rd Embodiment The circuit block diagram of the other differential signal processing apparatus 6 relevant to 3rd Embodiment The circuit block diagram of the differential signal processing apparatus 7 which concerns on the 4th Embodiment of this invention. The circuit block diagram of the differential signal processing apparatus 8 which concerns on the 5th Embodiment of this invention. The circuit block diagram of the differential signal processing apparatus 9 which concerns on the 6th Embodiment of this invention. The circuit block diagram of the differential signal processing apparatus 10 which concerns on the 7th Embodiment of this invention. The circuit block diagram of the differential signal processing apparatus 11 which concerns on the 8th Embodiment of this invention. The circuit block diagram of the differential signal processing apparatus 12 which concerns on the 9th Embodiment of this invention. The circuit block diagram of the radio | wireless circuit apparatus 13 which concerns on the 10th Embodiment of this invention. The circuit block diagram of the radio | wireless circuit apparatus 14 which concerns on the 11th Embodiment of this invention. The circuit block diagram of the differential signal processing apparatus 15 relevant to 11th Embodiment The circuit block diagram of the radio | wireless circuit apparatus 16 which concerns on the 12th Embodiment of this invention. Circuit configuration diagram of level detection circuit 223 of radio circuit device 16 The circuit block diagram of the radio | wireless circuit apparatus 18 which concerns on the 13th Embodiment of this invention. Circuit configuration diagram of level detection circuit 225 of radio circuit device 18 The circuit block diagram of the radio | wireless circuit apparatus 20 which concerns on the 14th Embodiment of this invention. The figure for demonstrating the control which the radio | wireless circuit apparatus 20 performs Circuit configuration diagram of level detection circuit 226 of radio circuit device 20 Circuit diagram of conventional differential signal processing device 501 Circuit diagram of conventional differential signal processing device 502

Explanation of symbols

1 to 12, 15, 501, 502 Differential signal processing devices 13 to 14, 16, 18, 20 Radio circuit devices 111 to 116 Low noise bias circuits for differential 121 to 124, 128 to 130, 521 Differential amplifier circuit 125 Impedance conversion circuit 126 Mixer circuit 127 Oscillator circuit 201 Antenna 202 Duplexer 203, 207, 210, 211 Amplifier 204, 217 Filter 205 Demodulator 206 Modulator 208, 209 Oscillator 212, 215 Control circuit 213 Couplers 214, 216, 218 Level detection Circuits 511, 512, b Bias circuits C1-C8, C11, C12, C111, C112 Capacitors L1-L4 Inductors Q1-Q6, Q11-Q14, Q111, Q112 Transistors R1-R4, R11-R18, R111-R114 Resistors

Claims (45)

A differential low noise bias circuit for supplying a low noise bias current to the base or gate of a differential transistor,
A first resistor having one end connected to one base or gate of the differential transistor;
A second resistor having one end connected to the other base or gate of the differential transistor;
A third resistor having one end connected to the other end of the first resistor;
A fourth resistor having one end connected to the other end of the second resistor;
A first transistor having the other end of the third resistor connected to a base or a gate;
A second transistor having the base or gate connected to the other end of the fourth resistor;
Voltage is supplied to a connection point between the first resistor and the third resistor, a connection point between the second resistor and the fourth resistor, a collector or drain of the first transistor, and a collector or drain of the second transistor. A differential low-noise bias circuit, wherein a DC voltage is supplied from a point via a grounding element. The grounding element is
A connection point between the first resistor and the third resistor, and a fifth resistor connecting the collector or drain of the first transistor and the voltage supply point;
2. A connection point between the second resistor and the fourth resistor, a collector or drain of the second transistor, and a sixth resistor that connects the voltage supply point. The low-noise bias circuit for differential described in 1. The grounding element is
A fifth resistor connecting the collector or drain of the first transistor and the voltage supply point;
A sixth resistor connecting the collector or drain of the second transistor and the voltage supply point;
A third transistor whose base or gate is connected to the collector or drain of the first transistor and whose emitter or source is connected to the connection point of the first resistor and the third resistor;
A fourth transistor whose base or gate is connected to the collector or drain of the second transistor, and whose emitter or source is connected to the connection point of the second resistor and the fourth resistor;
A first capacitor connecting a collector or drain and an emitter or source of the first transistor;
The differential low-noise bias circuit according to claim 1, comprising a second capacitor that connects a collector or drain of the second transistor and an emitter or source. The grounding element is
A fifth resistor connecting the collector or drain of the first transistor and the collector or drain of the second transistor and the voltage supply point;
A third transistor whose base or gate is connected to the collector or drain of the first transistor and whose emitter or source is connected to the connection point of the first resistor and the third resistor;
A base or gate is connected to a collector or drain of the second transistor, and an emitter or source is configured by a fourth transistor connected to a connection point between the second resistor and the fourth resistor. The differential low noise bias circuit according to claim 1, wherein:   2. The differential low-noise bias circuit according to claim 1, wherein the first and second transistors are NPN bipolar transistors or N-channel MOS field effect transistors.   6. The differential low noise bias circuit according to claim 5, wherein emitters or sources of the first and second transistors are grounded.   6. The differential low-noise bias circuit according to claim 5, wherein the emitters or sources of the first and second transistors are grounded via resistors, respectively.   6. The differential low-noise bias circuit according to claim 5, wherein emitters or sources of the first and second transistors are grounded via inductors, respectively.   The differential low-noise bias circuit according to claim 1, wherein the first and second transistors are PNP bipolar transistors or P-channel MOS field effect transistors.   The differential low-noise bias circuit according to claim 9, wherein emitters or sources of the first and second transistors are connected to the voltage supply point, respectively.   10. The differential low-noise bias circuit according to claim 9, wherein emitters or sources of the first and second transistors are connected to the voltage supply point through resistors, respectively.   10. The differential low-noise bias circuit according to claim 9, wherein emitters or sources of the first and second transistors are connected to the voltage supply point through inductors, respectively.   The differential low-noise bias circuit according to claim 1, wherein the connection from the grounding element to the voltage supply point or the grounding point is made by a single wiring. A differential signal processing device including a differential low noise bias circuit that generates a low noise bias current and a differential signal processing circuit that executes predetermined differential signal processing,
The differential low noise bias circuit is:
A first resistor;
A second resistor;
A third resistor having one end connected to the other end of the first resistor;
A fourth resistor having one end connected to the other end of the second resistor;
A first transistor having the other end of the third resistor connected to a base or a gate;
A second transistor having the base or gate connected to the other end of the fourth resistor;
Voltage is supplied to a connection point between the first resistor and the third resistor, a connection point between the second resistor and the fourth resistor, a collector or drain of the first transistor, and a collector or drain of the second transistor. DC voltage is supplied from the point through the grounding element,
The differential signal processing device, wherein the differential signal processing circuit executes predetermined differential signal processing using a bias current supplied from one end of each of the first resistor and the second resistor. The differential signal processing circuit includes:
A third transistor in which one end of the first resistor is connected to the base or the gate and the emitter or the source is high-frequency grounded;
A fourth transistor having one end of the second resistor connected to the base or the gate and the emitter or source grounded at a high frequency,
15. The differential signal processing apparatus according to claim 14, wherein the third and fourth transistors amplify and output from the collector or drain a signal that is differentially input to a base or a gate, respectively. The differential signal processing circuit includes:
A third transistor having one end of the first resistor connected to a base or gate and a collector or drain connected to a predetermined potential;
A fourth transistor having one end of the second resistor connected to the base or the gate and the collector or drain connected to a predetermined potential;
15. The differential signal processing apparatus according to claim 14, wherein the third and fourth transistors output a signal differentially input to a base or a gate by impedance conversion from an emitter or a source, respectively. The differential signal processing circuit includes:
A third transistor having one end of the first resistor connected to a base or a gate;
A fourth transistor having one end of the second resistor connected to a base or gate and an emitter or source connected to the emitter or source of the third transistor;
Each of the third and fourth transistors inputs a first signal to an emitter or a source, inputs a second signal to a base or a gate, and inputs a first signal and a second signal from a collector or a drain. The differential signal processing apparatus according to claim 14, wherein the signal is mixed and output. The differential signal processing circuit includes:
A fifth transistor having one end of the second resistor connected to a base or a gate;
A sixth transistor in which one end of the first resistor is connected to a base or a gate, and an emitter or a source is connected to an emitter or a source of the fifth transistor;
The fifth and sixth transistors input the first signal in reverse phase to the emitter or source, and differentially input the second signal to the base or gate, respectively. The differential signal processing apparatus according to claim 17, wherein the differential signal processing apparatus mixes and outputs the two signals. The differential signal processing circuit includes:
A third transistor in which one end of the first resistor is connected to the base or the gate and the emitter or the source is high-frequency grounded;
A fourth transistor having one end of the second resistor connected to the base or the gate and the emitter or the source grounded at a high frequency;
A first capacitor connecting a base or gate of the third transistor and a collector or drain of the fourth transistor;
A second capacitor connecting the base or gate of the fourth transistor and the collector or drain of the third transistor;
15. The differential signal processing apparatus according to claim 14, wherein the third and fourth transistors have a high-frequency grounded emitter or source, and output a differential signal oscillated from a collector or drain. The grounding element is
A connection point between the first resistor and the third resistor, and a fifth resistor connecting the collector or drain of the first transistor and the voltage supply point;
The connection point between the second resistor and the fourth resistor, and the sixth resistor that connects the collector or drain of the second transistor and the voltage supply point. The differential signal processing device according to 1. The grounding element is
A fifth resistor connecting the collector or drain of the first transistor and the voltage supply point;
A sixth resistor connecting the collector or drain of the second transistor and the voltage supply point;
A fifth transistor having a base or gate connected to the collector or drain of the first transistor and an emitter or source connected to a connection point of the first resistor and the third resistor;
A sixth transistor whose base or gate is connected to the collector or drain of the second transistor, and whose emitter or source is connected to the connection point of the second resistor and the fourth resistor;
A first capacitor connecting a collector or drain and an emitter or source of the first transistor;
The differential signal processing device according to claim 15, comprising a second capacitor that connects a collector or drain of the second transistor and an emitter or source. The grounding element is
A fifth resistor connecting the collector or drain of the first transistor and the collector or drain of the second transistor and the voltage supply point;
A fifth transistor having a base or gate connected to the collector or drain of the first transistor and an emitter or source connected to a connection point of the first resistor and the third resistor;
A base or a gate is connected to a collector or drain of the second transistor, and an emitter or a source is formed of a sixth transistor connected to a connection point between the second resistor and the fourth resistor. The differential signal processing device according to claim 15, characterized in that:   16. The differential signal processing apparatus according to claim 15, wherein the first to fourth transistors are NPN bipolar transistors or N-channel MOS field effect transistors.   24. The differential signal processing apparatus according to claim 23, wherein emitters or sources of the first to fourth transistors are grounded.   24. The differential signal processing apparatus according to claim 23, wherein emitters or sources of the first to fourth transistors are grounded via resistors.   24. The differential signal processing apparatus according to claim 23, wherein emitters or sources of the first to fourth transistors are each grounded via an inductor.   16. The differential signal processing apparatus according to claim 15, wherein the first to fourth transistors are PNP type bipolar transistors or P channel type MOS field effect transistors.   28. The differential signal processing apparatus according to claim 27, wherein emitters or sources of the first to fourth transistors are respectively connected to voltage supply points.   28. The differential signal processing apparatus according to claim 27, wherein emitters or sources of the first to fourth transistors are connected to voltage supply points through resistors, respectively.   28. The differential signal processing apparatus according to claim 27, wherein emitters or sources of the first to fourth transistors are connected to voltage supply points via inductors, respectively.   The differential signal processing apparatus according to claim 15, wherein the connection from the grounding element to the voltage supply point or the grounding point is made by a single wiring. The differential signal processing circuit includes:
A fifth transistor having a base or gate connected to a predetermined potential and an emitter or source connected to the collector or drain of the third transistor;
A sixth transistor in which a predetermined potential is connected to the base or the gate, and the collector or drain of the fourth transistor is connected to the emitter or the source;
16. The signal according to claim 15, wherein a signal differentially input to a base or gate of each of the third and fourth transistors is amplified and output from a collector or drain of the fifth and sixth transistors. Differential signal processing device. The collector or drain of the fifth transistor and the base or gate of the third transistor are connected via a first feedback circuit;
16. The differential signal processing apparatus according to claim 15, wherein a collector or drain of the sixth transistor and a base or gate of the fourth transistor are connected via a second feedback circuit.   The differential signal processing apparatus according to claim 33, wherein a series circuit of resistors is used for the first and second feedback circuits.   The differential signal processing apparatus according to claim 33, wherein a parallel circuit of a resistor and a capacitor is used for the first and second feedback circuits. A duplexer sharing the antenna for transmission and reception;
A first oscillator using the differential signal processing device according to claim 19;
A first amplifier using the differential signal processing device according to claim 15, which amplifies a reception signal output from the duplexer;
The demodulator using the differential signal processing device according to claim 18, which demodulates the reception output amplified by the first amplifier with the signal of the first oscillator;
A second oscillator using the differential signal processing device according to claim 19;
The modulator using the differential signal processing device according to claim 18, which modulates a transmission signal with a signal of the second oscillator;
A radio circuit device comprising: a second amplifier using the differential signal processing device according to claim 15, which amplifies a transmission signal output from the modulator and outputs the amplified signal to the duplexer.   During signal transmission, the second amplifier, the second oscillator, and the modulator are controlled to increase the transmission power of the transmission signal, and at the same time, the first amplifier, the first oscillator, and the demodulator The radio circuit device according to claim 36, further comprising a control circuit that performs control to increase current consumption.   Controlling the second amplifier, the second oscillator, and the modulator other than during signal transmission to reduce the transmission power of the transmission signal, and at the same time, the first amplifier, the first oscillator, and the demodulation 37. The wireless circuit device according to claim 36, further comprising a control circuit that performs control to reduce current consumption of the device. A coupler for extracting a part of the transmission signal output from the second amplifier;
A level detection circuit for detecting the power level of the transmission signal extracted by the coupler;
A control circuit that changes current consumption of the first amplifier, the first oscillator, and the demodulator according to the power level detected by the level detection circuit;
The control circuit controls the current consumption of the first amplifier, the first oscillator, and the demodulator to increase when the power level detected by the level detection circuit increases. The radio circuit device according to claim 36. A coupler for extracting a part of the transmission signal output from the second amplifier;
A level detection circuit for detecting the power level of the transmission signal extracted by the coupler;
A control circuit that changes current consumption of the first amplifier, the first oscillator, and the demodulator according to the power level detected by the level detection circuit;
The control circuit controls the current consumption of the first amplifier, the first oscillator, and the demodulator to decrease when the power level detected by the level detection circuit decreases. The radio circuit device according to claim 36. A level detection circuit for inputting a reception signal output from the first amplifier and detecting a power level of the reception signal;
A control circuit that changes current consumption of the first amplifier, the first oscillator, and the demodulator according to the power level detected by the level detection circuit;
The control circuit controls the current consumption of the first amplifier, the first oscillator, and the demodulator to increase when the power level detected by the level detection circuit increases. The radio circuit device according to claim 36. A level detection circuit for inputting a reception signal output from the first amplifier and detecting a power level of the reception signal;
A control circuit that changes current consumption of the first amplifier, the first oscillator, and the demodulator according to the power level detected by the level detection circuit;
The control circuit controls the current consumption of the first amplifier, the first oscillator, and the demodulator to decrease when the power level detected by the level detection circuit decreases. The radio circuit device according to claim 36. A level detection circuit that inputs a reception signal output from the first amplifier and a reception signal output from the demodulator, and detects and compares the power levels of the two reception signals;
A control circuit that changes current consumption of the first amplifier, the first oscillator, and the demodulator according to a power level difference detected and compared by the level detection circuit;
The control circuit controls the current consumption of the first amplifier, the first oscillator, and the demodulator to be increased when the power level difference detected by the level detection circuit becomes large. The radio circuit device according to claim 36. A level detection circuit that inputs a reception signal output from the first amplifier and a reception signal output from the demodulator, and detects and compares the power levels of the two reception signals;
A control circuit that changes current consumption of the first amplifier, the first oscillator, and the demodulator according to a power level difference detected and compared by the level detection circuit;
The control circuit controls the current consumption of the first amplifier, the first oscillator, and the demodulator to be decreased when the power level difference detected by the level detection circuit is small. The radio circuit device according to claim 36.   A doubler circuit using the differential low-noise bias circuit according to claim 1.

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