JPS62148929A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To hold surely a picture signal inputted to a picture element electrode by forming an electric charge holding capacity with the picture element electrode and a conductive layer which are provided on a transparent insulating substrate. CONSTITUTION:An Si thin film 18 of the first layer which forms the source, the drain, and the channel of a transistor Tr, a wiring layer 26 of the second layer which forms a gate line to be the gate of the Tr, a GND line 27, a data line 25, a liquid crystal driving electrode 31, etc., are formed on a transparent insulating substrate 33. An electric charge holding capacitor is formed in the part where the line 27 and the electrode 31 overlap. Thus, the picture signal inputted to the picture element electrode is held surely, and a video signal is held independently of the change of the time constant of a liquid crystal even if the resistance of the liquid crystal is changed by the change of liquid crystal materials to change the time constant of the liquid crystal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an active matrix substrate for displays using MIS (metal-insulator-semiconductor) transistor arrays.

Disgray tunneling, which uses a conventional active matrix, is attracting attention as a method that allows for a much smaller matrix size than the dynamic method, and is capable of producing large panels with a large number of dots. Particularly in light-receiving devices such as liquid crystals, there is a limit to the driving duty of the dynamic method, and active matrix applications are being considered for television displays and the like. FIG. 1 shows a conventional active multi-IJ rack 1 cell. The address line X is connected to the gate of the transistor 2, and the transistor is turned on to cause the signal on the data line Y to be stored as a charge in the holding capacitor 5. This capacitor 3 holds the data until data is written again, and at the same time drives the liquid crystal 4. Here Va is a common electrode signal. Since the leakage of the liquid crystal is very small, the charge retention Kd for a short time is sufficient.

The manufacturing of the transistor and capacitor 1 here is a normal process C.
The process is exactly the same. FIG. 2 is an example in which the cell shown in FIG. 1 is produced by a silicon gate process. 10 transistors and 1 capacitor on a single crystal silicon wafer
1 is configured. Address line and capacitor upper electrode 1
1 with polycrystalline silicon (polysilicon), and data line Y
and liquid crystal drive electrode 13i1j:Ap, and the substrate and AIL and the polysilicon and M are connected through contact holes 7.8.9, respectively.

Matrix substrates according to this type of conventional IC process have the following major drawbacks.

One is that the manufacturing process for matrix substrates is the same as that for ICs, so the process is complicated and process costs are high, and at the same time, yield decreases due to junction leakage with the substrate silicon.
Total cost is high. In particular, the junction between the silicon substrate and the diffusion layer that becomes the source/drain is affected by crystal defects in the single crystal.
The PA must be placed at the bottom, and it is difficult to suppress leakage from all tens of thousands of cells with this structure. The junction leak generated here discharges the box 1 load accumulated in the condenser 2, reducing the contrast 1.

Second, light incident on the silicon substrate through the gap between the electrodes generates electron-hole pairs and is diffused to generate a photocurrent, which discharges the charge in the capacitor 3, resulting in a decrease in contrast.

The purpose of the present invention is to provide a method for improving this drawback.The structure of the present invention is to construct a thin film transistor using a silicon thin film as a channel on a glass, quartz, or silicon wafer. I'll explain that.

FIG. 3 shows a matrix cell used in the present invention, and the conventional method shown in FIG. 1 is different from the conventional one shown in FIG. The reason is that the wiring is omitted, and the basic data writing and holding are the same. The GND potential in this case means a constant bias voltage, and the bias level or signal level does not matter. In addition, data line Y and GN are used as capacitors for data line Y to sample and hold display data input.
The capacitance 21 between the D lines or the capacitance 22 between the address lines X is used.

An example of the cell structure is shown based on the plan view of the cell in FIG. 4(A) and the sectional view taken along AB in FIG. 4(B). A first layer is formed on the transparent substrate 33 for the source, drain, and channel of the transistor.
The silicon thin film 28 of the first layer and the second silicon thin film or 1l-1 forming the gate line which becomes the gate of the transistor.
: A wiring layer 26 equivalent to that, a GND line 27, a data line 25 made of a transparent low-resistance material, such as a Nesa film such as SnO2, a metal with a thickness of several + ooXly, a liquid crystal drive electrode 31, and an interlayer A contact hole 29 is formed to provide electrical conduction. Also, the overlapping portion of the G and ND lines 27, the liquid crystal, and the single pole of the hyostatic electrode becomes a charge holding capacitor (Fig. 6-18). N+ diffusion (for P channel, p+
), and a channel 3o exists below the gate electrode 38 via a gate insulating film 36, and an insulated film 37 such as an oxide film is further formed around the gate electrode.

FIG. 5 shows a manufacturing process of the active matrix cell shown in FIG. 4. There are basically two types of manufacturing processes: low-temperature processes and high-temperature processes, each with its own characteristics. In low temperature processes, glass or high melting point glass such as Pyrox or Corning is used as a transparent substrate, and
It is a processing process that takes place at temperatures below 0.degree. C., and is characterized by the fact that the substrate itself is inexpensive. In the low-temperature process, a silicon thin film is first deposited on the substrate 33 using an OVA method such as a plasma OVD method or a low pressure CVD method.
It is formed by a method such as a method, sputtering method, etc., and then photoetched into a desired shape. After that, the surface is oxidized in an O, plasma atmosphere. In fact, equivalent insulation may be deposited using the CVD method. As a result, an oxide film 41 which becomes a gate insulating film is formed on the silicon thin film 40. (Figure 5(a)
) After that, a second layer of silicon thin film was deposited in the same manner as the first layer of silicon thin film, and after photo-etching,
Furthermore, the oxide film 41- is etched using the second silicon thin film 45ft mask to form the gate insulating film 41, and at the same time, a diffusion window is opened, and diffusion is performed by ion implantation to form the source, drain 42. 43 is formed. (FIG. 5(b)) After this, plasma treatment is performed again in a zero atmosphere to form a plasma oxide film 46 on the surface.
Annealing is performed at 00°C to 60°C. (Figure 5 (C)
) The feature of this process is that the silicon thin film is directly oxidized by plasma treatment. problems and reliability is improved.

The high-temperature process uses a transparent substrate such as quartz that has a melting point of 60 degrees Celsius or higher, and the manufacturing process involves steps exceeding 600 degrees Celsius.The feature of this process is that it can perform treatments such as high-temperature annealing, which improves the mobility and reliability of the transistor. Can improve sex. Since the structure of the transistor is the same as that of the low-temperature process, it will be explained using FIG. (a) After forming a first layer of thin silicon on the transparent substrate 53 by low pressure or normal pressure CVD method, and patterning it to form the high part 40, the temperature is between 900°C and 1100°C. An oxide film 41 is formed by thermal oxidation. ('b) After that, the 21st silicon layer was deposited in the same manner as the 11th layer, the gate electrode 45 was patterned, and the insulating film 41 was further etched by this amount as a mask. The source/drain 42 is ion-implanted with N+ or P″- impurities without grade deposition or insulation 11Q41i!
．． Form 43e. (C) After that, a thermal oxide film 46, which will become the dielectric film of the holding capacitor, is formed in the same manner as the gate insulating film.

The feature of the configuration example shown in Fig. 4 is that the gate insulating film of the transistor becomes a gate self-line by oxidizing the first silicon thin film or forming it on the silicon thin film, and it becomes a single-crystal bulk silicon element. On the other hand, the deterioration in speed can be prevented by reducing the parasitic capacitance by forming a self-aligned line to compensate for the decrease in mobility and deterioration in speed. The other is a capacitor for charge retention (Figure 6-18).
), data line sample-hold capacitance (Figure 3)
21, 22), an oxide film of a second silicon thin film or an insulating film on the thin film is used as the dielectric film of the capacitor forming the capacitors 21, 22). Conventional bulk silicon type (Figure 2)
In the above, thermal oxidation of bulk silicon was used for the gate insulating film and charge retention capacitor of the transistor, but when doping with impurities is the gate cell alignment method shown in Figure 5 (1')), the capacitance is Since high-concentration impurities do not enter under the second layer of silicon thin film that forms one electrode, it becomes unstable in terms of volume and weight and is difficult to use. An extra step of doping with concentrated impurities is required. Therefore, as shown in FIG. 4, by forming a dielectric film that forms a holding capacitor on the second silicon thin film, it is possible to simplify the process and stabilize the capacitance, which is the purpose of the present invention. becomes.

The steps from FIG. 5(c) onward are almost the same for both low-temperature and high-temperature processes. A contact hole is opened to connect the wiring part with the first and second layers, and a metal ring with a thickness of several 100×μ is made of a material that doubles as the wiring and transparent electrode. Apply by sputtering or evaporation and photoetch. If it is difficult to make direct contact with a silicon thin film such as a Nesa film, a contact material such as Au or Ni-Cr is added to the contact portion.

The transistor formed by the method of the present invention has lower mobility than a transistor formed on bulk silicon, and also has a higher OF F +1-, so it is necessary to take measures to ensure that there are no problems in use.

FIG. 6(A) shows the mobility at 10 V of a transistor formed by a high-temperature process in which the first silicon thin film was formed using a low-pressure OVD apparatus while changing the deposition temperature. It has been experimentally found that the mobility is rapidly improved when the deposition temperature is lower than 600°C. Therefore, in order to improve mobility and ensure response, reduced pressure OV
It is best to form the first layer of silicon thin film at 600°C or lower using D equipment. Figure 7 is a plot of the OFF leakage current at 10V of the transistor by varying the thickness of the silicon thin film in the first eyelet. . Through experiments, the inventor found that with a film thickness of 3700λ or less, the leakage current is 5'00 PA or less, which is acceptable for use.

Mobility decreases significantly not only in high-temperature processes, but especially in low-temperature processes. Another improvement measure for this purpose is to locally anneal the first silicon thin film at a high temperature so that the substrate is not affected by laser or electron beams. FIG. 6(B) shows an additional pulse applied to the silicon thin film formed in the same manner as in (A) as described above.
, which is the mobility of the transistor obtained by illuminating the switch with a laser beam, and it can be seen that it has been further improved. Furthermore, the mobility of a transistor obtained by a low-temperature process obtained by depositing on high-melting point glass at 500°C to 540°C and then laser annealing under the same conditions is as shown in Figure 6 (B). It was almost a match. This shows that local annealing using a laser beam, electron beam, etc. is effective in both low-temperature and high-temperature processes.

FIG. 8 shows another example of cell structure. (A) In the diagram, the address line 50 is the data line 51, the drive electrode, and the gate of the channel 54 of the transistor which serves as the drive electrode and the capacitor's source and drain.Also, the GND line 56 is formed simultaneously with the address line 50 and forms a capacitor between it and the electrode 52.

FIG. 8(B) shows a cross section taken along line AB in FIG. 8(A), and to explain it as a high-temperature process as an example of the manufacturing process, polysilicon is deposited as a silicon thin film on a high melting point glass substrate 57 such as quartz. Grow about 3000X. However, in some cases, a thin 5iO2
(Z may be formed in advance.Furthermore, after forming the gate 50 and capacitor electrode 53 by photoetching, a 5102 film 55 of about 1 soo After applying polysilicon and forming a pattern by photoetching, P ions are implanted into areas other than the channel portion 54 using a resist mask to form a source/drain electrode, a data line wiring portion, and a liquid crystal drive electrode that also serves as a capacitor electrode. Since the performance of the transistor (strain value, conductance) is insufficient as it is, V-zer is irradiated locally on the channel part 54 or uniformly on the entire substrate to weld and solidify the polysilicon in a short time. The performance is improved by increasing the grain length by increasing the grain length.This is called laser annealing.

FIG. 9 shows a cross section of a low-temperature process cell constructed on a normal glass substrate as another example of the present invention. A silicon film is formed on the glass substrate 70 by a low-temperature film formation method such as sputtering or plasma OVD, and P ions or B ions are implanted into the entire surface.

Next, a gate 73 and a capacitor electrode 721fr are formed by photoetching. Furthermore, an insulating film 74 is formed.

This also uses a material such as 5102 grown at low temperature. Historically, the second layer of silicon film, which also serves as the transistor source/drain, capacitor, and drive electrode, is formed at low temperatures. This polysilicon is either completely undoped or has a sufficient amount of B to ensure the threshold value.
Inject ions. Thereafter, a laser beam is applied locally or to the entire area for irradiation with cyanyl lasing. A portion of the laser beam is absorbed by the first silicon layer, but is transmitted through the glass substrate 70. Therefore, the ion-implanted impurities in the first layer of silicon are activated, and the grains of the second layer of polysilicon grow (
In particular, if the channel portion 78) is treated with an appropriate beam energy and an appropriate time (depending on the Arechhals spacing for pulsed lasers, and scanning speed for CW lasers), the glass substrate will be annealed within a range with almost no effect. It is possible. The feature of this method is that the laser annealing has a much smaller effect on the glass substrate than conventional thermal annealing, allowing the use of inexpensive glass.The laser annealing activates impurities and
It is possible to grow the grains of the silicon film in the channel region and improve the characteristics (particularly the mobility) of the transistor at the same time.

Thereafter, An is applied and photoetched to form source and drain electrodes 76 and 77e. Since it is difficult to make contact between M and silicon in this state, it may be necessary to perform some heat treatment or to irradiate the whole with a weak laser beam.

The structure shown in FIG. 8 can of course be realized by a low temperature process. The feature of this structure is that, contrary to Figure 4, the gate of the transistor is a thin film of silicon in the first layer, and the channel is a thin film of silicon in the second layer.
As a result, both silicon thin layers can be arbitrarily diffused at a high concentration to form a gate oxide film obtained by oxidizing the first silicon layer or a gate insulating film on the first silicon layer. A dielectric film that forms a capacitor for charge retention can be used, and the process of forming an oxide film can be performed in one step. Another feature is that as shown in Fig. 4, the wiring material' (i7) can be easily connected to the 00° C.
The ND line and the second layer silicon film become the data line wiring, and the wiring material is deposited for the configuration example shown in Figure 4.
The photo-etching process can be omitted, further simplifying the process. In addition, this method uses silicon @ as one pole of the transparent drive box of the liquid crystal, and the silicon film is sufficiently transparent when it becomes 300 DX or less, so it is highly effective.

FIG. 10 shows a simple cross section of a liquid crystal display device using the MAD1NOX substrate of the present invention. Transparent drive electrode 67
A liquid crystal element 68 is sandwiched between a transparent substrate 65 on which a transparent substrate 65 is placed and a glass 66 on which a common electrode 69 made of glass is placed. Furthermore, polarizing plate 6
2. After sanding with 65, attach a reflector 64 to the lower side. In this case, most of the light incident from above passes through the electrode 67, is reflected by the reflection plate 64, and is sensed by the human eye.

This method is a normal FE twisted nematic (TN)
Because it can use a method type liquid crystal, the contrast is high,
At the same time, the viewing angle is wide. The specific examples shown in FIGS. 4, 8, 9, and 9 use transparent liquid crystal drive electrodes on a transparent substrate,
This is because the conventional bulk silicon type shown in Figure 2 had a serious drawback in that the FE type (TN type) liquid crystal, which has the highest contrast among liquid crystals, could not be used due to the opacity of the substrate. This method has the great advantage of dramatically improving the contrast compared to the bulk silicon type. However, in the structural example of the present invention,
Even if an opaque substrate or opaque drive electrode is used, the G-H tie': f, T) 8M, which is achieved with conventional bulk silicon.
If a type of liquid crystal is used, the contrast will not be improved much, but the purpose of simplifying the process, improving the process yield, and preventing the disappearance of the displayed image due to leakage due to incident light can be achieved.

According to the present invention (using a substrate made of glass, quartz, etc.), it becomes easier to assemble the panel compared to the conventional panel structure in which bulk silicon was used as one side electrode of the liquid crystal. This is a silicon wafer.

Since silicon wafers are single crystals, they easily crack along the cleavage planes due to the pressure during assembly. Also, when a silicon wafer goes through a thermal process, it becomes warped and the liquid crystal 6
8 is 5 .mu.m to 1,511 m, the thickness of the liquid crystal is often 10 .mu.m or more, and it is difficult to assemble the liquid crystal to make the thickness constant throughout.

Also, high temperatures are applied when sealing the liquid crystal, but the upper glass 6
Since the coefficient of thermal expansion is different from 6, the seal will not be completely sealed.

On the other hand, if the substrate of the lower electrode is made of glass, or something close to glass, as in the present invention, all of these problems will be solved, and the assembly can be carried out smoothly and at a high yield, just like a normal liquid crystal panel.

The data storage capacity in the present invention is used to hold the display data of the cell portion for a certain period of time, and is approximately 16 times in the case of a chimp image, for example.

If the leakage current of the L silicon thin film transistor is less than 100 PA at iQV, then the capacitance of this holding capacitor j
d O,5P F to IP'F are required. If the liquid crystal has a high dielectric constant, especially one with a dielectric constant of 10 or more, and the thickness of the liquid crystal is set to 10 μm or less, the capacitance using the liquid crystal as a dielectric becomes more than 0.5 PFμ, and a charge holding capacitor is not required. Then, in Figure 3, the GND line and capacitance 18
can be omitted, the effective liquid crystal driving area can be increased, contrast can be improved, and redundant elements can be eliminated, leading to improved yield. At this time, the sample hold capacitance of the data line Y has a parasitic capacitance of 2 at the intersection of the data line and the address line.
2 is the main one.

Transistors constructed in accordance with the present invention enable external drive circuits for the active matrix, ie shift registers and sample and hold circuits, to all be fabricated on the same substrate.

FIG. 11 shows an example of a drive circuit on the gate line side used in the present invention. Shift register cell 8 consists of transistors 81 to 84 and one bootstrap capacitor 85. There are two phases of clocks φ and φ2, and the '1' potential is sequentially transferred in synchronization with the clock by inputting the start pulse SP.The output of each shift register is ~T.
Jm is input to the gate line, and as a result, the hook gate lines are sequentially selected as shown in FIG. An input quadrature transfer gate transistor 81 is used for the shift register input, and after the data is temporarily stored in TI to TN, "1" is written to D and to Dm using the bootstrap capacitor. If this transfer gater is not used, the disease and T2゜D2 and T3
. . . short-circuited, it is necessary to make the Pootstrap capacitance gradually thicker than the gate line capacitance OGi, the pattern becomes sharper, and the yield is completely reduced. Matari,~T
In order to discharge Jf+1 to "0" after being written to "1", it is only necessary to connect Ts to the transistor 84, but if this shift register operates at a low frequency, it will operate even with a slight leakage. Therefore, in order to improve the yield and stabilize the operation, a potential fixing transistor 83 is added and refreshed to "0" level every half cycle of the clock.

FIG. 13 is an example of a data line side drive circuit according to the present invention. The shift register cell 86 includes a Pootstrap capacitor 88, transistors 89 and 91 necessary for operation, and a reset transistor 90 for shift register selection, which will be described later.
A start pulse sp6 is applied to the first stage via an input gate 87. Also, each shift register output S
, ~E1m are sample and hold transistors H, -Hm
The video input signal V, El is inputted to the video input terminal V, El in synchronization with the scanning signal.

(Video signal or data write signal) is sampled and held in capacitors CD, ~CDm parasitic on the data line. The data line side drive circuit performs all processing within one scanning line, so it is fast and there is no need to take leakage current into consideration.
On the other hand, it is necessary to consider ensuring high-speed operation and suppressing power consumption, which increases due to high speed.

In this shift register, only 1 bit out of m pits is set to 1, so power consumption other than the clock is low.

In addition, the sample-and-hold transistors H1 to Hm are required to have fairly high-speed switching, but because their gate inputs are applied with an amplitude nearly twice that of the clock signal due to the Pootstrap capacitance, as shown in Figure 14, the switching speed is extremely high. It has the advantage of high-speed switching.

FIG. 15 shows the case where these are actually arranged on an active matrix substrate f'C. There are data-side shift registers 90.91, dummy cells 94.95 for forming a final stage feedback signal, and sample-and-hold transistors H, -Hm, arranged vertically symmetrically. Further, the gate side shift registers 92 and 93 and the dummies 96 and 97 are arranged symmetrically. Originally, the peripheral circuits should not be symmetrical on both sides, but only on one side, but in consideration of yield, multiple shift register arrays are prepared.

Of course, it may be 4 columns or 8 columns, but an example of 2 columns is shown here.

By forming the drive circuit shown in FIG. 15 using transistors using silicon thin films as in the present invention, there are the following advantages.Firstly, especially on the data line side, the clock frequency is several MH2.
Since the power consumption is high, the parasitic capacitance of the clock line consumes more power than the internal power consumption of the shift register. In particular, in bulk silicon, the wiring capacitance of the clock line and the junction capacitance with the substrate are 100 PF or more, which reduces the clock speed and results in power consumption of 10 mA or more. However, according to the present invention (on an insulating substrate, this parasitic capacitance is several P'F, so power consumption can be extremely reduced and speed can be improved. Next, in bulk silicon, for example, the transistor 82 in FIG. When the source potential increases, the threshold value increases due to the back gate effect.As a result, in order to obtain the necessary signal voltage, it is necessary to increase the voltage at the gate T of the transistor 82, and as a result, the clock signal level increases. However, in the structure of the present invention, the substrate of the transistor is 70°, so there is no back gate effect, and the clock amplitude can be small, resulting in lower power consumption. Furthermore, the bootstrap capacitance may be small -g<, and can be realized in a small area.Footstrap capacitance in the peripheral drive circuit of the present invention
Use absolute h-t clarity between the gate and the channel. This is because the bootstrap capacitance requires that the inter-electrode capacitance is variable depending on the gate voltage at the upper pole, so the lower capacitance (the capacitance should be made of low-conductivity or non-doped silicon).

In this way, if the active matrix cell part and the peripheral drive part are formed simultaneously on the insulating substrate by dividing the silicon thin film 11t, the wiring connection becomes easier and the overall cost can be reduced. The peripheral drive circuit is shown in Figure 11.

Considering the fact that it is configured with a non-inverting Ray-Yo-Less shift register as shown in Figure 16, and that the parasitic capacitance is much lower, it is possible to reduce the overall consumption power, and at the same time improve yield and reduce costs. It is possible to achieve a reduction in

As described above, the present invention provides an active matrix having silicon transistors and silicon capacitors on a substrate, and has the following advantages over the prior art.

The manufacturing process is simple; the conventional bulk silicon type requires 6 photoetching steps, but the method of the present invention requires only 3 or 4 photoetching steps, resulting in low process costs and P-etching process similar to bulk silicon. Since the cross-sectional area of the N junction is very small, there is little junction leakage, and an improvement in yield can be expected.

Also, 90% of the light incident from above passes through μ, and 1)
Since the diffusion length of C1)A in the thin film is also short, almost no photocurrent is generated, and the leakage value with respect to the original is 1.0 P A 11 even under 10,000 lux. It was possible to prevent the display image from disappearing.

Furthermore, by using the transparent liquid Otsube wJ for the transparent substrate, it is possible to use the FB type liquid crystal with the highest contrast, and the brightness of the screen is also improved, making it possible to dramatically improve the display quality.

At the same time, using glass or a similar material for the substrate makes it easy to assemble the tunnel, which improves the assembly yield and simplifies the process compared to the conventional silk silicon type.

When an active matrix peripheral drive circuit is installed, power consumption can be significantly reduced.

As mentioned above, in the present invention, liquid crystal is sealed within a pair of substrates,
The substrate is a quartz or glass substrate, a first conductive layer provided on the substrate, an insulating film provided on the first conductive layer,
A silicon semiconductor material provided on the insulating film layer, a source and a tunnel diffusion region provided in the silicon semiconductor layer, and a pixel electrode electrically connected to the semiconductor material provided in the insulating layer. However, since the pixel electrode and the first conductive layer form the entire charge storage capacitor, it is possible to reliably hold the image signal input to the pixel electrode, and the resistance of the liquid crystal changes as the liquid crystal material changes. Even if the time constant of the liquid crystal changes, the video signal can be maintained regardless of this change.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of a cell used in a conventional active matrix, Figure 2 is a plan view and cross-sectional view of a bulk silicon type 4 (A), (B) ID implementation example, and Figure 5 (a). (b) (c) is its manufacturing process. Figure 6. FIG. 7 shows the characteristics of a silicon thin film. Figure 8 (A) (
B). FIG. 9 is another implementation example of the present invention, and FIG. 10 is a sectional view when assembled into the active matrix panel of the present invention. FIGS. 11, 16, and 15 show examples of peripheral drive circuits used in the present invention, and FIGS. 12 and 14 show their operating waveforms. 11... Upper electrode 10 of polycondenser of capacitor 6
... Bolin 1 Fucon gate 7.8.9... Contact hole 13... Drive electrode by M 30.40, 51, 53, 72.73... 11th silicon thin film 26.45, 50, 52.75...Second layer silicon thin film 26-3f], 44, 54.78...Channel 33, 57.
70...Substrate 62.63...Polarizing plate 64...Reflecting plate 65.66...Transparent substrate 69...NESA film 67...Polysilicon drive electrode 68...Liquid crystal body 76.77 ...M 36.41.55.74...Gate insulating film 37.46
... Capacitor insulating film 25.31 ... Transparent low resistance material 85.88 ... Footstrap capacitance 89 ... Active matrix 9Q, 91, 92.93 ... Shift register or higher Applicant Seiko Epson stock Company Fig. 5 Fig. 9 Δ2 Fig. 10 'Oni to ): m 1-! 5 t'? to one
Senma ＼ ＼ ＼ l outside 0, rqli cl)
Group 5 Group

Claims (1)

[Claims] A liquid crystal is sealed within a pair of substrates, the substrates being quartz or glass substrates, a first conductive layer provided on the substrates, an insulating film provided on the first conductive layer, and an insulating layer provided on the insulating layer. a silicon semiconductor film, a source and drain diffusion region provided in the silicon semiconductor film, and a pixel electrode provided in the insulating layer and electrically connected to the semiconductor film; A liquid crystal display device characterized in that a charge storage capacitor is formed by a first conductive layer.