JPH09120084A - Production of liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To uniformly grow grains in a silicon layer by annealing a silicon thin film by irradiation with laser beams or the like of the whole substrate. SOLUTION: An oxide film 41 to be formed as a gate insulating film is formed on a silicon thin film 40. Then a second silicon thin film is deposited by the same method as for the first silicon thin film and subjected to photoetching. Further the oxide film 41 is etched by using the second silicon thin film 45 as a mask to form a gate insulating film 41. At the same time, openings for diffusion are formed, and ions are implanted to form a source 42 and a drain 43. Then, a plasma oxide film 46 is formed on the surface and annealed. Thus, the silicon thin film 40 to constitute a thin film transistor is formed on a transparent glass substrate 33 and the whole glass substrate 33 is irradiated with laser beams or electron beams to anneal the silicon thin film 40. Then, the obtd substrates 33 are disposed to face each other to assemble a liquid crystal element.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix substrate for a display using a MIS (metal-insulator-semiconductor) transistor array.

[0002]

2. Description of the Related Art Conventionally, a display panel using an active matrix has attracted attention as a method capable of realizing a large-sized panel having a large number of dots because the matrix size thereof can be made extremely large as compared with the dynamic method.
In particular, a light-receiving element such as a liquid crystal has a limited drive duty in a dynamic system, and application of an active matrix is considered for a television display and the like. FIG. 1 shows one cell of a conventional active matrix. The address line X is input to the gate of the transistor 2, and the transistor is turned on to cause the signal on the data line Y to be stored as charge in the holding capacitor 3. Until data is written again, it is held by the capacitor 3 and simultaneously drives the liquid crystal 4. Here, VC is a common electrode signal. Since the leakage of the liquid crystal is very small, it is enough to hold the charge for a short time.

The manufacture of the transistor and the capacitor 1 here is completely suitable for the process of a normal IC. FIG. 2 shows FIG.
It is an example in which the cell of (1) is created by a silicon gate process. A transistor 10 and a capacitor 11 are formed on a single crystal silicon wafer. The address line X and the upper electrode 11 of the capacitor are made of polycrystalline silicon (polysilicon), and the data line Y and the liquid crystal drive electrode 13Al are formed. The contact holes 7, 8 and 9 allow the substrate and Al, and the polysilicon and Al to be formed. Are connected respectively.

[0004]

The matrix substrate according to the ordinary IC process of this kind has the following drawbacks.

First, since the manufacturing process of the matrix substrate is the same as that of the IC, the process is complicated and the process cost is high, and at the same time, the yield is reduced due to the junction leak with the substrate silicon, and the total cost is high. In particular, the junction between the silicon substrate and the source / drain and a certain diffusion layer is considerably affected by crystal defects in the single crystal, and this leakage current must be 10 OPA or less in a normal cell. It is difficult to suppress the leak of all the cells. The junction leak generated here discharges the charge stored in the capacitor 3 and lowers the contrast.

Secondly, the light incident on the silicon substrate through the gap of the Al electrode generates electron-hole pairs and diffuses to generate a photocurrent, which discharges the electric charge of the capacitor 3 and lowers the contrast.

[0007]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for remedying this drawback. The structure of the present invention comprises a thin film transistor having a silicon thin film as a channel on a glass, quartz or silicon wafer. To do.

In the thin film transistor of the present invention, liquid crystal is enclosed in a pair of substrates, the substrate being a quartz or glass substrate, and a first conductive layer provided on the substrate, and provided on the first conductive layer. Insulating film, a silicon semiconductor film provided on the insulating layer, source and drain diffusion regions provided in the silicon semiconductor film, and a pixel electrode provided on the insulating layer and electrically connected to the semiconductor film And a charge holding capacity is formed by forming a charge holding capacity by the pixel electrode and the first conductive layer.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 shows a matrix cell used in the present invention. In the conventional matrix cell shown in FIG. 1, a GND wiring for the capacitor 18 is newly provided or, as will be described later, the capacitance holding capacitor 18 and the GND wiring. Is omitted, and the basic writing and holding of data is the same. GND in this case
The potential means a constant bias voltage, and the bias level or signal level does not matter. In addition, the data line Y is used as a capacity for sample-holding the input of display data by the data line Y.
And the true capacitance 21 of the GND line or the capacitance 22 between the address line X and the line.

A plan view of the cell of FIG. 4A, A- of FIG.
An example of the cell structure is shown based on the cross-sectional view at B. Transparent substrate 3
3, the first layer of the silicon thin film 28 forming the source / drain / channel of the transistor and the second layer of the silicon thin film forming the gate line to be the gate of the transistor, or any wiring layer 26 and the GND line 27, Further, a transparent low resistance material, for example, a Nesa film such as Sn02, a data line 25 made of a metal having a thickness of 100 Å or less, a liquid crystal drive electrode 31, and a contact hole 29 for establishing conduction between layers are formed. Further, the overlapping portion of the GND line 27 and the liquid crystal driving electrode is a charge holding capacitor (see FIG. 3-1).
8) Source / drain of transistor 34.3
In FIG. 5, N + diffusion (P + in case of P channel) is performed, a channel 30 exists below the gate electrode 38 through a gate insulating film 36, and an insulating film 37 such as an oxide film is further formed around the gate electrode. ing.

FIG. 5 shows a manufacturing process of the active matrix cell shown in FIG. There are basically two types of manufacturing processes, a low temperature process and a high temperature process, and each has its own characteristics. In the low temperature process, glass or a high melting point glass such as Pyrex or Corning is used as a transparent substrate, and it is a process step at 600 ° C. or less, and the substrate itself is inexpensive. In the low temperature process, the substrate 3
A silicon thin film is formed on 3 by a CVA method such as a plasma CVD method or a low pressure CVD method, a sputtering method or the like, and photo-etched into a required shape. Then, the surface is oxidized in a 0 ₂ plasma atmosphere. In practice, a CVD method may be used to deposit an equivalent insulating film. As a result, an oxide film 41 serving as a gate insulating film is formed on the silicon thin film 40. (FIG. 5 (a)) After that, the second-layer silicon thin film is devoted and photo-etched in the same manner as the first-layer silicon thin film, and then the second-layer silicon thin film 45 is used as a mask to form an oxide film 41. Are simultaneously etched to form a gate insulating film 41, a diffusion window is opened at the same time, and diffusion is performed by ion implantation to form source / drain 42/43. (FIG. 5B) Further, after this, plasma treatment is performed again in an O ₂ atmosphere to form a plasma oxide film 46 on the surface, and 4
Annealing is performed at 00 ° C to 600 ° C. (FIG. 5 (c)) The feature of this process is that the silicon thin film is directly oxidized by plasma treatment. As a gate insulating film of a transistor and a derivative film for a capacitor, it moves as compared with the oxide film of the CVD method. The degree is improved and the reliability is improved. The high temperature process uses a transparent substrate having a melting point of 600 ° C. or higher, such as quartz, and the manufacturing process includes steps exceeding 600 ° C. This process is characterized by high temperature annealing and the like, so that the mobility and reliability of the transistor can be improved. Can be improved. Since the structure of the transistor is the same as that in the low temperature process, it will be described again with reference to FIG. (A) First, a first layer of a silicon thin film is formed on the transparent substrate 33 by a reduced pressure or atmospheric pressure CVD method, etc., patterned to form an island portion 40, and then thermally oxidized at 900 ° C. to 1100 ° C. Oxide film 4
Form one. (B) After that, the second layer of silicon thin film is deposited in the same manner as the first layer, the gate electrode 45 is patterned, and the insulating film 41 is etched using this as a mask to pre-deposit N + or P + impurities. Impurities are ion-implanted without etching the position or the insulating film 41 to form the source drains 42 and 43.
(C) Thereafter, a thermal oxide film 46 serving as a dielectric film of the holding capacitor is formed in the same manner as the gate insulating film.

The feature of the configuration example shown in FIG. 4 is that the gate insulating film of the transistor is formed by oxidizing or forming a first silicon thin film on the silicon thin film and performing gate self-alignment using the gate as a mask. Such a silicon thin film has a lower mobility and a lower speed than a single crystal bulk silicon device, but the speed deterioration can be prevented by making the parasitic capacitance self-aligning and reducing the parasitic capacitance.
The other is a second silicon thin film as a dielectric film of a capacitor for holding a charge (Fig. 3-18) and a capacitor for holding a sample and hold of a data line (Figs. 3-21 and 22). It is to use an oxide film or an insulating film on a thin film. In the conventional bulk silicon type (FIG. 2), the gate insulating film and the charge storage capacitor of the transistor are all made of the thermal oxide film of bulk silicon.
In the case of the gate self-alignment method shown in (b), since high-concentration impurities do not enter under the second-layer silicon thin film, which serves as one electrode of the capacitor, the capacitor becomes unstable as it is, and it is difficult to use it. Then, an extra step of doping a high-concentration impurity only in the lower electrode of the capacitor like in the case of parc silicon is required. Therefore, as shown in FIG. 4, by forming the dielectric film for forming the holding capacitor on the second silicon thin film, it is possible to simplify the process and stabilize the capacitor, which is the object of the present invention. Become.

The steps after FIG. 5 (c) are substantially common to both low temperature and high temperature processes. A material that also serves as a wiring and a transparent driving electrode by forming a contact hole for making a contact between the wiring portion and the first layer and the second layer, a negative film, and a thickness of 10
Photo-etch a metal such as 0 Å or less by sputtering or vapor deposition. If it is difficult to directly contact the silicon thin film such as the Nesa film, a contact-specific material such as Au / Ni-Cr is added to the contact portion.

The transistor formed according to the method of the present invention has a lower mobility and a larger amount of OFF leakage than the transistor formed on the bulk silicon, and therefore, a device which does not hinder the use is required.

FIG. 6A shows a first silicon thin film,
It shows the mobility at 10V of a transistor formed by a low pressure CVD apparatus while changing the devolution temperature and formed by a high temperature process. It has been found through experiments that the mobility is sharply improved when the devotion temperature is 600 ° C. or lower. Therefore, in order to improve the mobility and ensure the response, it is preferable to form the first silicon thin film at 600 ° C. or lower by a decompression CVD apparatus.

FIG. 7 shows the OF of the transistor at 10 V.
The F leak current 1L is plotted by changing the film thickness of the silicon thin film of the first layer. The inventor has determined by experiment that
With a film thickness of 700 Å or less, there is no problem in use.
I knew it would be below 0 PA.

Not only in the high temperature process, but especially in the low temperature process, the mobility is drastically reduced. Another improvement means for this may be to locally anneal the silicon thin film of the first layer at a high temperature so as not to affect the substrate by the laser or the electron beam. FIG. 6B shows the mobility of the transistor obtained by further illuminating the silicon thin film formed in the same machine as the above-mentioned (A) with the laser beam by the Q switch having the pulse width Sonsec of 0.12 mJ, It can be seen that it is further improved. Again 500
The mobility of the transistor by the low temperature process obtained by performing laser annealing under the same conditions after depositing on the high melting point glass at 550 to 540 ° C. almost coincided with the curve of FIG. 6B. This indicates that local annealing using a laser beam, an electron beam, or the like is effective in both low-temperature and high-temperature processes. FIG. 8 shows another example of the mechanism of the cell. (A) is a plan view in which an address line 50 is a gate of a channel 54 of a transistor having a data line 51, a drive electrode and a capacitor electrode 52 as a source / drain. Also, the GND line 53 is the address line 5
It is formed at the same time as 0 and forms a capacitance with the electrode 52. FIG. 8B shows a cross section taken along the line AB of FIG. 8A. As an example of the manufacturing process, a high temperature process will be described. Polysilicon is used as a silicon thin film on a high melting point glass substrate 57 such as quartz. Grow 3000Å. However, in some cases, to improve the adhesion, thin SiO
₂ may be preformed. Further, after forming the gate 50 and the capacitor electrode 53 by photo etching, a SiO2 film 55 of about 1500 Å is grown as a gate insulating film and a dielectric film of the capacitor by thermal oxidation. After that, a second layer of polysilicon is attached and a pattern is formed by photoetching, and then P ions are implanted in a region other than the channel portion 54 by a resist mask to form a source / drain electrode, a data line wiring portion, and a liquid crystal driving electrode which also functions as a capacitor electrode. Form. Since the performance of the transistor (squiggly value, conductance) is insufficient as it is, the polysilicon is welded and solidified within a short time by irradiating the laser locally, particularly on the channel 54 or uniformly on the entire substrate. Performance is improved by growing grains. This is what is called laser annealing.

As another example of the present invention, FIG. 9 shows a cross section by a low temperature process in which cells are formed on a normal glass substrate. A silicon film is formed on the glass substrate 70 by a low-temperature film formation method such as a sputtering method or a plasma CVD method, and P ions or B ions are implanted over the entire surface. Next, a gate 73 and a capacitor electrode 72 are formed by photo etching.
Further, an insulating film 74 is formed. Also for this, Si02 or the like, which can grow at low temperature, is used. Further, a second-layer silicon film serving also as a source / drain of the transistor, a capacitor and a drive electrode is formed at a low temperature. This polysilicon is not doped at all, or is implanted with a sufficient amount of B ions to enhance the threshold value. Thereafter, annealing is performed by irradiating a laser beam locally or entirely. Part of the laser beam is absorbed by the first layer of silicon,
The glass substrate 70 is transparent. Therefore, the activation of the ion-implanted impurities in the first layer of silicon and the growth of the grains of the second layer of polysilicon (in particular, the channel portion 78) are carried out at an appropriate beam energy and an appropriate time (with a pulse laser). If so, the annealing can be performed within a range that has almost no effect on the glass substrate by performing processing at a pulse interval and with a CW laser depending on the scanning speed). The feature of this method is that laser annealing can reduce the influence of the conventional thermal annealing on the glass substrate, so that glass with low cost can be used. It is possible at the same time to grow the grain of the film and improve the characteristics of the transistor (in particular the mobility).

After that, Al is applied and photoetching is performed to form source / drain electrodes 76 and 77. Since it is difficult to make contact between Al and silicon as they are, a little heat treatment or a weak laser beam may be applied thereafter.

The structure shown in FIG. 8 can be realized by a low-temperature process. The feature of this structure is that, contrary to FIG. 4, the transistor gate uses the first layer of silicon thin film and the channel uses the second layer of silicon thin film. Concentration diffusion becomes possible, and a gate oxide film obtained by oxidizing the first silicon thin film is used as a gate insulating film on the first silicon film.
A derivative film for forming a capacitor for holding a charge can be used, and a process of forming an oxide film is completed in one process. Another feature is that even if a new wiring material is not provided as shown in FIG.
The first layer of silicon film serves as an address line and a GND line, and the second layer of silicon film serves as a data line wiring. This eliminates the step of depositing a wiring material and photoetching the structure example of FIG. The process is simplified. In this method, a silicon film is used as a transparent drive electrode of liquid crystal, and the effect is great because the silicon film is sufficiently transparent when it is less than 3000 Å.

FIG. 10 shows a simple cross section of a liquid crystal display device using the matrix substrate of the present invention. A liquid crystal 68 is sandwiched between a transparent substrate 65 on which a transparent driving electrode 67 is mounted and a glass 66 on which a common electrode 69 made of a Nesa film is mounted. Furthermore, after polarizing with the polarizing plates 62 and 63, the reflector 6 is placed on the lower side.
Turn on 4. In this way, most of the light incident from above passes through the electrode 67, is reflected by the reflector 64, and is sensed by the human eye. Since this system can use a normal FE twist nematic (TN) type liquid crystal, it has a high contrast and a wide viewing angle. Although the specific example shown in FIGS. 4, 8 and 9 uses a transparent liquid crystal drive electrode on a transparent substrate,
This is because the conventional park silicon type shown in FIG. 2 has a serious drawback that the FE type (TN type) liquid crystal having the highest contrast among the liquid crystals cannot be used due to the opacity of the substrate, but the method of the specific example of the present invention. According to the above, there is a great advantage that the contrast is dramatically improved as compared with the Parc silicon type. Even if the opaque substrate or the opaque drive electrode is used in the structural example of the present invention, the contrast is not significantly improved by using the GH type or DSM type liquid crystal which is used in the conventional park silicon, but the process is simplified. It is possible to achieve the objectives of increasing the display efficiency, improving the process yield, and preventing the disappearance of the display image due to the leakage due to the incident light.

When a substrate made of glass, quartz or the like is used as in the present invention, the panel can be easily assembled as compared with the conventional panel structure in which parc silicon is used as one electrode of the liquid crystal. Conventionally, a silicon wafer is used instead of the transparent substrate 65 in FIG. Since the silicon wafer is a single crystal, it breaks along the cleavage plane against the pressure during assembly. Further, the warp of the silicon wafer becomes large when it is subjected to a heat process, and the thickness of the liquid crystal body 68 is 5 μm to 15 μm, while the warp is 10 μm.
In many cases, it is difficult to assemble the liquid crystal body with a constant thickness.

Further, although high temperature is applied when the liquid crystal body is sealed,
Since the coefficient of thermal expansion is different from that of the upper glass 66, the seal does not work perfectly. On the other hand, if the substrate of the lower electrode is glass or a glass similar to that of the present invention as in the present invention, all of these problems are solved, and as with a normal liquid crystal panel, the assembly can be smoothly carried out with a good yield.

The data holding capacity in the present invention is used to hold the display data of the cell portion for a certain period of time, and is about 16 msec for a television image, for example. If the leakage current of silicon thin film transistor is 10V, it is 1
If it is less than 00 PA, the capacity of this holding capacitor is 0.5 PF to 1 PF. If the liquid crystal has a high relative dielectric constant, especially 10 or more, and the thickness of the liquid crystal is 10 or less.
If the thickness is less than μm, the capacitance of the liquid crystal as a dielectric is 0.5.
Since it becomes PF or more, the charge holding capacitor becomes unnecessary. Then, in the upper part of FIG. 3, the GND line and the capacitor 18 can be omitted, the effective liquid crystal driving area is increased, the contrast can be improved, and an extra element is eliminated, which leads to the improvement of the yield 1. At this time, the sample-hold capacitance of the data line Y is mainly the parasitic capacitance 22 at the intersection of the data line and the address line.

The transistor constructed according to the present invention comprises:
An external drive circuit for an active matrix, that is, a shift register and a sample hold circuit can be formed on the same substrate.

FIG. 11 shows an example of a drive circuit on the gate line side used in the present invention. The shift register cell 80 includes four transistors 81 to 84 and one put-stove capacitor 8
5 is comprised. The clock has two phases of φ1 and φ2, and the “1” potential is sequentially transferred by the input of the start pulse SP in synchronization with the clock. Output D of each shift register
1 to Dm are input to the gate lines, and as a result, as shown in FIG. 12, each gate line is sequentially selected. An input transfer gate transistor 81 is used as an input to the shift register, one is stored in T1 to TN, and then "1" is written to D1 to Dm by the boot strap capacitance. If this transfer gate is not used, D1 and T2, D2 and T, ... Are short-circuited, and it is necessary to make the boot strap capacitance larger than the gate line capacitance CGi, and the pattern is large and the yield is reduced. . Also D1 to Dm "
In order to discharge to "0" after being written to "1", it is only necessary to connect T3 to the transistor 84. However, when this shift register operates at a low frequency, even a slight leak causes malfunction. Therefore, in order to improve the yield and stabilize the operation, the potential fixing transistor 83 is added, and the voltage is refreshed to the "0" level every half cycle of the clock.

FIG. 13 shows an example of the drive circuit on the data line side according to the present invention. The shift register cell 86 includes a boot strap capacitor 88 and transistors 89 and 91 necessary for operation.
And a reset transistor 90 for selecting a shift register, which will be described later, and a start pulse SP is applied to the first stage via an input gate 87. The output 81 to Sm of each shift register is the sample hold transistor H1.
~ Hm input to the video input V in synchronization with the scanning signal,
S (video signal or data write signal) is sampled and held by the capacitors CD1 to CDm parasitic on the data line.
The data line side drive circuit is high-speed because all the processing is performed within one scanning line, and it is not necessary to consider the leak current, but on the contrary, ensuring high-speed operation and increasing consumption due to high speed It is necessary to consider saving power.

Since only 1 bit out of m bits is "1" in this shift register, power consumption other than the clock is small. Sample-and-hold transistors H1 to
A fairly high-speed switching of Hm is required, but since the gate input is applied with an amplitude close to twice that of the clock signal as shown in FIG. 14, there is an advantage that the switching can be performed at a very high speed. .

FIG. 15 shows a case where these are actually arranged on the active matrix substrate. There are data-side shift registers 90 and 91, dummy cells 94 and 95 that form the final stage feedback signal, and sample-hold transistors H1 to Hm, which are arranged in a vertically symmetrical manner. The gate-side shift resists 92 and 93 and the dummies 96 and 97 are arranged symmetrically. Originally, the peripheral circuit does not need to be symmetrical on both sides, and only one may be used, but a plurality of shift register arrays are prepared in consideration of the yield. Of course, it may be 4 columns or 8 columns, but here, an example of 2 columns is shown.

The following advantages can be obtained by forming the drive circuit shown in FIG. 15 with a transistor using a silicon thin film as in the present invention. First, especially on the data line side, since the clock frequency is as high as several MHz, the amount consumed by the parasitic capacitance of the clock line is larger than the internal power consumption of the shift register. Particularly, in the case of park silicon, the wiring capacitance of the clock line and the junction capacitance with the substrate are 10 OPF or more, and the clock speed is reduced, resulting in power consumption of 10 mA or more. However, this parasitic capacitance is several P on an insulating substrate as in the present invention.
It is F, and the power consumption can be extremely reduced and the speed can be improved. Next, in the case of parc silicon, for example, FIG.
If the potential of the source amount of the transistor 82 rises, the back gate effect increases the squiggle value. As a result, it is necessary to increase the voltage of the gate T1 of the transistor 82 in order to obtain the required signal voltage, and eventually the signal level of the clock is increased or the area of the boot strap capacitor 85 is considerably increased. However, in the structure of the present invention, the substrate of the transistor is float ink,
Therefore, the back gate effect does not occur. Therefore, since the clock amplitude may be small, the power consumption may be reduced and the boot strap passenger may be small in a small area. The bootstrap capacitance in the peripheral drive circuit of the present invention is different from the charge retention capacitor and basically uses an insulating film between a gate and a channel forming a transistor. This means that the bootstrap capacitance needs to have a variable interelectrode capacitance depending on the gate voltage as the upper electrode, and therefore the lower electrode of the capacitance is made of a low-concentration or non-dove silicon film.

As described above, if the active matrix cell portion and the peripheral drive portion are simultaneously formed on the insulating substrate by using the silicon thin film, the connection is facilitated and the overall cost is reduced. Further, considering that the peripheral drive circuit is configured by a non-inversion type ratioless shift register as shown in FIGS. 11 and 13 and the parasitic capacitance is gradually reduced, it is possible to reduce the total power consumption. At the same time, yield improvement and cost reduction can be realized.

[0033]

As described above, the present invention provides an active matrix having a silicon transistor and a silicon capacitor on a substrate, and has the following advantages over conventional ones.

When the transparent liquid crystal drive is used for the transparent substrate, the FE type liquid crystal having the highest contrast can be used, the brightness of the screen can be improved, and the display quality can be dramatically improved.

At the same time, when glass or a material similar thereto is used for the substrate, the panel can be easily assembled, the assembly yield is improved and the process is simplified as compared with the conventional bulk silicon type.

When an active matrix peripheral drive circuit is mounted, the power consumption can be greatly reduced.

As described above, in the present invention, liquid crystal is enclosed in a pair of substrates, and the substrate is a quartz or glass substrate, and the first conductive layer provided on the substrate and the first conductive layer provided on the first conductive layer. Obtained insulating film, silicon semiconductor film provided on the insulating film layer, source and drain diffusion regions provided in the silicon semiconductor film, and electrically connected to the semiconductor film provided on the insulating layer Since the charge storage capacitor is formed by the pixel electrode and the first conductive layer, the image signal inputted to the pixel electrode can be surely held, and the liquid crystal material Even if the resistance of the liquid crystal changes and the time constant of the liquid crystal changes due to the change of, the video signal can be held regardless of this change.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a cell used in a conventional active matrix.

FIG. 2 is a plan view of a cell using bulk silicon.

FIG. 3 is a cell diagram of the present invention.

FIG. 4 is a plan view and a cross-sectional view of an implementation example thereof.

FIG. 5 is a view showing the manufacturing process thereof.

FIG. 6 is a diagram showing characteristics of a silicon thin film.

FIG. 7 is a diagram showing characteristics of a silicon thin film.

FIG. 8 is a diagram showing another implementation example of the present invention.

FIG. 9 is a diagram showing another implementation example of the present invention.

FIG. 10 is a sectional view of the active matrix panel of the present invention when assembled.

FIG. 11 is a diagram showing an example of a peripheral drive circuit used in the present invention.

FIG. 12 is an operation waveform diagram thereof.

FIG. 13 is a diagram showing an example of a peripheral drive circuit used in the present invention.

FIG. 14 is an operation waveform diagram thereof.

FIG. 15 is a diagram showing an example of a peripheral drive circuit used in the present invention.

[Explanation of symbols]

11 ... Polysilicon upper electrode of capacitor 3 ... Polysilicon gate 7, 8, 9 ... Contact hole 13 ... Al drive electrode 30, 40, 51, 53, 72, 73 ... First-layer silicon thin film 26, 45 , 50, 52, 75 ... Second-layer silicon thin film 30, 44, 54, 78 ... Channel 33, 57, 70 ... Substrate 62, 635 ... Polarizing plate 64 ... Reflecting plate 65, 66 ... Transparent substrate 69 ... Nesa film 67 ... Polysilicon drive electrode 68 ... Liquid crystal body 76, 77 ... Al 36, 41, 55, 74 ... Gate insulation film 37, 46 ... Capacitor insulation film 25, 31 ... Transparent low resistance body 85/88 ... Bootstrap capacity 89 ... Active matrix 90, 91, 92, 93 ... Shift register

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[Procedure amendment]

[Submission date] September 19, 1996

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction contents]

[Document Name] Statement

Title: Method for manufacturing liquid crystal device

[Claims]

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a liquid crystal device for a display using a thin film transistor.

[0002]

2. Description of the Related Art Conventionally, a display panel using an active matrix has attracted attention as a method capable of realizing a large-sized panel having a large number of dots because its matrix size can be made very large as compared with the dynamic method. In particular, a light-receiving element such as a liquid crystal has a limited drive duty in a dynamic system, and application of an active matrix is considered for a television display and the like. FIG. 1 shows one cell of a conventional active matrix. The address line X is input to the gate of the transistor 2, and the transistor is turned on to cause the signal on the data line Y to be stored as charge in the holding capacitor 3. Until data is written again, it is held by the capacitor 3 and simultaneously drives the liquid crystal 4. Here, VC is a common electrode signal. Since the leakage of the liquid crystal is very small, it is enough to hold the charge for a short time.

The manufacture of the transistor and the capacitor 1 is completely suitable for the process of a normal IC.

FIG. 2 shows an example in which the cell of FIG. 1 is formed by a silicon gate process. A transistor 10 and a capacitor 11 are formed on a single crystal silicon wafer. The address line X and the upper electrode 11 of the capacitor are made of polycrystalline silicon (polysilicon).
Is formed of aluminum (Al), and the contact holes 7, 8 and 9 connect the substrate to Al and the polysilicon to Al, respectively.

[0005]

The matrix substrate according to the conventional IC process has the following major drawbacks.

Since the manufacturing process of the matrix substrate is the same as that of the IC, a step of performing a heat treatment at about 1000 ° C. is included in the process, and these high temperature processes limit the element materials and substrate materials. In particular, when the display becomes large, it is essential to use inexpensive glass for the substrate, which is difficult with the current high temperature process.

[0007]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for remedying this drawback, and the structure of the present invention is to form a thin film transistor having a silicon thin film as a channel on a glass substrate.

According to the present invention, liquid crystal is sealed between a pair of substrates, one of the pair of substrates is made of a transparent glass substrate, and the pixel electrodes and the pixels are formed in a matrix on the transparent glass substrate. In a method of manufacturing a liquid crystal device, which comprises a thin film transistor connected to an electrode,
Forming a silicon thin film forming the thin film transistor on the transparent glass substrate; forming the silicon thin film, irradiating the entire glass substrate with a laser beam or an electron beam to anneal the silicon thin film; And assembling the liquid crystal panel with the glass substrate and the other substrate of the pair of substrates facing each other.

[0009]

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 3 shows a matrix cell used in the present invention. The difference from the conventional one in FIG.
The difference is that the GND wiring of the capacitor 18 is newly provided, but the basic writing and holding of data is the same.
In this case, the GND potential means a constant bias voltage, regardless of the bias level or the signal level. Further, the capacitance 21 between the data line Y and the GND line or the capacitance 22 between the data line and the address line X is used as the capacitance for the data line Y to sample and hold the input of the display data.

FIG. 4A is a plan view of the cell, and FIG.
A sectional view at B is shown. On the transparent substrate 33, the first-layer silicon thin film 28 forming the source / drain / channel of the transistor and the second-layer silicon thin film forming the gate line to be the gate of the transistor or the wiring layer 26 and the GND line equivalent thereto. 27, a transparent low resistance material, for example, a Nesa film such as SnO ₂ , a data line 25 made of a metal or the like having a thickness of 100 angstroms or less, a liquid crystal drive electrode 31, and a contact hole 29 for establishing conduction between layers. There is. Further, the overlapping portion of the GND line 27 and the liquid crystal drive electrode becomes a charge holding capacitor (FIG. 3-18). N is added to the source / drain 34/35 of the transistor.
⁺ Diffusion channel 30 under the (P-channel if P ⁺⁾ is made the gate electrode 38 is formed via a gate insulating film 36, and insulating film 37 further oxide film or the like around the gate electrode is formed .

The feature of the configuration example shown in FIG. 4 is that the gate insulating film of the transistor is formed by oxidizing the first silicon thin film or forming it on the silicon thin film, and performing gate self-alignment using the gate as a mask. Although such a silicon thin film has a lower mobility and a lower speed than a single-crystal bulk silicon element, the speed deterioration can be prevented by making the parasitic capacitance self-aligning and reducing the parasitic capacitance. The other is a charge holding capacitor (Fig. 3-18) and a data line sample-hold capacitor (Fig. 3-21, 2).
The oxide film of the second silicon thin film or the insulating film on the thin film is used as the dielectric film of the capacitor forming 2).

In the conventional bulk silicon type (FIG. 2), a bulk silicon thermal oxide film is used for the gate insulating film and the charge storage capacitor of the transistor. However, the impurity self-doping is shown in FIG. 5B. In the case of the align method, high-concentration impurities do not enter under the second-layer silicon thin film that forms one electrode of the capacitance, and if it is left as it is, the capacitance becomes unstable and it is difficult to use. As described above, an extra step of doping a high-concentration impurity only in the lower electrode of the capacitor is required. Therefore, as shown in FIG. 4, by forming the dielectric film for forming the holding capacitor on the second silicon thin film, it is possible to simplify the process and stabilize the capacitor, which is the object of the present invention. Become.

FIG. 5 shows a manufacturing process of the active matrix cell shown in FIG. There are basically two types of manufacturing processes, a low temperature process and a high temperature process, and each has its own characteristics. In the low temperature process, glass or a high melting point glass such as Pyrex or Corning is used as a transparent substrate, and it is a process step at 600 ° C. or less, and the substrate itself is inexpensive. First, the low temperature process of the active matrix cell shown in FIG. 4 will be described with reference to FIG. In the low temperature process, first, a silicon thin film is formed on the substrate 33 by a CVA method such as a plasma CVD method or a low pressure CVD method,
It is formed by a sputtering method or the like, and is photo-etched into a required shape. Then, the surface is oxidized in a 0 ₂ plasma atmosphere.

Also, an equivalent insulating film may be deposited by the CVD method. As a result, an oxide film 41 serving as a gate insulating film is formed on the silicon thin film 40. (FIG. 5 (a)) After that, the second-layer silicon thin film is devoted and photo-etched in the same manner as the first-layer silicon thin film, and then the second-layer silicon thin film 45 is used as a mask to form an oxide film 41.
Are simultaneously etched to form a gate insulating film 41, a diffusion window is opened at the same time, and diffusion is performed by ion implantation to form source / drain 42/43. (FIG. 5 (b)) After that, plasma treatment is again performed in an atmosphere of 0 ₂ to form a plasma oxide film 46 on the surface, and 400 ° C. to 6 ° C.
Annealing is performed at 00 ° C. (FIG. 5 (c)) The feature of this process is that the silicon thin film is directly oxidized by plasma treatment. As a gate insulating film of a transistor and a derivative film for a capacitor, it moves as compared with the oxide film of the CVD method. The degree is improved and the reliability is improved.

The high temperature process will be described for reference.

The high temperature process uses a transparent substrate having a melting point of 600 ° C. or higher, such as quartz, and the manufacturing process has steps exceeding 600 ° C. This process is characterized by high temperature annealing and the like, so that the mobility of the transistor is high. And reliability can be improved. Since the structure of the transistor is the same as that in the low temperature process, it will be described again with reference to FIG.

(A) First, a first-layer silicon thin film is formed on the transparent substrate 33 by a reduced pressure or atmospheric pressure CVD method or the like, and is patterned to form an island portion 40, and then 900 ° C. to 1 ° C.
Oxidation film 41 is formed by thermal oxidation between 100 ° C.
(B) After that, the second layer of silicon thin film is deposited in the same manner as the first layer, the gate electrode 45 is patterned, and the insulating film 41 is etched using this as a mask.
Pre-deposition of N ⁺ or P ⁺ impurities or ion implantation of impurities is performed without etching the insulating film 41 to form source drains 42 and 43. (C) Thereafter, a thermal oxide film 46 serving as a dielectric film of the holding capacitor is formed in the same manner as the gate insulating film.

The steps after FIG. 5 (c) are almost common to both low temperature and high temperature processes. A material that also serves as a wiring and a transparent driving electrode by forming a contact hole for making a contact between the wiring portion and the first layer and the second layer, a negative film, and a thickness of 10
Photo-etching is performed by applying a metal or the like having a thickness of 0 Å or less by sputtering or vapor deposition. If it is difficult to directly contact the silicon thin film such as the Nesa film, Au ・ Ni
-A contact-specific material such as Cr is added to the contact portion.

The transistor formed according to the method of the present invention has a lower mobility and a larger amount of OFF leakage than a transistor formed on bulk silicon.

FIG. 6A shows the silicon thin film of the first layer,
It shows the mobility at 10V of a transistor formed by a low pressure CVD apparatus while changing the devolution temperature and formed by a high temperature process. It was found by experiments that the mobility sharply improves when the deposition temperature becomes 600 ° C. or lower. Therefore, first, as a first point, in order to improve the mobility and ensure the response, a low pressure CVD apparatus is used.
It is advisable to form the first silicon thin film at a temperature of 00 ° C. or lower.

FIG. 7 shows the OF of the transistor at 10V.
The F leak current Ic is plotted by changing the film thickness of the silicon thin film of the first layer. The inventor has determined by experiment that
It was found that at a film thickness of 700 angstroms or less, the leak current is 500 pA or less, which is not a problem for use.

Not only in the high temperature process, but especially in the low temperature process, the mobility is drastically reduced. Another improvement means for this may be to anneal the silicon thin film of the first layer at a high temperature so that the substrate is not affected by the laser or electron beam. FIG. 6 (B) shows that a silicon thin film formed in the same machine as (A) as described above has 0.12 m per pulse.
J is the mobility of the fresh transistor obtained by irradiating the laser beam by the Q switch having the pulse width Sonsec, and it can be seen that the mobility is further improved. Also 500 ℃ ~ 5
The mobility of the transistor by the low temperature process obtained by performing laser annealing under the same conditions after depositing on the high melting point glass at 40 ° C. almost matched the curve of FIG. 6B. From this, it is understood that the annealing by the laser beam, the electron beam, etc. is effective in both the low temperature process and the high temperature process.

(Embodiment 2) FIG. 8 shows another structural example of the cell. (A) is a plan view in which an address line 50 is a gate of a channel 54 of a transistor having a data line 51, a drive electrode and a capacitor electrode 52 as a source / drain. The GND line 53 is formed at the same time as the address line 50 and forms a capacitance between the GND line 53 and the electrode 52.

FIG. 8B is a sectional view taken along the line AB of FIG. 8A. As an example of a manufacturing process, a high temperature process will be described. Grow silicon to about 3000 Angstroms. However, in some cases, thin SiO ₂ may be formed in advance in order to improve the adhesion. Further, after forming the gate 50 and the capacitor electrode 53 by photo etching, a SiO ₂ film 55 of about 1500 angstrom is grown as a gate insulating film and a dielectric film of the capacitor by thermal oxidation. After that, a second layer of polysilicon is attached and a pattern is formed by photoetching, and then P ions are implanted into a portion other than the channel portion 54 by a resist mask to form a source / drain electrode and a wiring portion of the data line
A liquid crystal drive electrode that also functions as a capacitor electrode is formed.
As it is, the performance (transmission value, conductance) of the transistor is insufficient. Therefore, by uniformly irradiating the entire substrate with a laser and welding and solidifying the polysilicon in a short time to grow the grain, Make improvements. This is what is called laser annealing.

The structure shown in FIG. 8 can of course be realized by a low temperature process. The feature of this structure is that, contrary to FIG. 4, the transistor gate uses the first layer of silicon thin film and the channel uses the second layer of silicon thin film. Concentration diffusion becomes possible, and a gate oxide film obtained by oxidizing the first silicon thin film is used as a gate insulating film on the first silicon film.
A derivative film for forming a capacitor for holding a charge can be used, and a process of forming an oxide film is completed in one process. Another feature is that even if a new wiring material is not provided as shown in FIG.
The first layer of silicon film serves as an address line and a GND line, and the second layer of silicon film serves as a data line wiring. This eliminates the step of depositing a wiring material and photoetching the structure example of FIG. The process is simplified. In this method, a silicon film is used as a transparent drive electrode of liquid crystal, and the silicon film is sufficiently transparent when the film thickness is 3000 angstroms or less.

(Embodiment 3) FIG. 9 shows a cross section by a low temperature process in which cells are formed on a normal glass substrate as another example of the present invention. A silicon film is formed on the glass substrate 70 by a low-temperature film formation method such as a sputtering method or a plasma CVD method, and P ions or B ions are implanted over the entire surface. Next, a gate 73 and a capacitor electrode 72 are formed by photo etching. Further, an insulating film 74 is formed. We are also still used Si0 ₂ or the like amounting to low-temperature growth. Further, a second-layer silicon film serving also as a source / drain of the transistor, a capacitor and a drive electrode is formed at a low temperature. This polysilicon is not doped at all, or is implanted with a sufficient amount of B ions to enhance the threshold value.
After that, the whole is irradiated with a laser beam and annealed. Part of the laser beam is absorbed by the first layer of silicon,
The glass substrate 70 is transparent. Therefore, the activation of the ion-implanted impurities in the first layer of silicon and the growth of the grains of the second layer of polysilicon (in particular, the channel portion 78) are carried out at an appropriate beam energy and an appropriate time (with a pulse laser). If so, the annealing can be performed within a range that has almost no effect on the glass substrate by performing processing at a pulse interval and with a CW laser depending on the scanning speed). The feature of this method is that laser annealing can reduce the influence of the conventional thermal annealing on the glass substrate, so that glass with low cost can be used. It is possible at the same time to grow the grain of the film and improve the characteristics of the transistor (in particular the mobility).

After that, Al is applied and photoetching is performed to form source / drain electrodes 76 and 77. Since it is difficult to make contact between Al and silicon as they are, a little heat treatment or a weak laser beam may be applied thereafter.

FIG. 10 shows a simple cross section of a liquid crystal display device using the matrix substrate of the present invention. A liquid crystal 68 is sandwiched between a transparent substrate 65 on which a transparent driving electrode 67 is mounted and a glass 66 on which a common electrode 69 made of a Nesa film is mounted. Furthermore, after polarizing with the polarizing plates 62 and 63, the reflector 6 is placed on the lower side.
Turn on 4. In this way, most of the light incident from above passes through the electrode 67, is reflected by the reflector 64, and is sensed by the human eye. Since this system can use a normal FE twist nematic (TN) type liquid crystal, it has a high contrast and a wide viewing angle. Although the specific example shown in FIGS. 4, 8 and 9 uses a transparent liquid crystal drive electrode on a transparent substrate,
This is because the conventional park silicon type shown in FIG. 2 has a serious drawback that the FE type (TN type) liquid crystal having the highest contrast among the liquid crystals cannot be used due to the opacity of the substrate, but the method of the specific example of the present invention. According to the method, there is a great advantage that the contrast is dramatically improved as compared with the bulk silicon type. Even if the opaque substrate or the opaque drive electrode is used in the structural example of the present invention, the contrast is not significantly improved by using the GH type or DSM type liquid crystal which is used in the conventional park silicon, but the process is simplified. It is possible to achieve the objectives of increasing the display efficiency, improving the process yield, and preventing the disappearance of the display image due to the leakage due to the incident light.

When the glass substrate is used as in the present invention, the panel can be easily assembled as compared with the conventional panel structure in which the parc silicon is used as one electrode of the liquid crystal. Conventionally, FIG.
In place of the transparent substrate 65, a silicon wafer is used.
Since the silicon wafer is a single crystal, it breaks along the cleavage plane against the pressure during assembly. Further, the warp of the silicon wafer becomes large when it is subjected to a heating process, and the thickness of the liquid crystal body 68 is often 5 μm to 15 μm, whereas the warp is often 10 μm or more, and it is difficult to assemble the liquid crystal body with a constant thickness. .

High temperature is applied when the liquid crystal is sealed,
Since the coefficient of thermal expansion is different from that of the upper glass 66, the seal does not work perfectly. On the other hand, if the substrate of the lower electrode is glass or a glass similar to that of the present invention as in the present invention, all of these problems are solved, and as with a normal liquid crystal panel, the assembly can be smoothly carried out with a good yield.

The data holding capacity in the present invention is used to hold the display data of the cell portion for a certain period of time, and is about 16 msec for a television image, for example. If the leakage current of silicon thin film transistor is 10V, it is 1
If it is less than 00 pA, the capacity of this holding capacitor is 0.5 PF to 1 PF. If the liquid crystal has a high relative dielectric constant, especially 10 or more, and the thickness of the liquid crystal is 10 or less.
If the thickness is less than μm, the capacitance of the liquid crystal as a dielectric is 0.5.
Since it becomes PF or more, the charge holding capacitor becomes unnecessary. Then, in the upper part of FIG. 3, the GND line and the capacitor 18 can be omitted, the effective liquid crystal driving area is increased, the contrast can be improved, and an extra element is eliminated, which leads to the improvement of the yield 1. At this time, the sample-hold capacitance of the data line Y is mainly the parasitic capacitance 22 at the intersection of the data line and the address line.

A transistor constructed according to the present invention is
An external drive circuit for an active matrix, that is, a shift register and a sample hold circuit can be formed on the same substrate.

FIG. 11 shows an example of a drive circuit on the gate line side used in the present invention. The shift register cell 80 includes four transistors 81 to 84 and one put-stove capacitor 8
5 is comprised. The clock has two phases of φ1 and φ2, and the “1” potential is sequentially transferred by the input of the start pulse SP in synchronization with the clock. Output D of each shift register
_{1 to} D _m are input to the gate lines, and as a result, as shown in FIG. 12, each gate line is sequentially selected. An input transfer gate transistor 81 is used as an input to the shift register, and one is stored in T _{1 to} T _N , and then “1” is written to D _{1 to} Dm by the boot strap capacitance. If this transfer gate is not used, D ₁ and T ₂ , D ₂ and T, ...
And the boot strap capacitance is gate line capacitance CG
It needs to be larger than i, and the pattern is large, which reduces the yield.

[0036] Also after it is written to the "1" of the D ₁ to D _m '
In order to discharge it to 0 ″, it suffices to connect T ₃ to the transistor 84, but when this shift register operates at a low frequency, even a slight leak causes a malfunction, so that the yield is improved, In order to stabilize the operation, a potential fixing transistor 83 is added, and the potential is fixed to "0" level every half cycle of the clock.

FIG. 13 shows an example of the drive circuit on the data line side according to the present invention. The shift register cell 86 includes a boot strap capacitor 88 and transistors 89 and 91 necessary for operation.
And a reset transistor 90 for selecting a shift register, which will be described later, and a start pulse SP is applied to the first stage via an input gate 87. The output 81 to Sm of each shift register is the sample and hold transistor H ₁
~ H _m input to the video input V in synchronization with the scanning signal,
S (video signal or data write signal) is sampled and held by the capacitors C _{D1 to} C _Dm parasitic on the data line. The data line side drive circuit is fast because all the processing is performed within one scanning line, so it is not necessary to consider the leak current.
On the contrary, it is necessary to consider ensuring high-speed operation and suppressing power consumption that increases due to high speed.

Since only 1 bit out of m bits is "1" in this shift register, power consumption other than the clock is small. Sample and hold transistor H ₁ ~
H _{m A} fairly high speed switching is required, but since the gate input is applied with an amplitude close to twice that of the clock signal as shown in FIG.
It has the advantage of being able to switch at a very high speed.

FIG. 15 shows a case where these are actually arranged on the active matrix substrate. There are data-side shift registers 90 and 91, dummy cells 94 and 95 that form the final stage feedback signal, and sample-hold transistors H1 to Hm, which are arranged in a vertically symmetrical manner. The gate-side shift resists 92 and 93 and the dummies 96 and 97 are arranged symmetrically. Originally, the peripheral circuit does not need to be symmetrical on both sides, and only one may be used, but a plurality of shift register arrays are prepared in consideration of the yield. Of course, it may be 4 columns or 8 columns, but here, an example of 2 columns is shown.

The following advantages can be obtained by forming the drive circuit shown in FIG. 15 with a transistor using a silicon thin film as in the present invention. First, especially on the data line side, since the clock frequency is as high as several MHz, the amount consumed by the parasitic capacitance of the clock line is larger than the internal power consumption of the shift register. Particularly, in the case of park silicon, the wiring capacitance of the clock line and the junction capacitance with the substrate are 10 OPF or more, and the clock speed is reduced, resulting in power consumption of 10 mA or more. However, this parasitic capacitance is several P on an insulating substrate as in the present invention.
It is F, and the power consumption can be extremely reduced and the speed can be improved. Next, in the case of parc silicon, for example, FIG.
If the potential of the source amount of the transistor 82 rises, the back gate effect increases the squiggle value. As a result, it is necessary to increase the voltage of the gate T1 of the transistor 82 in order to obtain the required signal voltage, and eventually the signal level of the clock is increased or the area of the boot strap capacitor 85 is considerably increased. However, in the structure of the present invention, the substrate of the transistor is float ink,
Therefore, the back gate effect does not occur. Therefore, since the clock amplitude may be small, the power consumption may be reduced and the boot strap passenger may be small in a small area. The bootstrap capacitance in the peripheral drive circuit of the present invention is different from the charge retention capacitor and basically uses an insulating film between a gate and a channel forming a transistor. This means that the bootstrap capacitance needs to have a variable interelectrode capacitance depending on the gate voltage as the upper electrode, and therefore the lower electrode of the capacitance is made of a low-concentration or non-dove silicon film.

As described above, when the active matrix cell portion and the peripheral drive portion are simultaneously formed on the insulating substrate by using the silicon thin film, the connection becomes easy and the overall cost is reduced. Further, considering that the peripheral drive circuit is configured by a non-inversion type ratioless shift register as shown in FIGS. 11 and 13 and the parasitic capacitance is gradually reduced, it is possible to reduce the total power consumption. At the same time, yield improvement and cost reduction can be realized.

[0042]

As described above, according to the present invention, a silicon thin film forming a thin film transistor connected to a pixel electrode of an active matrix by using a silicon thin film on a transparent glass substrate is provided with a laser beam or an electron beam thereafter. Since it is annealed by irradiating the entire surface, a laser beam or an electron beam can be applied to every corner of the silicon, and the grains of the silicon layer can be uniformly grown. As a result, the characteristics of the thin film transistors connected to the pixel electrodes can be made uniform.

Further, by irradiating the entire transparent glass substrate with a laser beam or an electron beam, the entire substrate is uniformly heated, and the effects of distortion, warpage, deformation, etc. of the glass substrate due to heat can be prevented. Have.

Further, as described above, since it is possible to prevent the influence of distortion, warpage, deformation, etc. of the glass substrate, when the transparent glass substrate irradiated with the laser beam or the electron beam and the counter substrate are bonded together, misalignment is caused. Can be prevented.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a cell used in a conventional active matrix.

FIG. 2 is a plan view of a cell using bulk silicon.

FIG. 3 is a cell diagram of the first embodiment of the present invention.

4A and 4B are a plan view and a cross-sectional view thereof.

5A, 5B, and 5C are views showing the manufacturing process.

FIG. 6 is a diagram showing characteristics of a silicon thin film.

FIG. 7 is a diagram showing characteristics of a silicon thin film.

8A and 8B are cell configuration diagrams of a second embodiment of the present invention.

FIG. 9 is a cell configuration diagram of a third embodiment of the present invention.

FIG. 10 is a sectional view of the active matrix panel of the present invention when assembled.

FIG. 11 is a diagram showing an example of a peripheral drive circuit used in the present invention.

FIG. 12 is an operation waveform diagram thereof.

FIG. 13 is a diagram showing an example of a peripheral drive circuit used in the present invention.

FIG. 14 is an operation waveform diagram thereof.

FIG. 15 is a diagram showing an example of a peripheral drive circuit used in the present invention.

[Explanation of reference numerals] 7, 8, 9 ... Contact hole 10 ... Gate electrode 11 ... Upper electrode of capacitor 3 ... Driving electrode 25, 31 ... Transparent low resistance body 26, 45, 50, 52, 75 ... Second-layer silicon thin film 28, 40, 51, 53, 72, 73 ... First-layer silicon thin film 30, 44, 54, 78 ... Channel 33, 57, 70 ... Substrate 36, 41, 55, 74 ... Gate insulating film 62, 63 ... Polarizing plate 64 ... Reflector plate 65, 66 ... Transparent substrate 69 ... Nesa film 67 ... Transparent drive electrode 68 ... Liquid crystal body 76, 77 ... Al 36, 41, 55, 74 ... Gate Insulating film 37, 46 ... Insulating film for capacitance 25, 31 ... Transparent low resistance element 85/88 ... Bootstrap capacitance 89 ... Active matrix 90, 91, 92, 93 ... Shift register

Claims (1)

[Claims] 1. A liquid crystal is sealed in a pair of substrates, the substrates being quartz or glass substrates, a first conductive layer provided on the substrates, an insulating film provided on the first conductive layer, A silicon semiconductor film provided on the insulating layer, source and drain diffusion regions provided in the silicon semiconductor film, and a pixel electrode provided on the insulating layer and electrically connected to the semiconductor film, A thin film transistor, wherein a charge holding capacitor is formed by forming a charge holding capacitor by the pixel electrode and the first conductive layer.