JPS6214774Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a vertical output stage DC bias feedback circuit for stabilizing the voltage level of a sawtooth voltage applied to a vertical deflection coil during a scanning period in a vertical deflection circuit of a television receiver.

For example, in a shunt-regulated push-pull (SRPP) circuit using two transistors of the same polarity in the vertical output circuit 3 as shown in the example of FIG. It is connected to the coil 4 and fed back to the vertical drive circuit 2 via a DC bias feedback circuit 8 made up of an integrating circuit. A sawtooth waveform current flows through the vertical deflection coil 4. However, the transistor 6 at the midpoint 7 between the two transistors 5, 6
Since the coupling capacitor 9 is connected in series to the vertical deflection coil 4, the voltage on the side has a pulse-like waveform during the retrace period T1 as shown in FIG. ₂ , and a parabolic waveform during the scanning period _T2. The waveform is as follows. Note that 10 is a variable resistor that corrects linearity.

In this case, the voltage at the intermediate point 7 is a sawtooth wave, which is connected to the vertical drive circuit through an integrator circuit consisting of a capacitor C ₁ and a resistor R ₁ and a time constant circuit consisting of a capacitor C ₂ and a resistor R ₂ in series, as shown in FIG. It is connected to the. Here, the integrating circuit is for smoothing the vertical output voltage, and the time constant circuit is for determining the discharge period.

Further, in the vertical drive circuit, the feedback DC bias is detected by sampling only the retrace period. Therefore, there is no influence of parabolic waveforms generated during the scanning period. But the scanning period
For the voltage T ₂ , the direct current voltage cannot be controlled sufficiently unless it is sufficiently integrated in an integrating circuit and fed back. Therefore, conventionally, the integration time constant, which is expressed as the product of resistance and capacitor, is increased. It is true that when the integration time constant is increased, the parabolic waveform portion of the scanning period T ₂ becomes closer to a DC voltage, improving stability. However, simply increasing the integration time constant causes a phase shift during the retrace period _T1 , which causes a delay in the output voltage and causes vibration in the feedback loop, and also has the disadvantage of causing bounce due to shock when switching channels. There is. It also has the disadvantage of being susceptible to changes in characteristics due to changes in transistor temperature and variations in transistors used.

The present invention provides a vertical output stage DC bias feedback circuit that eliminates the drawbacks of the prior art.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 4 is a circuit diagram showing an embodiment of the DC bias feedback circuit of the present invention. In the DC bias feedback circuit 8 shown in FIG. 1, a resistor R ₃ and a capacitor C ₃ are connected in parallel to the capacitor C ₁ of an integrating circuit consisting of a resistor R ₁ and a capacitor C ₁ , and a resistor R ₂ and a capacitor C ₂ . Insert and add a series circuit with. The capacitor C ₃ sufficiently smoothes the voltage during the scanning period T ₂ of the voltage waveform shown in FIG. 3, and the resistor R ₃
This is to prevent the voltage during the retrace period _T1 from being delayed by the circuitry. This has the effect of preventing vibrations occurring within the feedback loop.

In this circuit, in order to sufficiently increase smoothing during the scanning period T ₂ and to prevent abnormal vibrations, the capacitor _is
It is desirable to make the capacity of C ₃ sufficiently large. Also, in this DC bias feedback circuit, the number of stages of the integrating circuit is not limited to two in series as shown in Figure 4, but depending on the constant of the integrating circuit, even a single stage integrating circuit as shown in Figure 5 may have a resistance _R3 . The same effect can be obtained by connecting capacitor _C3 .

As described above, according to the present invention, the time constant of the conventional integrating circuit is not only increased, but also a series circuit of a resistor and a large capacitor is added in parallel to the capacitor of the integrating circuit. Therefore, a stable DC bias feedback circuit with reduced vibration due to feedback can be obtained.

[Brief explanation of the drawing]

Figure 1 is a schematic circuit diagram of a conventional DC bias feedback circuit, Figure 2 is a voltage waveform diagram at the midpoint between two transistors on the output side of a vertical output circuit, and Figure 3 is a diagram of DC bias using a conventional integrating circuit. feedback circuit,
FIG. 4 is a circuit diagram showing a DC bias feedback circuit according to an embodiment of the present invention, and FIG. 5 is a circuit diagram showing another embodiment of the present invention. The symbols shown in the drawings indicate the following. 2
... Vertical drive circuit, 3 ... Vertical output circuit,
C ₁ , C ₂ , C ₃ ... Capacitor, R ₃ ... Resistor.

Claims (1)

[Scope of utility model registration request] In a circuit that feeds back bias converted into DC by an integrating circuit consisting of a DC resistor and a parallel capacitor from a vertical output circuit of a television receiver to a vertical drive circuit, the bias circuit is connected to the parallel capacitor constituting the integrating circuit. A vertical output stage DC bias feedback circuit formed by connecting in parallel a series circuit consisting of a resistor to prevent rotation and a smoothing capacitor having a larger capacitance than the parallel capacitor.